MipsInstrInfo.td revision 71ab7a79a74ebb3dad1aac02c5a5c7c2c20b547f
16193c12a1897723c87b41f4e304a8cd04deef2dcDake Gu//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 26193c12a1897723c87b41f4e304a8cd04deef2dcDake Gu// 361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// The LLVM Compiler Infrastructure 461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// 561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// This file is distributed under the University of Illinois Open Source 661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// License. See LICENSE.TXT for details. 761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// 861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// 1061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// This file contains the Mips implementation of the TargetInstrInfo class. 1161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// 1261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 1361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 1461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 1561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 1661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Mips profiles and nodes 1761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 1861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 19572ed31d757c2635ea0a5cdd7ec8a33cd16f77b7Dake Gudef SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 2061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 2161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDTCisSameAs<1, 2>, 2261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDTCisSameAs<3, 4>, 2361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDTCisInt<4>]>; 2461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 2561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 2661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SDT_MipsMAddMSub : SDTypeProfile<0, 4, 2761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 2861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDTCisSameAs<1, 2>, 2961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDTCisSameAs<2, 3>]>; 3061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SDT_MipsDivRem : SDTypeProfile<0, 2, 3161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDTCisInt<0>, 3261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDTCisSameAs<0, 1>]>; 3361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 3461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 3561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 3661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 378e3566285de4ac771d6188f62fe947e23d371a3dKris Giesing 3861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 3961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 4061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 4161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 4261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDTCisSameAs<0, 4>]>; 4361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 4461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SDTMipsLoadLR : SDTypeProfile<1, 2, 4561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDTCisInt<0>, SDTCisPtrTy<1>, 4661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDTCisSameAs<0, 2>]>; 4761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 4861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Call 4961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 5061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu SDNPVariadic]>; 5261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 5361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Tail call 5461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 5561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 5661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 5761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Hi and Lo nodes are used to handle global addresses. Used on 5861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 5961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// static model. (nothing to do with Mips Registers Hi and Lo) 6061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 6161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 6261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 6361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 6461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// TlsGd node is used to handle General Dynamic TLS 6561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 6661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 6761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// TprelHi and TprelLo nodes are used to handle Local Exec TLS 6861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 6961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 7061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 716193c12a1897723c87b41f4e304a8cd04deef2dcDake Gu// Thread pointer 7261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 7361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 7461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Return 7561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 763f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu 7761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// These are target-independent nodes, but have target-specific formats. 7861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 7961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 8061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 8161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPSideEffect, 8261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDNPOptInGlue, SDNPOutGlue]>; 8361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 8461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// MAdd*/MSub* nodes 8561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 8661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPOptInGlue, SDNPOutGlue]>; 8761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 8861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPOptInGlue, SDNPOutGlue]>; 8961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 9061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPOptInGlue, SDNPOutGlue]>; 9161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 9261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPOptInGlue, SDNPOutGlue]>; 9361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 9461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// DivRem(u) nodes 9561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 9661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPOutGlue]>; 9761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 9861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPOutGlue]>; 9961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 10061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Target constant nodes that are not part of any isel patterns and remain 10161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// unchanged can cause instructions with illegal operands to be emitted. 10261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Wrapper node patterns give the instruction selector a chance to replace 10361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// target constant nodes that would otherwise remain unchanged with ADDiu 10461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// nodes. Without these wrapper node patterns, the following conditional move 10561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 10661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// compiled: 10761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// movn %got(d)($gp), %got(c)($gp), $4 10861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// This instruction is illegal since movn can take only register operands. 10961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 11061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 11161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 11261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 11361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 11461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 11561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 11661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 11761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 11861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 11961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 12061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 12161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 12261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 12361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 12461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 12561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 12661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 12761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 12861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 12961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 13061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 13161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 13261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 13361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 13461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 13561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Mips Instruction Predicate Definitions. 13661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 13761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 13861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureSEInReg">; 13961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef HasBitCount : Predicate<"Subtarget.hasBitCount()">, 14061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureBitCount">; 14161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef HasSwap : Predicate<"Subtarget.hasSwap()">, 14261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureSwap">; 14361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef HasCondMov : Predicate<"Subtarget.hasCondMov()">, 14461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureCondMov">; 14561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 14661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureFPIdx">; 14761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef HasMips32 : Predicate<"Subtarget.hasMips32()">, 14861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureMips32">; 14961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 15061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureMips32r2">; 15161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef HasMips64 : Predicate<"Subtarget.hasMips64()">, 15261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureMips64">; 15361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef NotMips64 : Predicate<"!Subtarget.hasMips64()">, 15461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"!FeatureMips64">; 15561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 15661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureMips64r2">; 15761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef IsN64 : Predicate<"Subtarget.isABI_N64()">, 15861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureN64">; 15961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef NotN64 : Predicate<"!Subtarget.isABI_N64()">, 16061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"!FeatureN64">; 16161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 16261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureMips16">; 16361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 16461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureMips32">; 16561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 16661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureMips32">; 16761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 16861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"FeatureMips32">; 16961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 17061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu AssemblerPredicate<"!FeatureMips16">; 17161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 17261905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass MipsPat<dag pattern, dag result> : Pat<pattern, result> { 17361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Predicates = [HasStdEnc]; 17461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 17561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 17661905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass IsCommutable { 17761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bit isCommutable = 1; 17861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 17961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 18061905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass IsBranch { 18161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bit isBranch = 1; 18261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 18361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 18461905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass IsReturn { 18561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bit isReturn = 1; 18661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 18761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 18861905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass IsCall { 18961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bit isCall = 1; 19061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 19161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 19261905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass IsTailCall { 19361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bit isCall = 1; 19461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bit isTerminator = 1; 1958e3566285de4ac771d6188f62fe947e23d371a3dKris Giesing bit isReturn = 1; 19661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bit isBarrier = 1; 19761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bit hasExtraSrcRegAllocReq = 1; 19861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bit isCodeGenOnly = 1; 19961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 20061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 20161905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass IsAsCheapAsAMove { 20261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bit isAsCheapAsAMove = 1; 20361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 20461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 20561905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass NeverHasSideEffects { 20661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bit neverHasSideEffects = 1; 20761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 20861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 20961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 21061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Instruction format superclass 21161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 21261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 21361905b0b52c50018dcaebcd79699c39b8f28d622Dake Guinclude "MipsInstrFormats.td" 214c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu 21561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 21661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Mips Operand, Complex Patterns and Transformations Definitions. 21761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 21861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 21961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Instruction operand types 22061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef jmptarget : Operand<OtherVT> { 22161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let EncoderMethod = "getJumpTargetOpValue"; 22261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 22361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef brtarget : Operand<OtherVT> { 22461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let EncoderMethod = "getBranchTargetOpValue"; 22561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let OperandType = "OPERAND_PCREL"; 22661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeBranchTarget"; 22761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 22861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef calltarget : Operand<iPTR> { 22961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let EncoderMethod = "getJumpTargetOpValue"; 23061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 23161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef calltarget64: Operand<i64>; 23261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef simm16 : Operand<i32> { 23361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod= "DecodeSimm16"; 23461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 23561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef simm16_64 : Operand<i64>; 23661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef shamt : Operand<i32>; 23761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 23861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Unsigned Operand 23961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef uimm16 : Operand<i32> { 24061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let PrintMethod = "printUnsignedImm"; 24161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 24261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 24361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MipsMemAsmOperand : AsmOperandClass { 24461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Name = "Mem"; 24561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let ParserMethod = "parseMemOperand"; 24661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 24761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 24861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Address operand 24961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef mem : Operand<i32> { 25061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let PrintMethod = "printMemOperand"; 25161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let MIOperandInfo = (ops CPURegs, simm16); 25261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let EncoderMethod = "getMemEncoding"; 25361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let ParserMatchClass = MipsMemAsmOperand; 25461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 25561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 25661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef mem64 : Operand<i64> { 25761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let PrintMethod = "printMemOperand"; 25861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let MIOperandInfo = (ops CPU64Regs, simm16_64); 25961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let EncoderMethod = "getMemEncoding"; 26061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let ParserMatchClass = MipsMemAsmOperand; 26161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 26261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 26361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef mem_ea : Operand<i32> { 26461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let PrintMethod = "printMemOperandEA"; 26561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let MIOperandInfo = (ops CPURegs, simm16); 26661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let EncoderMethod = "getMemEncoding"; 26761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 26861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 26961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef mem_ea_64 : Operand<i64> { 27061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let PrintMethod = "printMemOperandEA"; 27161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let MIOperandInfo = (ops CPU64Regs, simm16_64); 27261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let EncoderMethod = "getMemEncoding"; 27361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 27461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 27561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// size operand of ext instruction 27661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef size_ext : Operand<i32> { 27761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let EncoderMethod = "getSizeExtEncoding"; 27861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeExtSize"; 27961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 28061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 28161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// size operand of ins instruction 28261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef size_ins : Operand<i32> { 28361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let EncoderMethod = "getSizeInsEncoding"; 28461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeInsSize"; 28561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 28661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 28761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Transformation Function - get the lower 16 bits. 28861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef LO16 : SDNodeXForm<imm, [{ 28961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu return getImm(N, N->getZExtValue() & 0xFFFF); 29061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu}]>; 29161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 29261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Transformation Function - get the higher 16 bits. 29361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef HI16 : SDNodeXForm<imm, [{ 29461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 29561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu}]>; 29661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 29761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Node immediate fits as 16-bit sign extended on target immediate. 29861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// e.g. addi, andi 29961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 30061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 30161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Node immediate fits as 15-bit sign extended on target immediate. 30261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// e.g. addi, andi 30361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 30461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 30561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Node immediate fits as 16-bit zero extended on target immediate. 30661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// The LO16 param means that only the lower 16 bits of the node 30761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// immediate are caught. 30861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// e.g. addiu, sltiu 30961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef immZExt16 : PatLeaf<(imm), [{ 31061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu if (N->getValueType(0) == MVT::i32) 31161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 31261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu else 31361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 31461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu}], LO16>; 31561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 31661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 31761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef immLow16Zero : PatLeaf<(imm), [{ 31861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu int64_t Val = N->getSExtValue(); 31961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu return isInt<32>(Val) && !(Val & 0xffff); 32061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu}]>; 32161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 32261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// shamt field must fit in 5 bits. 32361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 32461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 32561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Mips Address Mode! SDNode frameindex could possibily be a match 32661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// since load and store instructions from stack used it. 32761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef addr : 32861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 32961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 33061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 33161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Instructions specific format 33261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 33361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 33461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Arithmetic and logical instructions with 3 register operands. 33561905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0, 33661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstrItinClass Itin = NoItinerary, 33761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDPatternOperator OpNode = null_frag>: 33861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 33961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rd, $rs, $rt"), 34061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> { 34161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isCommutable = isComm; 34261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isReMaterializable = 1; 34361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu string BaseOpcode; 34461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu string Arch; 34561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 34661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 34761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Arithmetic and logical instructions with 2 register operands. 34861905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass ArithLogicI<string opstr, Operand Od, RegisterClass RC, 34961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDPatternOperator imm_type = null_frag, 35061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDPatternOperator OpNode = null_frag> : 35161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16), 35261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rt, $rs, $imm16"), 35361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> { 35461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isReMaterializable = 1; 35561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 35661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 35761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Arithmetic Multiply ADD/SUB 35861905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> : 35961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins CPURegs:$rs, CPURegs:$rt), 36061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rs, $rt"), 36161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul, FrmR> { 36261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Defs = [HI, LO]; 36361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Uses = [HI, LO]; 36461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isCommutable = isComm; 36561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 36661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 36761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Logical 36861905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass LogicNOR<string opstr, RegisterClass RC>: 36961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 37061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rd, $rs, $rt"), 37161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 37261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isCommutable = 1; 37361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 37461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 37561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Shifts 37661905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass shift_rotate_imm<string opstr, Operand ImmOpnd, 37761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu RegisterClass RC, SDPatternOperator OpNode = null_frag, 37861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDPatternOperator PF = null_frag> : 37961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 38061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rd, $rt, $shamt"), 38161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 38261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 38361905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass shift_rotate_reg<string opstr, RegisterClass RC, 38461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDPatternOperator OpNode = null_frag>: 38561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 38661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rd, $rt, $rs"), 38761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>; 38861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 38961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Load Upper Imediate 39061905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 39161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 39261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [], IIAlu, FrmI>, IsAsCheapAsAMove { 39361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let neverHasSideEffects = 1; 39461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isReMaterializable = 1; 39561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 39661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 39761905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 39861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 39961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu bits<21> addr; 40061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Inst{25-21} = addr{20-16}; 40161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Inst{15-0} = addr{15-0}; 40261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeMem"; 40361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 40461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 40561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Memory Load/Store 40661905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 40761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Operand MemOpnd> : 40861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 40961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { 41061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeMem"; 41161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let canFoldAsLoad = 1; 41261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 41361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 41461905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 41561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Operand MemOpnd> : 41661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 41761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 41861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeMem"; 41961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 42061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 42161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gumulticlass LoadM<string opstr, RegisterClass RC, 42261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDPatternOperator OpNode = null_frag> { 42361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 42461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 42561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderNamespace = "Mips64"; 42661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isCodeGenOnly = 1; 42761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu } 42861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 42961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 43061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gumulticlass StoreM<string opstr, RegisterClass RC, 43161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDPatternOperator OpNode = null_frag> { 43261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 43361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 43461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderNamespace = "Mips64"; 43561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isCodeGenOnly = 1; 43661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu } 43761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 43861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 43961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Load/Store Left/Right 44061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gulet canFoldAsLoad = 1 in 44161905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 44261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Operand MemOpnd> : 44361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 44461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rt, $addr"), 44561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 44661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeMem"; 44761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu string Constraints = "$src = $rt"; 44861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 44961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 45061905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 45161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Operand MemOpnd>: 45261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 45361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 45461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeMem"; 45561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 45661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 45761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gumulticlass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 45861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 45961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Requires<[NotN64, HasStdEnc]>; 46061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 46161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Requires<[IsN64, HasStdEnc]> { 46261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderNamespace = "Mips64"; 46361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isCodeGenOnly = 1; 46461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu } 46561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 46661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 46761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gumulticlass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 46861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 46961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Requires<[NotN64, HasStdEnc]>; 47061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 47161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Requires<[IsN64, HasStdEnc]> { 47261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderNamespace = "Mips64"; 47361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isCodeGenOnly = 1; 47461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu } 47561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 47661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 47761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Conditional Branch 47861905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 47961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 48061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rs, $rt, $offset"), 48161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 48261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu FrmI> { 48361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isBranch = 1; 48461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isTerminator = 1; 48561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let hasDelaySlot = 1; 48661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Defs = [AT]; 48761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 48861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 48961905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 49061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins RC:$rs, brtarget:$offset), 49161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rs, $offset"), 49261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 49361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isBranch = 1; 49461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isTerminator = 1; 49561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let hasDelaySlot = 1; 49661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Defs = [AT]; 49761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 49861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 49961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// SetCC 50061905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 50161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 50261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rd, $rs, $rt"), 50361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 50461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 50561905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 50661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu RegisterClass RC>: 50761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 50861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rt, $rs, $imm16"), 50961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>; 51061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 51161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Jump 51261905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 51361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SDPatternOperator targetoperator> : 51461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 51561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(operator targetoperator:$target)], IIBranch, FrmJ> { 51661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isTerminator=1; 51761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isBarrier=1; 51861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let hasDelaySlot = 1; 51961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeJumpTarget"; 52061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Defs = [AT]; 52161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 52261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 52361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Unconditional branch 52461905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass UncondBranch<string opstr> : 52561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 52661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(br bb:$offset)], IIBranch, FrmI> { 52761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isBranch = 1; 52861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isTerminator = 1; 5295ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout let isBarrier = 1; 5305ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout let hasDelaySlot = 1; 5315ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout let Predicates = [RelocPIC, HasStdEnc]; 53261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Defs = [AT]; 5335ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout} 5345ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout 5355ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout// Base class for indirect branch and return instruction classes. 5365ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stoutlet isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 5375ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stoutclass JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 5385ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 5395ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout 5405ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout// Indirect branch 5415ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stoutclass IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 5425ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout let isBranch = 1; 5435ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout let isIndirectBranch = 1; 5445ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout} 5455ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout 5465ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stout// Return instruction 5475ae73b45620a3d535b2d279512d5d34603e2bdb1Craig Stoutclass RetBase<RegisterClass RC>: JumpFR<RC> { 5488e3566285de4ac771d6188f62fe947e23d371a3dKris Giesing let isReturn = 1; 5498e3566285de4ac771d6188f62fe947e23d371a3dKris Giesing let isCodeGenOnly = 1; 5508e3566285de4ac771d6188f62fe947e23d371a3dKris Giesing let hasCtrlDep = 1; 5518e3566285de4ac771d6188f62fe947e23d371a3dKris Giesing let hasExtraSrcRegAllocReq = 1; 55261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 55361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 55461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Jump and Link (Call) 55561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gulet isCall=1, hasDelaySlot=1, Defs = [RA] in { 5568e3566285de4ac771d6188f62fe947e23d371a3dKris Giesing class JumpLink<string opstr> : 55761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 55861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 55961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeJumpTarget"; 56061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu } 56161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 56261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu class JumpLinkReg<string opstr, RegisterClass RC>: 56361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), 56461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(MipsJmpLink RC:$rs)], IIBranch, FrmR>; 56561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 56661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu class BGEZAL_FT<string opstr, RegisterClass RC> : 56761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins RC:$rs, brtarget:$offset), 56861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 56961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 57061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 57161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 57228fe4119471dcc0ccd752c331d6420fcf363f5a5Dake Guclass BAL_FT : 57328fe4119471dcc0ccd752c331d6420fcf363f5a5Dake Gu InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 57428fe4119471dcc0ccd752c331d6420fcf363f5a5Dake Gu let isBranch = 1; 57561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isTerminator = 1; 57661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isBarrier = 1; 5777fd35190a1f0fd92f1275324b23708b5a2087a76Craig Stout let hasDelaySlot = 1; 5787fd35190a1f0fd92f1275324b23708b5a2087a76Craig Stout let Defs = [RA]; 57961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 58061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 58161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Sync 5827fd35190a1f0fd92f1275324b23708b5a2087a76Craig Stoutlet hasSideEffects = 1 in 5837fd35190a1f0fd92f1275324b23708b5a2087a76Craig Stoutclass SYNC_FT : 58461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 58561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu NoItinerary, FrmOther>; 5867fd35190a1f0fd92f1275324b23708b5a2087a76Craig Stout 5877fd35190a1f0fd92f1275324b23708b5a2087a76Craig Stout// Mul, Div 5887fd35190a1f0fd92f1275324b23708b5a2087a76Craig Stoutclass Mult<string opstr, InstrItinClass itin, RegisterClass RC, 5897fd35190a1f0fd92f1275324b23708b5a2087a76Craig Stout list<Register> DefRegs> : 5907fd35190a1f0fd92f1275324b23708b5a2087a76Craig Stout InstSE<(outs), (ins RC:$rs, RC:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 59161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu itin, FrmR> { 59261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isCommutable = 1; 59361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Defs = DefRegs; 59461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let neverHasSideEffects = 1; 59528fe4119471dcc0ccd752c331d6420fcf363f5a5Dake Gu} 59628fe4119471dcc0ccd752c331d6420fcf363f5a5Dake Gu 59728fe4119471dcc0ccd752c331d6420fcf363f5a5Dake Guclass Div<SDNode op, string opstr, InstrItinClass itin, RegisterClass RC, 59861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu list<Register> DefRegs> : 59928fe4119471dcc0ccd752c331d6420fcf363f5a5Dake Gu InstSE<(outs), (ins RC:$rs, RC:$rt), 60061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RC:$rs, RC:$rt)], itin, 60161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu FrmR> { 60261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Defs = DefRegs; 60361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 60461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 60561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Move from Hi/Lo 60661905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 60761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 60861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Uses = UseRegs; 60961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let neverHasSideEffects = 1; 61061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 61161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 61261905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 61361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 61461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Defs = DefRegs; 61561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let neverHasSideEffects = 1; 61661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 61761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 61861905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 61961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 62061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 62161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let isCodeGenOnly = 1; 6228e3566285de4ac771d6188f62fe947e23d371a3dKris Giesing let DecoderMethod = "DecodeMem"; 62361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 62461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 62561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Count Leading Ones/Zeros in Word 62661905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass CountLeading0<string opstr, RegisterClass RC>: 62761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 62861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set RC:$rd, (ctlz RC:$rs))], IIAlu, FrmR>, 62961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Requires<[HasBitCount, HasStdEnc]>; 63034f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stout 63134f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stoutclass CountLeading1<string opstr, RegisterClass RC>: 63234f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stout InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 63334f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stout [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu, FrmR>, 63434f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stout Requires<[HasBitCount, HasStdEnc]>; 63534f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stout 63634f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stout 63734f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stout// Sign Extend in Register. 63834f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stoutclass SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 63934f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stout InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 64034f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stout [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 64134f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stout let Predicates = [HasSEInReg, HasStdEnc]; 64234f3ee7e818a20939ef49abf5509bcfaea5c3db0Craig Stout} 64361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 64461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Subword Swap 64561905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass SubwordSwap<string opstr, RegisterClass RC>: 64661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 64761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu NoItinerary, FrmR> { 64861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Predicates = [HasSwap, HasStdEnc]; 64961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let neverHasSideEffects = 1; 65061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 65161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 65261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Read Hardware 65361905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> : 65461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs CPURegClass:$rt), (ins HWRegClass:$rd), "rdhwr\t$rt, $rd", [], 65561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu IIAlu, FrmR>; 65661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 65761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Ext and Ins 65861905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass ExtBase<string opstr, RegisterClass RC>: 65961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$size), 66061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, " $rt, $rs, $pos, $size"), 66161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$size))], NoItinerary, 66261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu FrmR> { 66361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Predicates = [HasMips32r2, HasStdEnc]; 66461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 66561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 66661905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass InsBase<string opstr, RegisterClass RC>: 66761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ins:$size, RC:$src), 66861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, " $rt, $rs, $pos, $size"), 66961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$size, RC:$src))], 67061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu NoItinerary, FrmR> { 67161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Predicates = [HasMips32r2, HasStdEnc]; 67261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Constraints = "$src = $rt"; 67361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 67461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 67561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 67661905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 67761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 67861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 67961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 68061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gumulticlass Atomic2Ops32<PatFrag Op> { 68161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 68261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 68361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Requires<[IsN64, HasStdEnc]> { 68461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderNamespace = "Mips64"; 68561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu } 68661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 68761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 68861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Atomic Compare & Swap. 68961905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 69061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 69161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 69261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 69361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gumulticlass AtomicCmpSwap32<PatFrag Op> { 69461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 69561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Requires<[NotN64, HasStdEnc]>; 69661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 69761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Requires<[IsN64, HasStdEnc]> { 69861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderNamespace = "Mips64"; 69961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu } 70061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 70161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 70261905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass LLBase<string opstr, RegisterClass RC, Operand Mem> : 70361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 70461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu [], NoItinerary, FrmI> { 70561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeMem"; 70661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let mayLoad = 1; 70761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 70861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 70961905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass SCBase<string opstr, RegisterClass RC, Operand Mem> : 71061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<(outs RC:$dst), (ins RC:$rt, Mem:$addr), 71161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 71261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let DecoderMethod = "DecodeMem"; 71361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let mayStore = 1; 71461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu let Constraints = "$rt = $dst"; 71561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 71661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 71761905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass MFC3OP<dag outs, dag ins, string asmstr> : 71861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 71961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 72061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 72161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Pseudo instructions 72261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 72361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 72461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Return RA. 72561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gulet isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 72661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 72761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 72861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gulet Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 729c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudef ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 730c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu [(callseq_start timm:$amt)]>; 731c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudef ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 732c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu [(callseq_end timm:$amt1, timm:$amt2)]>; 733c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu} 734c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu 7354735bfcd924fec2d694523f34fac5f8151257dc7Dake Gulet usesCustomInserter = 1 in { 736572ed31d757c2635ea0a5cdd7ec8a33cd16f77b7Dake Gu defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 737572ed31d757c2635ea0a5cdd7ec8a33cd16f77b7Dake Gu defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 738572ed31d757c2635ea0a5cdd7ec8a33cd16f77b7Dake Gu defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 739572ed31d757c2635ea0a5cdd7ec8a33cd16f77b7Dake Gu defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 74061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 74161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 74261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 74361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 74461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 74561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 74661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 74761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 74861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 74961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 7504735bfcd924fec2d694523f34fac5f8151257dc7Dake Gu defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 7514735bfcd924fec2d694523f34fac5f8151257dc7Dake Gu defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 7524735bfcd924fec2d694523f34fac5f8151257dc7Dake Gu defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 75361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 75461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 75561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 75661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 75761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 75861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 75961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 76061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 76161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 76261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 76361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 76461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 76561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Instruction definition 76661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 76761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 76861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// MipsI Instructions 76961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 77061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 77161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu/// Arithmetic Instructions (ALU Immediate) 77261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>, 77361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu ADDI_FM<0x9>, IsAsCheapAsAMove; 77461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>; 77561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 77661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 77761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>; 77861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>; 77961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>; 78061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 78161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 78261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu/// Arithmetic Instructions (3-Operand, R-Type) 78361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>; 78461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 78561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 78661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>; 78761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>; 78861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 78961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 79061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>; 79161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>; 79261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 79361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef NOR : LogicNOR<"nor", CPURegs>, ADD_FM<0, 0x27>; 794c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu 79561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu/// Shift Instructions 79661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SLL : shift_rotate_imm<"sll", shamt, CPURegs, shl, immZExt5>, SRA_FM<0, 0>; 79761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SRL : shift_rotate_imm<"srl", shamt, CPURegs, srl, immZExt5>, SRA_FM<2, 0>; 79861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SRA : shift_rotate_imm<"sra", shamt, CPURegs, sra, immZExt5>, SRA_FM<3, 0>; 7998e3566285de4ac771d6188f62fe947e23d371a3dKris Giesingdef SLLV : shift_rotate_reg<"sllv", CPURegs, shl>, SRLV_FM<4, 0>; 80061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SRLV : shift_rotate_reg<"srlv", CPURegs, srl>, SRLV_FM<6, 0>; 801c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudef SRAV : shift_rotate_reg<"srav", CPURegs, sra>, SRLV_FM<7, 0>; 80261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 803c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu// Rotate Instructions 804c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gulet Predicates = [HasMips32r2, HasStdEnc] in { 805c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu def ROTR : shift_rotate_imm<"rotr", shamt, CPURegs, rotr, immZExt5>, 80661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu SRA_FM<2, 1>; 80761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def ROTRV : shift_rotate_reg<"rotrv", CPURegs, rotr>, SRLV_FM<6, 1>; 8088e3566285de4ac771d6188f62fe947e23d371a3dKris Giesing} 80961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 810c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu/// Load and Store Instructions 81161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu/// aligned 812c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudefm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>; 813c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudefm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>; 814c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudefm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>; 815c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudefm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>; 816c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudefm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>; 81761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudefm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>; 81861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudefm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>; 81961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudefm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>; 82061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 82161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu/// load/store left/right 82261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudefm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 82361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudefm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 82461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudefm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 82561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudefm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 82661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 82761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SYNC : SYNC_FT, SYNC_FM; 82861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 82961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu/// Load-linked, Store-conditional 83061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gulet Predicates = [NotN64, HasStdEnc] in { 83161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def LL : LLBase<"ll", CPURegs, mem>, LW_FM<0x30>; 83261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def SC : SCBase<"sc", CPURegs, mem>, LW_FM<0x38>; 83361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 83461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 83561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gulet Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 83661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def LL_P8 : LLBase<"ll", CPURegs, mem64>, LW_FM<0x30>; 83761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def SC_P8 : SCBase<"sc", CPURegs, mem64>, LW_FM<0x38>; 83861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 83961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 84061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu/// Jump and Branch Instructions 84161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 84261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu Requires<[RelocStatic, HasStdEnc]>, IsBranch; 84361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 84461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef B : UncondBranch<"b">, B_FM; 84561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 84661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 84761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 84861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 84961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 85061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 85161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 85261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef BAL_BR: BAL_FT, BAL_FM; 85361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 85461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef JAL : JumpLink<"jal">, FJ<3>; 85561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 85661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef BGEZAL : BGEZAL_FT<"bgezal", CPURegs>, BGEZAL_FM<0x11>; 85761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef BLTZAL : BGEZAL_FT<"bltzal", CPURegs>, BGEZAL_FM<0x10>; 85861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 85961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 86061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 86161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef RET : RetBase<CPURegs>, MTLO_FM<8>; 86261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 86361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu/// Multiply and Divide Instructions. 86461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MULT : Mult<"mult", IIImul, CPURegs, [HI, LO]>, MULT_FM<0, 0x18>; 86561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MULTu : Mult<"multu", IIImul, CPURegs, [HI, LO]>, MULT_FM<0, 0x19>; 86661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegs, [HI, LO]>, MULT_FM<0, 0x1a>; 86761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegs, [HI, LO]>, 86861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu MULT_FM<0, 0x1b>; 86961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 87061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 87161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 87261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 87361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 87461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 87561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu/// Sign Ext In Register Instructions. 87661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 87761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 87861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 87961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu/// Count Leading 88061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef CLZ : CountLeading0<"clz", CPURegs>, CLO_FM<0x20>; 88161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef CLO : CountLeading1<"clo", CPURegs>, CLO_FM<0x21>; 88261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 8833f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu/// Word Swap Bytes Within Halfwords 88461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef WSBH : SubwordSwap<"wsbh", CPURegs>, SEB_FM<2, 0x20>; 88561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 8863f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu/// No operation. 88761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu/// FIXME: NOP should be an alias of "sll $0, $0, 0". 88861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef NOP : InstSE<(outs), (ins), "nop", [], IIAlu, FrmJ>, NOP_FM; 88961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 89061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// FrameIndexes are legalized when they are operands from load/store 89161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// instructions. The same not happens for stack address copies, so an 8923f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu// add op with mem ComplexPattern is used and the stack address copy 89361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// can be matched. It's similar to Sparc LEA_ADDRi 8943f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 8953f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu 89661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// MADD*/MSUB* 89761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>; 89861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>; 89961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>; 9003f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>; 9013f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu 9023f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef RDHWR : ReadHardware<CPURegs, HWRegs>, RDHWR_FM; 9033f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu 9043f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef EXT : ExtBase<"ext", CPURegs>, EXT_FM<0>; 9053f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef INS : InsBase<"ins", CPURegs>, EXT_FM<4>; 9063f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu 9073f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu/// Move Control Registers From/To CPU Registers 9083f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef MFC0_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel), 9093f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 9103f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu 9113f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef MTC0_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt), 9123f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 9133f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu 9143f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef MFC2_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel), 9153f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 91661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 91761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef MTC2_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt), 91861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 91961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 92061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 92161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Instruction aliases 92261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 92361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 9243595aa0cbdaa8e754365ca94a0b9eb8fc52b9796Dake Gudef : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 92561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : InstAlias<"addu $rs,$rt,$imm", 92661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 92761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : InstAlias<"add $rs,$rt,$imm", 92861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 92961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : InstAlias<"and $rs,$rt,$imm", 93061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 93161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : InstAlias<"j $rs", (JR CPURegs:$rs)>; 93261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 93361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 93461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 9353f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef : InstAlias<"slt $rs,$rt,$imm", 936c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 937c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudef : InstAlias<"xor $rs,$rt,$imm", 93861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 93961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 940447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stoutdef : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 941447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stoutdef : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 942447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stoutdef : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 943447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stout 944447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stout//===----------------------------------------------------------------------===// 945447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stout// Assembler Pseudo Instructions 946447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stout//===----------------------------------------------------------------------===// 947447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stout 948447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stoutclass LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 949447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stout MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 950447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stout !strconcat(instr_asm, "\t$rt, $imm32")> ; 951447860fd5c105dd0ccd227237ac5f18fdc4c26dcCraig Stoutdef LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; 95261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 95361905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> : 95461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), 95561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(instr_asm, "\t$rt, $addr")> ; 95661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; 95761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 95861905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> : 95961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 96061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu !strconcat(instr_asm, "\t$rt, $imm32")> ; 96161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; 96261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 96361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 96461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 96561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 96661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Arbitrary patterns that map to one or more instructions 96761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//===----------------------------------------------------------------------===// 96861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 96961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Small immediates 97061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(i32 immSExt16:$in), 97161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDiu ZERO, imm:$in)>; 97261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(i32 immZExt16:$in), 97361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ORi ZERO, imm:$in)>; 97461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(i32 immLow16Zero:$in), 97561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (LUi (HI16 imm:$in))>; 97661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 97761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Arbitrary immediates 97861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(i32 imm:$imm), 97961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 98061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 98161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Carry MipsPatterns 98261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 98361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 98461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 98561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 98661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 98761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDiu CPURegs:$src, imm:$imm)>; 98861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 98961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Call 99061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 99161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (JAL tglobaladdr:$dst)>; 99261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 99361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (JAL texternalsym:$dst)>; 99461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu//def : MipsPat<(MipsJmpLink CPURegs:$dst), 99561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// (JALR CPURegs:$dst)>; 99661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 99761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Tail call 99861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 99961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (TAILCALL tglobaladdr:$dst)>; 100061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 100161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (TAILCALL texternalsym:$dst)>; 100261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// hi/lo relocs 100361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 100461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 100561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 100661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 100761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 100861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 100961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 101061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 101161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 101261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 101361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 101461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 101561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 101661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 101761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 101861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 101961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 102061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 102161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 102261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDiu CPURegs:$hi, tjumptable:$lo)>; 102361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 102461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDiu CPURegs:$hi, tconstpool:$lo)>; 102561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 102661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 102761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 102861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// gp_rel relocs 102961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 103061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 103161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 103261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDiu CPURegs:$gp, tconstpool:$in)>; 103361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 103461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// wrapper_pic 103561905b0b52c50018dcaebcd79699c39b8f28d622Dake Guclass WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 103661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu MipsPat<(MipsWrapper RC:$gp, node:$in), 103761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (ADDiuOp RC:$gp, node:$in)>; 103861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 103961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 104061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : WrapperPat<tconstpool, ADDiu, CPURegs>; 104161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : WrapperPat<texternalsym, ADDiu, CPURegs>; 104261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : WrapperPat<tblockaddress, ADDiu, CPURegs>; 104361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : WrapperPat<tjumptable, ADDiu, CPURegs>; 104461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 104561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 104661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// Mips does not have "not", so we expand our way 104761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gudef : MipsPat<(not CPURegs:$in), 104861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu (NOR CPURegs:$in, ZERO)>; 104961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 105061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// extended loads 105161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gulet Predicates = [NotN64, HasStdEnc] in { 105261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 105361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 105461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 105561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 105661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gulet Predicates = [IsN64, HasStdEnc] in { 105761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 105861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 105961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 106061905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 106161905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 106261905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu// peepholes 106361905b0b52c50018dcaebcd79699c39b8f28d622Dake Gulet Predicates = [NotN64, HasStdEnc] in { 106461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 106561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 106661905b0b52c50018dcaebcd79699c39b8f28d622Dake Gulet Predicates = [IsN64, HasStdEnc] in { 106761905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 106861905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu} 106961905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 1070c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu// brcond patterns 10713f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gumulticlass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 10723f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 10733f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu Instruction SLTiuOp, Register ZEROReg> { 10743f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1075c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1076c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudef : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 10773f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 10783f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu 10793f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 10803f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1081c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudef : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1082c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 10833f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 10843f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 10853f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 10863f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1087c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu 1088c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudef : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 10893f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 10903f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gudef : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 10913f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 10923f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu 1093c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudef : MipsPat<(brcond RC:$cond, bb:$dst), 1094c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 10953f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu} 1096c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu 1097c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gudefm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 10988e3566285de4ac771d6188f62fe947e23d371a3dKris Giesing 1099c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu// setcc patterns 1100c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gumulticlass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1101c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu Instruction SLTuOp, Register ZEROReg> { 1102c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1103c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1104c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu def : MipsPat<(setne RC:$lhs, RC:$rhs), 11053f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1106c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu} 1107c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu 1108c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gumulticlass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1109c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu def : MipsPat<(setle RC:$lhs, RC:$rhs), 1110c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 11113f0f3eb255bde49549a77c0b5d252decaa2a0202Dake Gu def : MipsPat<(setule RC:$lhs, RC:$rhs), 1112c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1113c04ca1b14c5bf9ecac80fc53d3f28a5a7fdd4e77Dake Gu} 111461905b0b52c50018dcaebcd79699c39b8f28d622Dake Gu 111561905b0b52c50018dcaebcd79699c39b8f28d622Dake Gumulticlass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1116 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1117 (SLTOp RC:$rhs, RC:$lhs)>; 1118 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1119 (SLTuOp RC:$rhs, RC:$lhs)>; 1120} 1121 1122multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1123 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1124 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1125 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1126 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1127} 1128 1129multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1130 Instruction SLTiuOp> { 1131 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1132 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1133 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1134 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1135} 1136 1137defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1138defm : SetlePats<CPURegs, SLT, SLTu>; 1139defm : SetgtPats<CPURegs, SLT, SLTu>; 1140defm : SetgePats<CPURegs, SLT, SLTu>; 1141defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1142 1143// bswap pattern 1144def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1145 1146//===----------------------------------------------------------------------===// 1147// Floating Point Support 1148//===----------------------------------------------------------------------===// 1149 1150include "MipsInstrFPU.td" 1151include "Mips64InstrInfo.td" 1152include "MipsCondMov.td" 1153 1154// 1155// Mips16 1156 1157include "Mips16InstrFormats.td" 1158include "Mips16InstrInfo.td" 1159 1160// DSP 1161include "MipsDSPInstrFormats.td" 1162include "MipsDSPInstrInfo.td" 1163 1164