MipsInstrInfo.td revision 72e9b6aeb48d9496bac9db8b02c88a618b464588
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, 37 SDTCisSameAs<0, 1>]>; 38def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 39 40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 44 SDTCisSameAs<0, 4>]>; 45 46def SDTMipsLoadLR : SDTypeProfile<1, 2, 47 [SDTCisInt<0>, SDTCisPtrTy<1>, 48 SDTCisSameAs<0, 2>]>; 49 50// Call 51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 53 SDNPVariadic]>; 54 55// Hi and Lo nodes are used to handle global addresses. Used on 56// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 57// static model. (nothing to do with Mips Registers Hi and Lo) 58def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 59def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 60def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 61 62// TlsGd node is used to handle General Dynamic TLS 63def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 64 65// TprelHi and TprelLo nodes are used to handle Local Exec TLS 66def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 67def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 68 69// Thread pointer 70def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 71 72// Return 73def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 74 75// These are target-independent nodes, but have target-specific formats. 76def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 77 [SDNPHasChain, SDNPOutGlue]>; 78def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 80 81// MAdd*/MSub* nodes 82def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 83 [SDNPOptInGlue, SDNPOutGlue]>; 84def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 85 [SDNPOptInGlue, SDNPOutGlue]>; 86def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 87 [SDNPOptInGlue, SDNPOutGlue]>; 88def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 89 [SDNPOptInGlue, SDNPOutGlue]>; 90 91// DivRem(u) nodes 92def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 93 [SDNPOutGlue]>; 94def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 95 [SDNPOutGlue]>; 96 97// Target constant nodes that are not part of any isel patterns and remain 98// unchanged can cause instructions with illegal operands to be emitted. 99// Wrapper node patterns give the instruction selector a chance to replace 100// target constant nodes that would otherwise remain unchanged with ADDiu 101// nodes. Without these wrapper node patterns, the following conditional move 102// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 103// compiled: 104// movn %got(d)($gp), %got(c)($gp), $4 105// This instruction is illegal since movn can take only register operands. 106 107def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 108 109// Pointer to dynamically allocated stack area. 110def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc, 111 [SDNPHasChain, SDNPInGlue]>; 112 113def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>; 114 115def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 116def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 117 118def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 119 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 120def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 121 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 122def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 123 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 124def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 125 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 126def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 127 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 128def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 130def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 131 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 132def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 134 135//===----------------------------------------------------------------------===// 136// Mips Instruction Predicate Definitions. 137//===----------------------------------------------------------------------===// 138def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 139 AssemblerPredicate<"FeatureSEInReg">; 140def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 141 AssemblerPredicate<"FeatureBitCount">; 142def HasSwap : Predicate<"Subtarget.hasSwap()">, 143 AssemblerPredicate<"FeatureSwap">; 144def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 145 AssemblerPredicate<"FeatureCondMov">; 146def HasMips32 : Predicate<"Subtarget.hasMips32()">, 147 AssemblerPredicate<"FeatureMips32">; 148def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 149 AssemblerPredicate<"FeatureMips32r2">; 150def HasMips64 : Predicate<"Subtarget.hasMips64()">, 151 AssemblerPredicate<"FeatureMips64">; 152def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">, 153 AssemblerPredicate<"FeatureMips32r2,FeatureMips64">; 154def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 155 AssemblerPredicate<"!FeatureMips64">; 156def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 157 AssemblerPredicate<"FeatureMips64r2">; 158def IsN64 : Predicate<"Subtarget.isABI_N64()">, 159 AssemblerPredicate<"FeatureN64">; 160def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 161 AssemblerPredicate<"!FeatureN64">; 162def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 163 AssemblerPredicate<"FeatureMips16">; 164def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 165 AssemblerPredicate<"FeatureMips32">; 166def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 167 AssemblerPredicate<"FeatureMips32">; 168def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 169 AssemblerPredicate<"FeatureMips32">; 170def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">, 171 AssemblerPredicate<"!FeatureMips16">; 172 173class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 174 let Predicates = [HasStandardEncoding]; 175} 176 177//===----------------------------------------------------------------------===// 178// Instruction format superclass 179//===----------------------------------------------------------------------===// 180 181include "MipsInstrFormats.td" 182 183//===----------------------------------------------------------------------===// 184// Mips Operand, Complex Patterns and Transformations Definitions. 185//===----------------------------------------------------------------------===// 186 187// Instruction operand types 188def jmptarget : Operand<OtherVT> { 189 let EncoderMethod = "getJumpTargetOpValue"; 190} 191def brtarget : Operand<OtherVT> { 192 let EncoderMethod = "getBranchTargetOpValue"; 193 let OperandType = "OPERAND_PCREL"; 194 let DecoderMethod = "DecodeBranchTarget"; 195} 196def calltarget : Operand<iPTR> { 197 let EncoderMethod = "getJumpTargetOpValue"; 198} 199def calltarget64: Operand<i64>; 200def simm16 : Operand<i32> { 201 let DecoderMethod= "DecodeSimm16"; 202} 203def simm16_64 : Operand<i64>; 204def shamt : Operand<i32>; 205 206// Unsigned Operand 207def uimm16 : Operand<i32> { 208 let PrintMethod = "printUnsignedImm"; 209} 210 211def MipsMemAsmOperand : AsmOperandClass { 212 let Name = "Mem"; 213 let ParserMethod = "parseMemOperand"; 214} 215 216// Address operand 217def mem : Operand<i32> { 218 let PrintMethod = "printMemOperand"; 219 let MIOperandInfo = (ops CPURegs, simm16); 220 let EncoderMethod = "getMemEncoding"; 221 let ParserMatchClass = MipsMemAsmOperand; 222} 223 224def mem64 : Operand<i64> { 225 let PrintMethod = "printMemOperand"; 226 let MIOperandInfo = (ops CPU64Regs, simm16_64); 227 let EncoderMethod = "getMemEncoding"; 228 let ParserMatchClass = MipsMemAsmOperand; 229} 230 231def mem_ea : Operand<i32> { 232 let PrintMethod = "printMemOperandEA"; 233 let MIOperandInfo = (ops CPURegs, simm16); 234 let EncoderMethod = "getMemEncoding"; 235} 236 237def mem_ea_64 : Operand<i64> { 238 let PrintMethod = "printMemOperandEA"; 239 let MIOperandInfo = (ops CPU64Regs, simm16_64); 240 let EncoderMethod = "getMemEncoding"; 241} 242 243// size operand of ext instruction 244def size_ext : Operand<i32> { 245 let EncoderMethod = "getSizeExtEncoding"; 246 let DecoderMethod = "DecodeExtSize"; 247} 248 249// size operand of ins instruction 250def size_ins : Operand<i32> { 251 let EncoderMethod = "getSizeInsEncoding"; 252 let DecoderMethod = "DecodeInsSize"; 253} 254 255// Transformation Function - get the lower 16 bits. 256def LO16 : SDNodeXForm<imm, [{ 257 return getImm(N, N->getZExtValue() & 0xFFFF); 258}]>; 259 260// Transformation Function - get the higher 16 bits. 261def HI16 : SDNodeXForm<imm, [{ 262 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 263}]>; 264 265// Node immediate fits as 16-bit sign extended on target immediate. 266// e.g. addi, andi 267def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 268 269// Node immediate fits as 16-bit zero extended on target immediate. 270// The LO16 param means that only the lower 16 bits of the node 271// immediate are caught. 272// e.g. addiu, sltiu 273def immZExt16 : PatLeaf<(imm), [{ 274 if (N->getValueType(0) == MVT::i32) 275 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 276 else 277 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 278}], LO16>; 279 280// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 281def immLow16Zero : PatLeaf<(imm), [{ 282 int64_t Val = N->getSExtValue(); 283 return isInt<32>(Val) && !(Val & 0xffff); 284}]>; 285 286// shamt field must fit in 5 bits. 287def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 288 289// Mips Address Mode! SDNode frameindex could possibily be a match 290// since load and store instructions from stack used it. 291def addr : 292 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 293 294//===----------------------------------------------------------------------===// 295// Pattern fragment for load/store 296//===----------------------------------------------------------------------===// 297class UnalignedLoad<PatFrag Node> : 298 PatFrag<(ops node:$ptr), (Node node:$ptr), [{ 299 LoadSDNode *LD = cast<LoadSDNode>(N); 300 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment(); 301}]>; 302 303class AlignedLoad<PatFrag Node> : 304 PatFrag<(ops node:$ptr), (Node node:$ptr), [{ 305 LoadSDNode *LD = cast<LoadSDNode>(N); 306 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment(); 307}]>; 308 309class UnalignedStore<PatFrag Node> : 310 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{ 311 StoreSDNode *SD = cast<StoreSDNode>(N); 312 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment(); 313}]>; 314 315class AlignedStore<PatFrag Node> : 316 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{ 317 StoreSDNode *SD = cast<StoreSDNode>(N); 318 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment(); 319}]>; 320 321// Load/Store PatFrags. 322def sextloadi16_a : AlignedLoad<sextloadi16>; 323def zextloadi16_a : AlignedLoad<zextloadi16>; 324def extloadi16_a : AlignedLoad<extloadi16>; 325def load_a : AlignedLoad<load>; 326def sextloadi32_a : AlignedLoad<sextloadi32>; 327def zextloadi32_a : AlignedLoad<zextloadi32>; 328def extloadi32_a : AlignedLoad<extloadi32>; 329def truncstorei16_a : AlignedStore<truncstorei16>; 330def store_a : AlignedStore<store>; 331def truncstorei32_a : AlignedStore<truncstorei32>; 332def sextloadi16_u : UnalignedLoad<sextloadi16>; 333def zextloadi16_u : UnalignedLoad<zextloadi16>; 334def extloadi16_u : UnalignedLoad<extloadi16>; 335def load_u : UnalignedLoad<load>; 336def sextloadi32_u : UnalignedLoad<sextloadi32>; 337def zextloadi32_u : UnalignedLoad<zextloadi32>; 338def extloadi32_u : UnalignedLoad<extloadi32>; 339def truncstorei16_u : UnalignedStore<truncstorei16>; 340def store_u : UnalignedStore<store>; 341def truncstorei32_u : UnalignedStore<truncstorei32>; 342 343//===----------------------------------------------------------------------===// 344// Instructions specific format 345//===----------------------------------------------------------------------===// 346 347// Arithmetic and logical instructions with 3 register operands. 348class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode, 349 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 350 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 351 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 352 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> { 353 let shamt = 0; 354 let isCommutable = isComm; 355 let isReMaterializable = 1; 356} 357 358class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm, 359 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 360 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 361 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> { 362 let shamt = 0; 363 let isCommutable = isComm; 364} 365 366// Arithmetic and logical instructions with 2 register operands. 367class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode, 368 Operand Od, PatLeaf imm_type, RegisterClass RC> : 369 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 370 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 371 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> { 372 let isReMaterializable = 1; 373} 374 375class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode, 376 Operand Od, PatLeaf imm_type, RegisterClass RC> : 377 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 378 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>; 379 380// Arithmetic Multiply ADD/SUB 381let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 382class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 383 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 384 !strconcat(instr_asm, "\t$rs, $rt"), 385 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 386 let rd = 0; 387 let shamt = 0; 388 let isCommutable = isComm; 389} 390 391// Logical 392class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: 393 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 394 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 395 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> { 396 let shamt = 0; 397 let isCommutable = 1; 398} 399 400// Shifts 401class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm, 402 SDNode OpNode, PatFrag PF, Operand ImmOpnd, 403 RegisterClass RC>: 404 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 405 !strconcat(instr_asm, "\t$rd, $rt, $shamt"), 406 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> { 407 let rs = isRotate; 408} 409 410// 32-bit shift instructions. 411class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm, 412 SDNode OpNode>: 413 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>; 414 415class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm, 416 SDNode OpNode, RegisterClass RC>: 417 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 418 !strconcat(instr_asm, "\t$rd, $rt, $rs"), 419 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> { 420 let shamt = isRotate; 421} 422 423// Load Upper Imediate 424class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 425 FI<op, (outs RC:$rt), (ins Imm:$imm16), 426 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> { 427 let rs = 0; 428 let neverHasSideEffects = 1; 429 let isReMaterializable = 1; 430} 431 432class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 433 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 434 bits<21> addr; 435 let Inst{25-21} = addr{20-16}; 436 let Inst{15-0} = addr{15-0}; 437 let DecoderMethod = "DecodeMem"; 438} 439 440// Memory Load/Store 441let canFoldAsLoad = 1 in 442class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 443 Operand MemOpnd, bit Pseudo>: 444 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 445 !strconcat(instr_asm, "\t$rt, $addr"), 446 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 447 let isPseudo = Pseudo; 448} 449 450class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 451 Operand MemOpnd, bit Pseudo>: 452 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 453 !strconcat(instr_asm, "\t$rt, $addr"), 454 [(OpNode RC:$rt, addr:$addr)], IIStore> { 455 let isPseudo = Pseudo; 456} 457 458// 32-bit load. 459multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 460 bit Pseudo = 0> { 461 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 462 Requires<[NotN64, HasStandardEncoding]>; 463 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 464 Requires<[IsN64, HasStandardEncoding]> { 465 let DecoderNamespace = "Mips64"; 466 let isCodeGenOnly = 1; 467 } 468} 469 470// 64-bit load. 471multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 472 bit Pseudo = 0> { 473 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 474 Requires<[NotN64, HasStandardEncoding]>; 475 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 476 Requires<[IsN64, HasStandardEncoding]> { 477 let DecoderNamespace = "Mips64"; 478 let isCodeGenOnly = 1; 479 } 480} 481 482// 32-bit store. 483multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 484 bit Pseudo = 0> { 485 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 486 Requires<[NotN64, HasStandardEncoding]>; 487 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 488 Requires<[IsN64, HasStandardEncoding]> { 489 let DecoderNamespace = "Mips64"; 490 let isCodeGenOnly = 1; 491 } 492} 493 494// 64-bit store. 495multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 496 bit Pseudo = 0> { 497 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 498 Requires<[NotN64, HasStandardEncoding]>; 499 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 500 Requires<[IsN64, HasStandardEncoding]> { 501 let DecoderNamespace = "Mips64"; 502 let isCodeGenOnly = 1; 503 } 504} 505 506// Load/Store Left/Right 507let canFoldAsLoad = 1 in 508class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 509 RegisterClass RC, Operand MemOpnd> : 510 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 511 !strconcat(instr_asm, "\t$rt, $addr"), 512 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 513 string Constraints = "$src = $rt"; 514} 515 516class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 517 RegisterClass RC, Operand MemOpnd>: 518 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 519 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 520 IIStore>; 521 522// 32-bit load left/right. 523multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 524 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 525 Requires<[NotN64, HasStandardEncoding]>; 526 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 527 Requires<[IsN64, HasStandardEncoding]> { 528 let DecoderNamespace = "Mips64"; 529 let isCodeGenOnly = 1; 530 } 531} 532 533// 64-bit load left/right. 534multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 535 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 536 Requires<[NotN64, HasStandardEncoding]>; 537 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 538 Requires<[IsN64, HasStandardEncoding]> { 539 let DecoderNamespace = "Mips64"; 540 let isCodeGenOnly = 1; 541 } 542} 543 544// 32-bit store left/right. 545multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 546 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 547 Requires<[NotN64, HasStandardEncoding]>; 548 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 549 Requires<[IsN64, HasStandardEncoding]> { 550 let DecoderNamespace = "Mips64"; 551 let isCodeGenOnly = 1; 552 } 553} 554 555// 64-bit store left/right. 556multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 557 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 558 Requires<[NotN64, HasStandardEncoding]>; 559 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 560 Requires<[IsN64, HasStandardEncoding]> { 561 let DecoderNamespace = "Mips64"; 562 let isCodeGenOnly = 1; 563 } 564} 565 566// Conditional Branch 567class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>: 568 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16), 569 !strconcat(instr_asm, "\t$rs, $rt, $imm16"), 570 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { 571 let isBranch = 1; 572 let isTerminator = 1; 573 let hasDelaySlot = 1; 574 let Defs = [AT]; 575} 576 577class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op, 578 RegisterClass RC>: 579 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16), 580 !strconcat(instr_asm, "\t$rs, $imm16"), 581 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { 582 let rt = _rt; 583 let isBranch = 1; 584 let isTerminator = 1; 585 let hasDelaySlot = 1; 586 let Defs = [AT]; 587} 588 589// SetCC 590class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op, 591 RegisterClass RC>: 592 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 593 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 594 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], 595 IIAlu> { 596 let shamt = 0; 597} 598 599class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, 600 PatLeaf imm_type, RegisterClass RC>: 601 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 602 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 603 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], 604 IIAlu>; 605 606// Jump 607class JumpFJ<bits<6> op, string instr_asm>: 608 FJ<op, (outs), (ins jmptarget:$target), 609 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> { 610 let isBranch=1; 611 let isTerminator=1; 612 let isBarrier=1; 613 let hasDelaySlot = 1; 614 let Predicates = [RelocStatic, HasStandardEncoding]; 615 let DecoderMethod = "DecodeJumpTarget"; 616 let Defs = [AT]; 617} 618 619// Unconditional branch 620class UncondBranch<bits<6> op, string instr_asm>: 621 BranchBase<op, (outs), (ins brtarget:$imm16), 622 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { 623 let rs = 0; 624 let rt = 0; 625 let isBranch = 1; 626 let isTerminator = 1; 627 let isBarrier = 1; 628 let hasDelaySlot = 1; 629 let Predicates = [RelocPIC, HasStandardEncoding]; 630 let Defs = [AT]; 631} 632 633// Base class for indirect branch and return instruction classes. 634let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 635class JumpFR<RegisterClass RC, list<dag> pattern>: 636 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", pattern, IIBranch> { 637 let rt = 0; 638 let rd = 0; 639 let shamt = 0; 640} 641 642// Indirect branch 643class IndirectBranch<RegisterClass RC>: JumpFR<RC, [(brind RC:$rs)]> { 644 let isBranch = 1; 645 let isIndirectBranch = 1; 646} 647 648// Return instruction 649class RetBase<RegisterClass RC>: JumpFR<RC, []> { 650 let isReturn = 1; 651 let isCodeGenOnly = 1; 652 let hasCtrlDep = 1; 653 let hasExtraSrcRegAllocReq = 1; 654} 655 656// Jump and Link (Call) 657let isCall=1, hasDelaySlot=1, Defs = [RA] in { 658 class JumpLink<bits<6> op, string instr_asm>: 659 FJ<op, (outs), (ins calltarget:$target), 660 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 661 IIBranch> { 662 let DecoderMethod = "DecodeJumpTarget"; 663 } 664 665 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 666 RegisterClass RC>: 667 FR<op, func, (outs), (ins RC:$rs), 668 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 669 let rt = 0; 670 let rd = 31; 671 let shamt = 0; 672 } 673 674 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 675 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 676 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 677 let rt = _rt; 678 } 679} 680 681// Mul, Div 682class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 683 RegisterClass RC, list<Register> DefRegs>: 684 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 685 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 686 let rd = 0; 687 let shamt = 0; 688 let isCommutable = 1; 689 let Defs = DefRegs; 690 let neverHasSideEffects = 1; 691} 692 693class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 694 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 695 696class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 697 RegisterClass RC, list<Register> DefRegs>: 698 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 699 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 700 [(op RC:$rs, RC:$rt)], itin> { 701 let rd = 0; 702 let shamt = 0; 703 let Defs = DefRegs; 704} 705 706class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 707 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 708 709// Move from Hi/Lo 710class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC, 711 list<Register> UseRegs>: 712 FR<0x00, func, (outs RC:$rd), (ins), 713 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> { 714 let rs = 0; 715 let rt = 0; 716 let shamt = 0; 717 let Uses = UseRegs; 718 let neverHasSideEffects = 1; 719} 720 721class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC, 722 list<Register> DefRegs>: 723 FR<0x00, func, (outs), (ins RC:$rs), 724 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> { 725 let rt = 0; 726 let rd = 0; 727 let shamt = 0; 728 let Defs = DefRegs; 729 let neverHasSideEffects = 1; 730} 731 732class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 733 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 734 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 735 let isCodeGenOnly = 1; 736} 737 738// Count Leading Ones/Zeros in Word 739class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>: 740 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 741 !strconcat(instr_asm, "\t$rd, $rs"), 742 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, 743 Requires<[HasBitCount, HasStandardEncoding]> { 744 let shamt = 0; 745 let rt = rd; 746} 747 748class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: 749 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 750 !strconcat(instr_asm, "\t$rd, $rs"), 751 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, 752 Requires<[HasBitCount, HasStandardEncoding]> { 753 let shamt = 0; 754 let rt = rd; 755} 756 757// Sign Extend in Register. 758class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt, 759 RegisterClass RC>: 760 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), 761 !strconcat(instr_asm, "\t$rd, $rt"), 762 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { 763 let rs = 0; 764 let shamt = sa; 765 let Predicates = [HasSEInReg, HasStandardEncoding]; 766} 767 768// Subword Swap 769class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 770 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 771 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 772 let rs = 0; 773 let shamt = sa; 774 let Predicates = [HasSwap, HasStandardEncoding]; 775 let neverHasSideEffects = 1; 776} 777 778// Read Hardware 779class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 780 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 781 "rdhwr\t$rt, $rd", [], IIAlu> { 782 let rs = 0; 783 let shamt = 0; 784} 785 786// Ext and Ins 787class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 788 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 789 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 790 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 791 bits<5> pos; 792 bits<5> sz; 793 let rd = sz; 794 let shamt = pos; 795 let Predicates = [HasMips32r2, HasStandardEncoding]; 796} 797 798class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 799 FR<0x1f, _funct, (outs RC:$rt), 800 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 801 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 802 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 803 NoItinerary> { 804 bits<5> pos; 805 bits<5> sz; 806 let rd = sz; 807 let shamt = pos; 808 let Predicates = [HasMips32r2, HasStandardEncoding]; 809 let Constraints = "$src = $rt"; 810} 811 812// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 813class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC, 814 RegisterClass PRC> : 815 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 816 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), 817 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 818 819multiclass Atomic2Ops32<PatFrag Op, string Opstr> { 820 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, 821 Requires<[NotN64, HasStandardEncoding]>; 822 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, 823 Requires<[IsN64, HasStandardEncoding]> { 824 let DecoderNamespace = "Mips64"; 825 } 826} 827 828// Atomic Compare & Swap. 829class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC, 830 RegisterClass PRC> : 831 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 832 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), 833 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 834 835multiclass AtomicCmpSwap32<PatFrag Op, string Width> { 836 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, 837 Requires<[NotN64, HasStandardEncoding]>; 838 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, 839 Requires<[IsN64, HasStandardEncoding]> { 840 let DecoderNamespace = "Mips64"; 841 } 842} 843 844class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 845 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 846 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 847 let mayLoad = 1; 848} 849 850class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 851 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 852 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 853 let mayStore = 1; 854 let Constraints = "$rt = $dst"; 855} 856 857//===----------------------------------------------------------------------===// 858// Pseudo instructions 859//===----------------------------------------------------------------------===// 860 861// Return RA. 862let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 863def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>; 864 865let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 866def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 867 "!ADJCALLSTACKDOWN $amt", 868 [(callseq_start timm:$amt)]>; 869def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 870 "!ADJCALLSTACKUP $amt1", 871 [(callseq_end timm:$amt1, timm:$amt2)]>; 872} 873 874// When handling PIC code the assembler needs .cpload and .cprestore 875// directives. If the real instructions corresponding these directives 876// are used, we have the same behavior, but get also a bunch of warnings 877// from the assembler. 878let neverHasSideEffects = 1 in 879def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp), 880 ".cprestore\t$loc", []>; 881 882let usesCustomInserter = 1 in { 883 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">; 884 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">; 885 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">; 886 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">; 887 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">; 888 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">; 889 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">; 890 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">; 891 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">; 892 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">; 893 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">; 894 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">; 895 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">; 896 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">; 897 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">; 898 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">; 899 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">; 900 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">; 901 902 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">; 903 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">; 904 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">; 905 906 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">; 907 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">; 908 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">; 909} 910 911//===----------------------------------------------------------------------===// 912// Instruction definition 913//===----------------------------------------------------------------------===// 914 915//===----------------------------------------------------------------------===// 916// MipsI Instructions 917//===----------------------------------------------------------------------===// 918 919/// Arithmetic Instructions (ALU Immediate) 920def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>; 921def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>; 922def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; 923def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; 924def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>; 925def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>; 926def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>; 927def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; 928 929/// Arithmetic Instructions (3-Operand, R-Type) 930def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>; 931def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>; 932def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>; 933def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>; 934def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; 935def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; 936def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>; 937def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>; 938def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>; 939def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; 940 941/// Shift Instructions 942def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>; 943def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>; 944def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>; 945def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>; 946def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>; 947def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>; 948 949// Rotate Instructions 950let Predicates = [HasMips32r2, HasStandardEncoding] in { 951 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>; 952 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>; 953} 954 955/// Load and Store Instructions 956/// aligned 957defm LB : LoadM32<0x20, "lb", sextloadi8>; 958defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 959defm LH : LoadM32<0x21, "lh", sextloadi16_a>; 960defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>; 961defm LW : LoadM32<0x23, "lw", load_a>; 962defm SB : StoreM32<0x28, "sb", truncstorei8>; 963defm SH : StoreM32<0x29, "sh", truncstorei16_a>; 964defm SW : StoreM32<0x2b, "sw", store_a>; 965 966/// unaligned 967defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>; 968defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>; 969defm ULW : LoadM32<0x23, "ulw", load_u, 1>; 970defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>; 971defm USW : StoreM32<0x2b, "usw", store_u, 1>; 972 973/// load/store left/right 974defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 975defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 976defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 977defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 978 979let hasSideEffects = 1 in 980def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 981 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 982{ 983 bits<5> stype; 984 let Opcode = 0; 985 let Inst{25-11} = 0; 986 let Inst{10-6} = stype; 987 let Inst{5-0} = 15; 988} 989 990/// Load-linked, Store-conditional 991def LL : LLBase<0x30, "ll", CPURegs, mem>, 992 Requires<[NotN64, HasStandardEncoding]>; 993def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 994 Requires<[IsN64, HasStandardEncoding]> { 995 let DecoderNamespace = "Mips64"; 996} 997 998def SC : SCBase<0x38, "sc", CPURegs, mem>, 999 Requires<[NotN64, HasStandardEncoding]>; 1000def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 1001 Requires<[IsN64, HasStandardEncoding]> { 1002 let DecoderNamespace = "Mips64"; 1003} 1004 1005/// Jump and Branch Instructions 1006def J : JumpFJ<0x02, "j">; 1007def JR : IndirectBranch<CPURegs>; 1008def B : UncondBranch<0x04, "b">; 1009def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; 1010def BNE : CBranch<0x05, "bne", setne, CPURegs>; 1011def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; 1012def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>; 1013def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>; 1014def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>; 1015 1016let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 1017 hasDelaySlot = 1, Defs = [RA] in 1018def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 1019 1020def JAL : JumpLink<0x03, "jal">; 1021def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 1022def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 1023def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 1024 1025def RET : RetBase<CPURegs>; 1026 1027/// Multiply and Divide Instructions. 1028def MULT : Mult32<0x18, "mult", IIImul>; 1029def MULTu : Mult32<0x19, "multu", IIImul>; 1030def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 1031def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 1032 1033def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>; 1034def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>; 1035def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; 1036def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; 1037 1038/// Sign Ext In Register Instructions. 1039def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; 1040def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; 1041 1042/// Count Leading 1043def CLZ : CountLeading0<0x20, "clz", CPURegs>; 1044def CLO : CountLeading1<0x21, "clo", CPURegs>; 1045 1046/// Word Swap Bytes Within Halfwords 1047def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 1048 1049/// No operation 1050let addr=0 in 1051 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 1052 1053// FrameIndexes are legalized when they are operands from load/store 1054// instructions. The same not happens for stack address copies, so an 1055// add op with mem ComplexPattern is used and the stack address copy 1056// can be matched. It's similar to Sparc LEA_ADDRi 1057def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1058 1059// DynAlloc node points to dynamically allocated stack space. 1060// $sp is added to the list of implicitly used registers to prevent dead code 1061// elimination from removing instructions that modify $sp. 1062let Uses = [SP] in 1063def DynAlloc : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1064 1065// MADD*/MSUB* 1066def MADD : MArithR<0, "madd", MipsMAdd, 1>; 1067def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 1068def MSUB : MArithR<4, "msub", MipsMSub>; 1069def MSUBU : MArithR<5, "msubu", MipsMSubu>; 1070 1071// MUL is a assembly macro in the current used ISAs. In recent ISA's 1072// it is a real instruction. 1073def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>, 1074 Requires<[HasMips32, HasStandardEncoding]>; 1075 1076def RDHWR : ReadHardware<CPURegs, HWRegs>; 1077 1078def EXT : ExtBase<0, "ext", CPURegs>; 1079def INS : InsBase<4, "ins", CPURegs>; 1080 1081//===----------------------------------------------------------------------===// 1082// Arbitrary patterns that map to one or more instructions 1083//===----------------------------------------------------------------------===// 1084 1085// Small immediates 1086def : MipsPat<(i32 immSExt16:$in), 1087 (ADDiu ZERO, imm:$in)>; 1088def : MipsPat<(i32 immZExt16:$in), 1089 (ORi ZERO, imm:$in)>; 1090def : MipsPat<(i32 immLow16Zero:$in), 1091 (LUi (HI16 imm:$in))>; 1092 1093// Arbitrary immediates 1094def : MipsPat<(i32 imm:$imm), 1095 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1096 1097// Carry MipsPatterns 1098def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1099 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1100def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1101 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1102def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1103 (ADDiu CPURegs:$src, imm:$imm)>; 1104 1105// Call 1106def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1107 (JAL tglobaladdr:$dst)>; 1108def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1109 (JAL texternalsym:$dst)>; 1110//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1111// (JALR CPURegs:$dst)>; 1112 1113// hi/lo relocs 1114def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1115def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1116def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1117def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1118def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1119 1120def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1121def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1122def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1123def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1124def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1125 1126def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1127 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1128def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1129 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1130def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1131 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1132def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1133 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1134def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1135 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1136 1137// gp_rel relocs 1138def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1139 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1140def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1141 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1142 1143// wrapper_pic 1144class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1145 MipsPat<(MipsWrapper RC:$gp, node:$in), 1146 (ADDiuOp RC:$gp, node:$in)>; 1147 1148def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1149def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1150def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1151def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1152def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1153def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1154 1155// Mips does not have "not", so we expand our way 1156def : MipsPat<(not CPURegs:$in), 1157 (NOR CPURegs:$in, ZERO)>; 1158 1159// extended loads 1160let Predicates = [NotN64, HasStandardEncoding] in { 1161 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1162 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1163 def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>; 1164 def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>; 1165} 1166let Predicates = [IsN64, HasStandardEncoding] in { 1167 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1168 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1169 def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>; 1170 def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>; 1171} 1172 1173// peepholes 1174let Predicates = [NotN64, HasStandardEncoding] in { 1175 def : MipsPat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1176 def : MipsPat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>; 1177} 1178let Predicates = [IsN64, HasStandardEncoding] in { 1179 def : MipsPat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1180 def : MipsPat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>; 1181} 1182 1183// brcond patterns 1184multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1185 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1186 Instruction SLTiuOp, Register ZEROReg> { 1187def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1188 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1189def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1190 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1191 1192def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1193 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1194def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1195 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1196def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1197 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1198def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1199 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1200 1201def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1202 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1203def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1204 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1205 1206def : MipsPat<(brcond RC:$cond, bb:$dst), 1207 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1208} 1209 1210defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1211 1212// setcc patterns 1213multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1214 Instruction SLTuOp, Register ZEROReg> { 1215 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1216 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1217 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1218 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1219} 1220 1221multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1222 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1223 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1224 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1225 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1226} 1227 1228multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1229 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1230 (SLTOp RC:$rhs, RC:$lhs)>; 1231 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1232 (SLTuOp RC:$rhs, RC:$lhs)>; 1233} 1234 1235multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1236 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1237 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1238 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1239 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1240} 1241 1242multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1243 Instruction SLTiuOp> { 1244 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1245 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1246 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1247 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1248} 1249 1250defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1251defm : SetlePats<CPURegs, SLT, SLTu>; 1252defm : SetgtPats<CPURegs, SLT, SLTu>; 1253defm : SetgePats<CPURegs, SLT, SLTu>; 1254defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1255 1256// select MipsDynAlloc 1257def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; 1258 1259// bswap pattern 1260def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1261 1262//===----------------------------------------------------------------------===// 1263// Floating Point Support 1264//===----------------------------------------------------------------------===// 1265 1266include "MipsInstrFPU.td" 1267include "Mips64InstrInfo.td" 1268include "MipsCondMov.td" 1269 1270// 1271// Mips16 1272 1273include "Mips16InstrFormats.td" 1274include "Mips16InstrInfo.td" 1275