MipsInstrInfo.td revision 9d577c861414c28967d77c2a1edf64b68efdeaee
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, 37 SDTCisSameAs<0, 1>]>; 38def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 39 40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 44 SDTCisSameAs<0, 4>]>; 45 46def SDTMipsLoadLR : SDTypeProfile<1, 2, 47 [SDTCisInt<0>, SDTCisPtrTy<1>, 48 SDTCisSameAs<0, 2>]>; 49 50// Call 51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 53 SDNPVariadic]>; 54 55// Hi and Lo nodes are used to handle global addresses. Used on 56// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 57// static model. (nothing to do with Mips Registers Hi and Lo) 58def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 59def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 60def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 61 62// TlsGd node is used to handle General Dynamic TLS 63def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 64 65// TprelHi and TprelLo nodes are used to handle Local Exec TLS 66def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 67def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 68 69// Thread pointer 70def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 71 72// Return 73def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 74 75// These are target-independent nodes, but have target-specific formats. 76def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 77 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 78def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 79 [SDNPHasChain, SDNPSideEffect, 80 SDNPOptInGlue, SDNPOutGlue]>; 81 82// MAdd*/MSub* nodes 83def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 84 [SDNPOptInGlue, SDNPOutGlue]>; 85def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91 92// DivRem(u) nodes 93def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 94 [SDNPOutGlue]>; 95def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97 98// Target constant nodes that are not part of any isel patterns and remain 99// unchanged can cause instructions with illegal operands to be emitted. 100// Wrapper node patterns give the instruction selector a chance to replace 101// target constant nodes that would otherwise remain unchanged with ADDiu 102// nodes. Without these wrapper node patterns, the following conditional move 103// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 104// compiled: 105// movn %got(d)($gp), %got(c)($gp), $4 106// This instruction is illegal since movn can take only register operands. 107 108def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 109 110// Pointer to dynamically allocated stack area. 111def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc, 112 [SDNPHasChain, SDNPInGlue]>; 113 114def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 115 116def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 117def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 118 119def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 122 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 123def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 126 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 127def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 131def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 135 136//===----------------------------------------------------------------------===// 137// Mips Instruction Predicate Definitions. 138//===----------------------------------------------------------------------===// 139def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 140 AssemblerPredicate<"FeatureSEInReg">; 141def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 142 AssemblerPredicate<"FeatureBitCount">; 143def HasSwap : Predicate<"Subtarget.hasSwap()">, 144 AssemblerPredicate<"FeatureSwap">; 145def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 146 AssemblerPredicate<"FeatureCondMov">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">, 154 AssemblerPredicate<"FeatureMips32r2,FeatureMips64">; 155def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 156 AssemblerPredicate<"!FeatureMips64">; 157def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 158 AssemblerPredicate<"FeatureMips64r2">; 159def IsN64 : Predicate<"Subtarget.isABI_N64()">, 160 AssemblerPredicate<"FeatureN64">; 161def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 162 AssemblerPredicate<"!FeatureN64">; 163def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 164 AssemblerPredicate<"FeatureMips16">; 165def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 166 AssemblerPredicate<"FeatureMips32">; 167def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 168 AssemblerPredicate<"FeatureMips32">; 169def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 170 AssemblerPredicate<"FeatureMips32">; 171def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">, 172 AssemblerPredicate<"!FeatureMips16">; 173 174class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 175 let Predicates = [HasStandardEncoding]; 176} 177 178//===----------------------------------------------------------------------===// 179// Instruction format superclass 180//===----------------------------------------------------------------------===// 181 182include "MipsInstrFormats.td" 183 184//===----------------------------------------------------------------------===// 185// Mips Operand, Complex Patterns and Transformations Definitions. 186//===----------------------------------------------------------------------===// 187 188// Instruction operand types 189def jmptarget : Operand<OtherVT> { 190 let EncoderMethod = "getJumpTargetOpValue"; 191} 192def brtarget : Operand<OtherVT> { 193 let EncoderMethod = "getBranchTargetOpValue"; 194 let OperandType = "OPERAND_PCREL"; 195 let DecoderMethod = "DecodeBranchTarget"; 196} 197def calltarget : Operand<iPTR> { 198 let EncoderMethod = "getJumpTargetOpValue"; 199} 200def calltarget64: Operand<i64>; 201def simm16 : Operand<i32> { 202 let DecoderMethod= "DecodeSimm16"; 203} 204def simm16_64 : Operand<i64>; 205def shamt : Operand<i32>; 206 207// Unsigned Operand 208def uimm16 : Operand<i32> { 209 let PrintMethod = "printUnsignedImm"; 210} 211 212def MipsMemAsmOperand : AsmOperandClass { 213 let Name = "Mem"; 214 let ParserMethod = "parseMemOperand"; 215} 216 217// Address operand 218def mem : Operand<i32> { 219 let PrintMethod = "printMemOperand"; 220 let MIOperandInfo = (ops CPURegs, simm16); 221 let EncoderMethod = "getMemEncoding"; 222 let ParserMatchClass = MipsMemAsmOperand; 223} 224 225def mem64 : Operand<i64> { 226 let PrintMethod = "printMemOperand"; 227 let MIOperandInfo = (ops CPU64Regs, simm16_64); 228 let EncoderMethod = "getMemEncoding"; 229 let ParserMatchClass = MipsMemAsmOperand; 230} 231 232def mem_ea : Operand<i32> { 233 let PrintMethod = "printMemOperandEA"; 234 let MIOperandInfo = (ops CPURegs, simm16); 235 let EncoderMethod = "getMemEncoding"; 236} 237 238def mem_ea_64 : Operand<i64> { 239 let PrintMethod = "printMemOperandEA"; 240 let MIOperandInfo = (ops CPU64Regs, simm16_64); 241 let EncoderMethod = "getMemEncoding"; 242} 243 244// size operand of ext instruction 245def size_ext : Operand<i32> { 246 let EncoderMethod = "getSizeExtEncoding"; 247 let DecoderMethod = "DecodeExtSize"; 248} 249 250// size operand of ins instruction 251def size_ins : Operand<i32> { 252 let EncoderMethod = "getSizeInsEncoding"; 253 let DecoderMethod = "DecodeInsSize"; 254} 255 256// Transformation Function - get the lower 16 bits. 257def LO16 : SDNodeXForm<imm, [{ 258 return getImm(N, N->getZExtValue() & 0xFFFF); 259}]>; 260 261// Transformation Function - get the higher 16 bits. 262def HI16 : SDNodeXForm<imm, [{ 263 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 264}]>; 265 266// Node immediate fits as 16-bit sign extended on target immediate. 267// e.g. addi, andi 268def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 269 270// Node immediate fits as 16-bit zero extended on target immediate. 271// The LO16 param means that only the lower 16 bits of the node 272// immediate are caught. 273// e.g. addiu, sltiu 274def immZExt16 : PatLeaf<(imm), [{ 275 if (N->getValueType(0) == MVT::i32) 276 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 277 else 278 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 279}], LO16>; 280 281// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 282def immLow16Zero : PatLeaf<(imm), [{ 283 int64_t Val = N->getSExtValue(); 284 return isInt<32>(Val) && !(Val & 0xffff); 285}]>; 286 287// shamt field must fit in 5 bits. 288def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 289 290// Mips Address Mode! SDNode frameindex could possibily be a match 291// since load and store instructions from stack used it. 292def addr : 293 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 294 295//===----------------------------------------------------------------------===// 296// Instructions specific format 297//===----------------------------------------------------------------------===// 298 299// Arithmetic and logical instructions with 3 register operands. 300class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode, 301 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 302 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 303 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 304 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> { 305 let shamt = 0; 306 let isCommutable = isComm; 307 let isReMaterializable = 1; 308} 309 310class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm, 311 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 312 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 313 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> { 314 let shamt = 0; 315 let isCommutable = isComm; 316} 317 318// Arithmetic and logical instructions with 2 register operands. 319class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode, 320 Operand Od, PatLeaf imm_type, RegisterClass RC> : 321 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 322 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 323 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> { 324 let isReMaterializable = 1; 325} 326 327class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode, 328 Operand Od, PatLeaf imm_type, RegisterClass RC> : 329 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 330 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>; 331 332// Arithmetic Multiply ADD/SUB 333let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 334class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 335 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 336 !strconcat(instr_asm, "\t$rs, $rt"), 337 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 338 let rd = 0; 339 let shamt = 0; 340 let isCommutable = isComm; 341} 342 343// Logical 344class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: 345 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 346 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 347 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> { 348 let shamt = 0; 349 let isCommutable = 1; 350} 351 352// Shifts 353class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm, 354 SDNode OpNode, PatFrag PF, Operand ImmOpnd, 355 RegisterClass RC>: 356 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 357 !strconcat(instr_asm, "\t$rd, $rt, $shamt"), 358 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> { 359 let rs = isRotate; 360} 361 362// 32-bit shift instructions. 363class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm, 364 SDNode OpNode>: 365 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>; 366 367class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm, 368 SDNode OpNode, RegisterClass RC>: 369 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 370 !strconcat(instr_asm, "\t$rd, $rt, $rs"), 371 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> { 372 let shamt = isRotate; 373} 374 375// Load Upper Imediate 376class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 377 FI<op, (outs RC:$rt), (ins Imm:$imm16), 378 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> { 379 let rs = 0; 380 let neverHasSideEffects = 1; 381 let isReMaterializable = 1; 382} 383 384class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 385 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 386 bits<21> addr; 387 let Inst{25-21} = addr{20-16}; 388 let Inst{15-0} = addr{15-0}; 389 let DecoderMethod = "DecodeMem"; 390} 391 392// Memory Load/Store 393let canFoldAsLoad = 1 in 394class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 395 Operand MemOpnd, bit Pseudo>: 396 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 397 !strconcat(instr_asm, "\t$rt, $addr"), 398 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 399 let isPseudo = Pseudo; 400} 401 402class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 403 Operand MemOpnd, bit Pseudo>: 404 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 405 !strconcat(instr_asm, "\t$rt, $addr"), 406 [(OpNode RC:$rt, addr:$addr)], IIStore> { 407 let isPseudo = Pseudo; 408} 409 410// 32-bit load. 411multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 412 bit Pseudo = 0> { 413 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 414 Requires<[NotN64, HasStandardEncoding]>; 415 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 416 Requires<[IsN64, HasStandardEncoding]> { 417 let DecoderNamespace = "Mips64"; 418 let isCodeGenOnly = 1; 419 } 420} 421 422// 64-bit load. 423multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 424 bit Pseudo = 0> { 425 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 426 Requires<[NotN64, HasStandardEncoding]>; 427 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 428 Requires<[IsN64, HasStandardEncoding]> { 429 let DecoderNamespace = "Mips64"; 430 let isCodeGenOnly = 1; 431 } 432} 433 434// 32-bit store. 435multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 436 bit Pseudo = 0> { 437 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 438 Requires<[NotN64, HasStandardEncoding]>; 439 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 440 Requires<[IsN64, HasStandardEncoding]> { 441 let DecoderNamespace = "Mips64"; 442 let isCodeGenOnly = 1; 443 } 444} 445 446// 64-bit store. 447multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 448 bit Pseudo = 0> { 449 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 450 Requires<[NotN64, HasStandardEncoding]>; 451 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 452 Requires<[IsN64, HasStandardEncoding]> { 453 let DecoderNamespace = "Mips64"; 454 let isCodeGenOnly = 1; 455 } 456} 457 458// Load/Store Left/Right 459let canFoldAsLoad = 1 in 460class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 461 RegisterClass RC, Operand MemOpnd> : 462 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 463 !strconcat(instr_asm, "\t$rt, $addr"), 464 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 465 string Constraints = "$src = $rt"; 466} 467 468class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 469 RegisterClass RC, Operand MemOpnd>: 470 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 471 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 472 IIStore>; 473 474// 32-bit load left/right. 475multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 476 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 477 Requires<[NotN64, HasStandardEncoding]>; 478 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 479 Requires<[IsN64, HasStandardEncoding]> { 480 let DecoderNamespace = "Mips64"; 481 let isCodeGenOnly = 1; 482 } 483} 484 485// 64-bit load left/right. 486multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 487 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 488 Requires<[NotN64, HasStandardEncoding]>; 489 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 490 Requires<[IsN64, HasStandardEncoding]> { 491 let DecoderNamespace = "Mips64"; 492 let isCodeGenOnly = 1; 493 } 494} 495 496// 32-bit store left/right. 497multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 498 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 499 Requires<[NotN64, HasStandardEncoding]>; 500 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 501 Requires<[IsN64, HasStandardEncoding]> { 502 let DecoderNamespace = "Mips64"; 503 let isCodeGenOnly = 1; 504 } 505} 506 507// 64-bit store left/right. 508multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 509 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 510 Requires<[NotN64, HasStandardEncoding]>; 511 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 512 Requires<[IsN64, HasStandardEncoding]> { 513 let DecoderNamespace = "Mips64"; 514 let isCodeGenOnly = 1; 515 } 516} 517 518// Conditional Branch 519class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>: 520 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16), 521 !strconcat(instr_asm, "\t$rs, $rt, $imm16"), 522 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { 523 let isBranch = 1; 524 let isTerminator = 1; 525 let hasDelaySlot = 1; 526 let Defs = [AT]; 527} 528 529class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op, 530 RegisterClass RC>: 531 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16), 532 !strconcat(instr_asm, "\t$rs, $imm16"), 533 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { 534 let rt = _rt; 535 let isBranch = 1; 536 let isTerminator = 1; 537 let hasDelaySlot = 1; 538 let Defs = [AT]; 539} 540 541// SetCC 542class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op, 543 RegisterClass RC>: 544 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 545 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 546 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], 547 IIAlu> { 548 let shamt = 0; 549} 550 551class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, 552 PatLeaf imm_type, RegisterClass RC>: 553 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 554 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 555 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], 556 IIAlu>; 557 558// Jump 559class JumpFJ<bits<6> op, string instr_asm>: 560 FJ<op, (outs), (ins jmptarget:$target), 561 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> { 562 let isBranch=1; 563 let isTerminator=1; 564 let isBarrier=1; 565 let hasDelaySlot = 1; 566 let Predicates = [RelocStatic, HasStandardEncoding]; 567 let DecoderMethod = "DecodeJumpTarget"; 568 let Defs = [AT]; 569} 570 571// Unconditional branch 572class UncondBranch<bits<6> op, string instr_asm>: 573 BranchBase<op, (outs), (ins brtarget:$imm16), 574 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { 575 let rs = 0; 576 let rt = 0; 577 let isBranch = 1; 578 let isTerminator = 1; 579 let isBarrier = 1; 580 let hasDelaySlot = 1; 581 let Predicates = [RelocPIC, HasStandardEncoding]; 582 let Defs = [AT]; 583} 584 585// Base class for indirect branch and return instruction classes. 586let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 587class JumpFR<RegisterClass RC, list<dag> pattern>: 588 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", pattern, IIBranch> { 589 let rt = 0; 590 let rd = 0; 591 let shamt = 0; 592} 593 594// Indirect branch 595class IndirectBranch<RegisterClass RC>: JumpFR<RC, [(brind RC:$rs)]> { 596 let isBranch = 1; 597 let isIndirectBranch = 1; 598} 599 600// Return instruction 601class RetBase<RegisterClass RC>: JumpFR<RC, []> { 602 let isReturn = 1; 603 let isCodeGenOnly = 1; 604 let hasCtrlDep = 1; 605 let hasExtraSrcRegAllocReq = 1; 606} 607 608// Jump and Link (Call) 609let isCall=1, hasDelaySlot=1, Defs = [RA] in { 610 class JumpLink<bits<6> op, string instr_asm>: 611 FJ<op, (outs), (ins calltarget:$target), 612 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 613 IIBranch> { 614 let DecoderMethod = "DecodeJumpTarget"; 615 } 616 617 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 618 RegisterClass RC>: 619 FR<op, func, (outs), (ins RC:$rs), 620 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 621 let rt = 0; 622 let rd = 31; 623 let shamt = 0; 624 } 625 626 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 627 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 628 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 629 let rt = _rt; 630 } 631} 632 633// Mul, Div 634class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 635 RegisterClass RC, list<Register> DefRegs>: 636 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 637 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 638 let rd = 0; 639 let shamt = 0; 640 let isCommutable = 1; 641 let Defs = DefRegs; 642 let neverHasSideEffects = 1; 643} 644 645class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 646 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 647 648class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 649 RegisterClass RC, list<Register> DefRegs>: 650 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 651 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 652 [(op RC:$rs, RC:$rt)], itin> { 653 let rd = 0; 654 let shamt = 0; 655 let Defs = DefRegs; 656} 657 658class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 659 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 660 661// Move from Hi/Lo 662class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC, 663 list<Register> UseRegs>: 664 FR<0x00, func, (outs RC:$rd), (ins), 665 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> { 666 let rs = 0; 667 let rt = 0; 668 let shamt = 0; 669 let Uses = UseRegs; 670 let neverHasSideEffects = 1; 671} 672 673class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC, 674 list<Register> DefRegs>: 675 FR<0x00, func, (outs), (ins RC:$rs), 676 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> { 677 let rt = 0; 678 let rd = 0; 679 let shamt = 0; 680 let Defs = DefRegs; 681 let neverHasSideEffects = 1; 682} 683 684class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 685 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 686 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 687 let isCodeGenOnly = 1; 688} 689 690// Count Leading Ones/Zeros in Word 691class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>: 692 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 693 !strconcat(instr_asm, "\t$rd, $rs"), 694 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, 695 Requires<[HasBitCount, HasStandardEncoding]> { 696 let shamt = 0; 697 let rt = rd; 698} 699 700class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: 701 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 702 !strconcat(instr_asm, "\t$rd, $rs"), 703 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, 704 Requires<[HasBitCount, HasStandardEncoding]> { 705 let shamt = 0; 706 let rt = rd; 707} 708 709// Sign Extend in Register. 710class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt, 711 RegisterClass RC>: 712 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), 713 !strconcat(instr_asm, "\t$rd, $rt"), 714 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { 715 let rs = 0; 716 let shamt = sa; 717 let Predicates = [HasSEInReg, HasStandardEncoding]; 718} 719 720// Subword Swap 721class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 722 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 723 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 724 let rs = 0; 725 let shamt = sa; 726 let Predicates = [HasSwap, HasStandardEncoding]; 727 let neverHasSideEffects = 1; 728} 729 730// Read Hardware 731class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 732 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 733 "rdhwr\t$rt, $rd", [], IIAlu> { 734 let rs = 0; 735 let shamt = 0; 736} 737 738// Ext and Ins 739class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 740 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 741 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 742 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 743 bits<5> pos; 744 bits<5> sz; 745 let rd = sz; 746 let shamt = pos; 747 let Predicates = [HasMips32r2, HasStandardEncoding]; 748} 749 750class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 751 FR<0x1f, _funct, (outs RC:$rt), 752 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 753 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 754 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 755 NoItinerary> { 756 bits<5> pos; 757 bits<5> sz; 758 let rd = sz; 759 let shamt = pos; 760 let Predicates = [HasMips32r2, HasStandardEncoding]; 761 let Constraints = "$src = $rt"; 762} 763 764// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 765class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC, 766 RegisterClass PRC> : 767 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 768 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), 769 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 770 771multiclass Atomic2Ops32<PatFrag Op, string Opstr> { 772 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, 773 Requires<[NotN64, HasStandardEncoding]>; 774 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, 775 Requires<[IsN64, HasStandardEncoding]> { 776 let DecoderNamespace = "Mips64"; 777 } 778} 779 780// Atomic Compare & Swap. 781class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC, 782 RegisterClass PRC> : 783 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 784 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), 785 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 786 787multiclass AtomicCmpSwap32<PatFrag Op, string Width> { 788 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, 789 Requires<[NotN64, HasStandardEncoding]>; 790 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, 791 Requires<[IsN64, HasStandardEncoding]> { 792 let DecoderNamespace = "Mips64"; 793 } 794} 795 796class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 797 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 798 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 799 let mayLoad = 1; 800} 801 802class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 803 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 804 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 805 let mayStore = 1; 806 let Constraints = "$rt = $dst"; 807} 808 809//===----------------------------------------------------------------------===// 810// Pseudo instructions 811//===----------------------------------------------------------------------===// 812 813// Return RA. 814let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 815def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>; 816 817let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 818def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 819 "!ADJCALLSTACKDOWN $amt", 820 [(callseq_start timm:$amt)]>; 821def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 822 "!ADJCALLSTACKUP $amt1", 823 [(callseq_end timm:$amt1, timm:$amt2)]>; 824} 825 826// When handling PIC code the assembler needs .cpload and .cprestore 827// directives. If the real instructions corresponding these directives 828// are used, we have the same behavior, but get also a bunch of warnings 829// from the assembler. 830let neverHasSideEffects = 1 in 831def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp), 832 ".cprestore\t$loc", []>; 833 834let usesCustomInserter = 1 in { 835 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">; 836 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">; 837 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">; 838 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">; 839 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">; 840 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">; 841 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">; 842 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">; 843 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">; 844 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">; 845 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">; 846 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">; 847 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">; 848 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">; 849 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">; 850 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">; 851 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">; 852 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">; 853 854 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">; 855 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">; 856 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">; 857 858 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">; 859 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">; 860 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">; 861} 862 863//===----------------------------------------------------------------------===// 864// Instruction definition 865//===----------------------------------------------------------------------===// 866 867class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 868 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 869 !strconcat(instr_asm, "\t$rt, $imm32")> ; 870def LoadImm32Reg : LoadImm32<"li",shamt,CPURegs>; 871//===----------------------------------------------------------------------===// 872// MipsI Instructions 873//===----------------------------------------------------------------------===// 874 875/// Arithmetic Instructions (ALU Immediate) 876def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>; 877def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>; 878def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; 879def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; 880def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>; 881def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>; 882def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>; 883def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; 884 885/// Arithmetic Instructions (3-Operand, R-Type) 886def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>; 887def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>; 888def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>; 889def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>; 890def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; 891def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; 892def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>; 893def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>; 894def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>; 895def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; 896 897/// Shift Instructions 898def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>; 899def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>; 900def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>; 901def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>; 902def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>; 903def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>; 904 905// Rotate Instructions 906let Predicates = [HasMips32r2, HasStandardEncoding] in { 907 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>; 908 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>; 909} 910 911/// Load and Store Instructions 912/// aligned 913defm LB : LoadM32<0x20, "lb", sextloadi8>; 914defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 915defm LH : LoadM32<0x21, "lh", sextloadi16>; 916defm LHu : LoadM32<0x25, "lhu", zextloadi16>; 917defm LW : LoadM32<0x23, "lw", load>; 918defm SB : StoreM32<0x28, "sb", truncstorei8>; 919defm SH : StoreM32<0x29, "sh", truncstorei16>; 920defm SW : StoreM32<0x2b, "sw", store>; 921 922/// load/store left/right 923defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 924defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 925defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 926defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 927 928let hasSideEffects = 1 in 929def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 930 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 931{ 932 bits<5> stype; 933 let Opcode = 0; 934 let Inst{25-11} = 0; 935 let Inst{10-6} = stype; 936 let Inst{5-0} = 15; 937} 938 939/// Load-linked, Store-conditional 940def LL : LLBase<0x30, "ll", CPURegs, mem>, 941 Requires<[NotN64, HasStandardEncoding]>; 942def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 943 Requires<[IsN64, HasStandardEncoding]> { 944 let DecoderNamespace = "Mips64"; 945} 946 947def SC : SCBase<0x38, "sc", CPURegs, mem>, 948 Requires<[NotN64, HasStandardEncoding]>; 949def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 950 Requires<[IsN64, HasStandardEncoding]> { 951 let DecoderNamespace = "Mips64"; 952} 953 954/// Jump and Branch Instructions 955def J : JumpFJ<0x02, "j">; 956def JR : IndirectBranch<CPURegs>; 957def B : UncondBranch<0x04, "b">; 958def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; 959def BNE : CBranch<0x05, "bne", setne, CPURegs>; 960def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; 961def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>; 962def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>; 963def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>; 964 965let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 966 hasDelaySlot = 1, Defs = [RA] in 967def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 968 969def JAL : JumpLink<0x03, "jal">; 970def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 971def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 972def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 973 974def RET : RetBase<CPURegs>; 975 976/// Multiply and Divide Instructions. 977def MULT : Mult32<0x18, "mult", IIImul>; 978def MULTu : Mult32<0x19, "multu", IIImul>; 979def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 980def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 981 982def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>; 983def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>; 984def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; 985def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; 986 987/// Sign Ext In Register Instructions. 988def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; 989def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; 990 991/// Count Leading 992def CLZ : CountLeading0<0x20, "clz", CPURegs>; 993def CLO : CountLeading1<0x21, "clo", CPURegs>; 994 995/// Word Swap Bytes Within Halfwords 996def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 997 998/// No operation 999let addr=0 in 1000 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 1001 1002// FrameIndexes are legalized when they are operands from load/store 1003// instructions. The same not happens for stack address copies, so an 1004// add op with mem ComplexPattern is used and the stack address copy 1005// can be matched. It's similar to Sparc LEA_ADDRi 1006def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1007 1008// DynAlloc node points to dynamically allocated stack space. 1009// $sp is added to the list of implicitly used registers to prevent dead code 1010// elimination from removing instructions that modify $sp. 1011let Uses = [SP] in 1012def DynAlloc : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1013 1014// MADD*/MSUB* 1015def MADD : MArithR<0, "madd", MipsMAdd, 1>; 1016def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 1017def MSUB : MArithR<4, "msub", MipsMSub>; 1018def MSUBU : MArithR<5, "msubu", MipsMSubu>; 1019 1020// MUL is a assembly macro in the current used ISAs. In recent ISA's 1021// it is a real instruction. 1022def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>, 1023 Requires<[HasMips32, HasStandardEncoding]>; 1024 1025def RDHWR : ReadHardware<CPURegs, HWRegs>; 1026 1027def EXT : ExtBase<0, "ext", CPURegs>; 1028def INS : InsBase<4, "ins", CPURegs>; 1029 1030//===----------------------------------------------------------------------===// 1031// Instruction aliases 1032//===----------------------------------------------------------------------===// 1033def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 1034def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 1035def : InstAlias<"addu $rs,$rt,$imm", 1036 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1037def : InstAlias<"add $rs,$rt,$imm", 1038 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1039def : InstAlias<"and $rs,$rt,$imm", 1040 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1041def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 1042def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 1043def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 1044def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 1045def : InstAlias<"slt $rs,$rt,$imm", 1046 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1047def : InstAlias<"xor $rs,$rt,$imm", 1048 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1049 1050//===----------------------------------------------------------------------===// 1051// Arbitrary patterns that map to one or more instructions 1052//===----------------------------------------------------------------------===// 1053 1054// Small immediates 1055def : MipsPat<(i32 immSExt16:$in), 1056 (ADDiu ZERO, imm:$in)>; 1057def : MipsPat<(i32 immZExt16:$in), 1058 (ORi ZERO, imm:$in)>; 1059def : MipsPat<(i32 immLow16Zero:$in), 1060 (LUi (HI16 imm:$in))>; 1061 1062// Arbitrary immediates 1063def : MipsPat<(i32 imm:$imm), 1064 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1065 1066// Carry MipsPatterns 1067def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1068 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1069def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1070 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1071def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1072 (ADDiu CPURegs:$src, imm:$imm)>; 1073 1074// Call 1075def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1076 (JAL tglobaladdr:$dst)>; 1077def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1078 (JAL texternalsym:$dst)>; 1079//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1080// (JALR CPURegs:$dst)>; 1081 1082// hi/lo relocs 1083def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1084def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1085def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1086def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1087def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1088 1089def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1090def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1091def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1092def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1093def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1094 1095def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1096 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1097def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1098 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1099def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1100 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1101def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1102 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1103def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1104 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1105 1106// gp_rel relocs 1107def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1108 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1109def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1110 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1111 1112// wrapper_pic 1113class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1114 MipsPat<(MipsWrapper RC:$gp, node:$in), 1115 (ADDiuOp RC:$gp, node:$in)>; 1116 1117def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1118def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1119def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1120def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1121def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1122def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1123 1124// Mips does not have "not", so we expand our way 1125def : MipsPat<(not CPURegs:$in), 1126 (NOR CPURegs:$in, ZERO)>; 1127 1128// extended loads 1129let Predicates = [NotN64, HasStandardEncoding] in { 1130 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1131 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1132 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1133} 1134let Predicates = [IsN64, HasStandardEncoding] in { 1135 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1136 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1137 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1138} 1139 1140// peepholes 1141let Predicates = [NotN64, HasStandardEncoding] in { 1142 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1143} 1144let Predicates = [IsN64, HasStandardEncoding] in { 1145 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1146} 1147 1148// brcond patterns 1149multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1150 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1151 Instruction SLTiuOp, Register ZEROReg> { 1152def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1153 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1154def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1155 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1156 1157def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1158 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1159def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1160 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1161def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1162 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1163def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1164 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1165 1166def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1167 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1168def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1169 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1170 1171def : MipsPat<(brcond RC:$cond, bb:$dst), 1172 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1173} 1174 1175defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1176 1177// setcc patterns 1178multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1179 Instruction SLTuOp, Register ZEROReg> { 1180 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1181 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1182 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1183 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1184} 1185 1186multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1187 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1188 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1189 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1190 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1191} 1192 1193multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1194 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1195 (SLTOp RC:$rhs, RC:$lhs)>; 1196 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1197 (SLTuOp RC:$rhs, RC:$lhs)>; 1198} 1199 1200multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1201 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1202 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1203 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1204 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1205} 1206 1207multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1208 Instruction SLTiuOp> { 1209 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1210 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1211 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1212 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1213} 1214 1215defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1216defm : SetlePats<CPURegs, SLT, SLTu>; 1217defm : SetgtPats<CPURegs, SLT, SLTu>; 1218defm : SetgePats<CPURegs, SLT, SLTu>; 1219defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1220 1221// select MipsDynAlloc 1222def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; 1223 1224// bswap pattern 1225def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1226 1227//===----------------------------------------------------------------------===// 1228// Floating Point Support 1229//===----------------------------------------------------------------------===// 1230 1231include "MipsInstrFPU.td" 1232include "Mips64InstrInfo.td" 1233include "MipsCondMov.td" 1234 1235// 1236// Mips16 1237 1238include "Mips16InstrFormats.td" 1239include "Mips16InstrInfo.td" 1240 1241// DSP 1242include "MipsDSPInstrFormats.td" 1243include "MipsDSPInstrInfo.td" 1244 1245