MipsInstrInfo.td revision c23061547de868c5971e1f7a12bc54a37a59a53f
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 81 [SDNPHasChain, SDNPSideEffect, 82 SDNPOptInGlue, SDNPOutGlue]>; 83 84// MAdd*/MSub* nodes 85def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93 94// DivRem(u) nodes 95def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99 100// Target constant nodes that are not part of any isel patterns and remain 101// unchanged can cause instructions with illegal operands to be emitted. 102// Wrapper node patterns give the instruction selector a chance to replace 103// target constant nodes that would otherwise remain unchanged with ADDiu 104// nodes. Without these wrapper node patterns, the following conditional move 105// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 106// compiled: 107// movn %got(d)($gp), %got(c)($gp), $4 108// This instruction is illegal since movn can take only register operands. 109 110def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 111 112def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 113 114def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 115def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 116 117def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 119def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 123def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133 134//===----------------------------------------------------------------------===// 135// Mips Instruction Predicate Definitions. 136//===----------------------------------------------------------------------===// 137def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 138 AssemblerPredicate<"FeatureSEInReg">; 139def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 140 AssemblerPredicate<"FeatureBitCount">; 141def HasSwap : Predicate<"Subtarget.hasSwap()">, 142 AssemblerPredicate<"FeatureSwap">; 143def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 144 AssemblerPredicate<"FeatureCondMov">; 145def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 146 AssemblerPredicate<"FeatureFPIdx">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 154 AssemblerPredicate<"!FeatureMips64">; 155def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 156 AssemblerPredicate<"FeatureMips64r2">; 157def IsN64 : Predicate<"Subtarget.isABI_N64()">, 158 AssemblerPredicate<"FeatureN64">; 159def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 160 AssemblerPredicate<"!FeatureN64">; 161def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 162 AssemblerPredicate<"FeatureMips16">; 163def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 164 AssemblerPredicate<"FeatureMips32">; 165def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 166 AssemblerPredicate<"FeatureMips32">; 167def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 168 AssemblerPredicate<"FeatureMips32">; 169def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 170 AssemblerPredicate<"!FeatureMips16">; 171 172class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 173 let Predicates = [HasStdEnc]; 174} 175 176class IsCommutable { 177 bit isCommutable = 1; 178} 179 180class IsBranch { 181 bit isBranch = 1; 182} 183 184class IsReturn { 185 bit isReturn = 1; 186} 187 188class IsCall { 189 bit isCall = 1; 190} 191 192class IsTailCall { 193 bit isCall = 1; 194 bit isTerminator = 1; 195 bit isReturn = 1; 196 bit isBarrier = 1; 197 bit hasExtraSrcRegAllocReq = 1; 198 bit isCodeGenOnly = 1; 199} 200 201class IsAsCheapAsAMove { 202 bit isAsCheapAsAMove = 1; 203} 204 205class NeverHasSideEffects { 206 bit neverHasSideEffects = 1; 207} 208 209//===----------------------------------------------------------------------===// 210// Instruction format superclass 211//===----------------------------------------------------------------------===// 212 213include "MipsInstrFormats.td" 214 215//===----------------------------------------------------------------------===// 216// Mips Operand, Complex Patterns and Transformations Definitions. 217//===----------------------------------------------------------------------===// 218 219// Instruction operand types 220def jmptarget : Operand<OtherVT> { 221 let EncoderMethod = "getJumpTargetOpValue"; 222} 223def brtarget : Operand<OtherVT> { 224 let EncoderMethod = "getBranchTargetOpValue"; 225 let OperandType = "OPERAND_PCREL"; 226 let DecoderMethod = "DecodeBranchTarget"; 227} 228def calltarget : Operand<iPTR> { 229 let EncoderMethod = "getJumpTargetOpValue"; 230} 231def calltarget64: Operand<i64>; 232def simm16 : Operand<i32> { 233 let DecoderMethod= "DecodeSimm16"; 234} 235def simm16_64 : Operand<i64>; 236def shamt : Operand<i32>; 237 238// Unsigned Operand 239def uimm16 : Operand<i32> { 240 let PrintMethod = "printUnsignedImm"; 241} 242 243def MipsMemAsmOperand : AsmOperandClass { 244 let Name = "Mem"; 245 let ParserMethod = "parseMemOperand"; 246} 247 248// Address operand 249def mem : Operand<i32> { 250 let PrintMethod = "printMemOperand"; 251 let MIOperandInfo = (ops CPURegs, simm16); 252 let EncoderMethod = "getMemEncoding"; 253 let ParserMatchClass = MipsMemAsmOperand; 254} 255 256def mem64 : Operand<i64> { 257 let PrintMethod = "printMemOperand"; 258 let MIOperandInfo = (ops CPU64Regs, simm16_64); 259 let EncoderMethod = "getMemEncoding"; 260 let ParserMatchClass = MipsMemAsmOperand; 261} 262 263def mem_ea : Operand<i32> { 264 let PrintMethod = "printMemOperandEA"; 265 let MIOperandInfo = (ops CPURegs, simm16); 266 let EncoderMethod = "getMemEncoding"; 267} 268 269def mem_ea_64 : Operand<i64> { 270 let PrintMethod = "printMemOperandEA"; 271 let MIOperandInfo = (ops CPU64Regs, simm16_64); 272 let EncoderMethod = "getMemEncoding"; 273} 274 275// size operand of ext instruction 276def size_ext : Operand<i32> { 277 let EncoderMethod = "getSizeExtEncoding"; 278 let DecoderMethod = "DecodeExtSize"; 279} 280 281// size operand of ins instruction 282def size_ins : Operand<i32> { 283 let EncoderMethod = "getSizeInsEncoding"; 284 let DecoderMethod = "DecodeInsSize"; 285} 286 287// Transformation Function - get the lower 16 bits. 288def LO16 : SDNodeXForm<imm, [{ 289 return getImm(N, N->getZExtValue() & 0xFFFF); 290}]>; 291 292// Transformation Function - get the higher 16 bits. 293def HI16 : SDNodeXForm<imm, [{ 294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 295}]>; 296 297// Node immediate fits as 16-bit sign extended on target immediate. 298// e.g. addi, andi 299def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 300 301// Node immediate fits as 16-bit zero extended on target immediate. 302// The LO16 param means that only the lower 16 bits of the node 303// immediate are caught. 304// e.g. addiu, sltiu 305def immZExt16 : PatLeaf<(imm), [{ 306 if (N->getValueType(0) == MVT::i32) 307 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 308 else 309 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 310}], LO16>; 311 312// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 313def immLow16Zero : PatLeaf<(imm), [{ 314 int64_t Val = N->getSExtValue(); 315 return isInt<32>(Val) && !(Val & 0xffff); 316}]>; 317 318// shamt field must fit in 5 bits. 319def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 320 321// Mips Address Mode! SDNode frameindex could possibily be a match 322// since load and store instructions from stack used it. 323def addr : 324 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 325 326//===----------------------------------------------------------------------===// 327// Instructions specific format 328//===----------------------------------------------------------------------===// 329 330/// Move Control Registers From/To CPU Registers 331def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt), 332 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 333def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 334 335def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel), 336 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">; 337def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 338 339def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt), 340 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 341def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 342 343def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), 344 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">; 345def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 346 347// Arithmetic and logical instructions with 3 register operands. 348class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0, 349 InstrItinClass Itin = NoItinerary, 350 SDPatternOperator OpNode = null_frag>: 351 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 352 !strconcat(opstr, "\t$rd, $rs, $rt"), 353 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> { 354 let isCommutable = isComm; 355 let isReMaterializable = 1; 356} 357 358// Arithmetic and logical instructions with 2 register operands. 359class ArithLogicI<string opstr, Operand Od, RegisterClass RC, 360 SDPatternOperator imm_type = null_frag, 361 SDPatternOperator OpNode = null_frag> : 362 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16), 363 !strconcat(opstr, "\t$rt, $rs, $imm16"), 364 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> { 365 let isReMaterializable = 1; 366} 367 368// Arithmetic Multiply ADD/SUB 369let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 370class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 371 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 372 !strconcat(instr_asm, "\t$rs, $rt"), 373 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 374 let rd = 0; 375 let shamt = 0; 376 let isCommutable = isComm; 377} 378 379// Logical 380class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: 381 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 382 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 383 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> { 384 let shamt = 0; 385 let isCommutable = 1; 386} 387 388// Shifts 389class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd, 390 RegisterClass RC, SDPatternOperator OpNode> : 391 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 392 !strconcat(opstr, "\t$rd, $rt, $shamt"), 393 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 394 395// 32-bit shift instructions. 396class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> : 397 shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>; 398 399class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>: 400 InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 401 !strconcat(opstr, "\t$rd, $rt, $rs"), 402 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>; 403 404// Load Upper Imediate 405class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 406 FI<op, (outs RC:$rt), (ins Imm:$imm16), 407 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove { 408 let rs = 0; 409 let neverHasSideEffects = 1; 410 let isReMaterializable = 1; 411} 412 413class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 414 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 415 bits<21> addr; 416 let Inst{25-21} = addr{20-16}; 417 let Inst{15-0} = addr{15-0}; 418 let DecoderMethod = "DecodeMem"; 419} 420 421// Memory Load/Store 422let canFoldAsLoad = 1 in 423class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 424 Operand MemOpnd, bit Pseudo>: 425 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 426 !strconcat(instr_asm, "\t$rt, $addr"), 427 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 428 let isPseudo = Pseudo; 429} 430 431class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 432 Operand MemOpnd, bit Pseudo>: 433 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 434 !strconcat(instr_asm, "\t$rt, $addr"), 435 [(OpNode RC:$rt, addr:$addr)], IIStore> { 436 let isPseudo = Pseudo; 437} 438 439// 32-bit load. 440multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 441 bit Pseudo = 0> { 442 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 443 Requires<[NotN64, HasStdEnc]>; 444 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 445 Requires<[IsN64, HasStdEnc]> { 446 let DecoderNamespace = "Mips64"; 447 let isCodeGenOnly = 1; 448 } 449} 450 451// 64-bit load. 452multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 453 bit Pseudo = 0> { 454 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 455 Requires<[NotN64, HasStdEnc]>; 456 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 457 Requires<[IsN64, HasStdEnc]> { 458 let DecoderNamespace = "Mips64"; 459 let isCodeGenOnly = 1; 460 } 461} 462 463// 32-bit store. 464multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 465 bit Pseudo = 0> { 466 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 467 Requires<[NotN64, HasStdEnc]>; 468 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 469 Requires<[IsN64, HasStdEnc]> { 470 let DecoderNamespace = "Mips64"; 471 let isCodeGenOnly = 1; 472 } 473} 474 475// 64-bit store. 476multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 477 bit Pseudo = 0> { 478 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 479 Requires<[NotN64, HasStdEnc]>; 480 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 481 Requires<[IsN64, HasStdEnc]> { 482 let DecoderNamespace = "Mips64"; 483 let isCodeGenOnly = 1; 484 } 485} 486 487// Load/Store Left/Right 488let canFoldAsLoad = 1 in 489class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 490 RegisterClass RC, Operand MemOpnd> : 491 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 492 !strconcat(instr_asm, "\t$rt, $addr"), 493 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 494 string Constraints = "$src = $rt"; 495} 496 497class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 498 RegisterClass RC, Operand MemOpnd>: 499 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 500 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 501 IIStore>; 502 503// 32-bit load left/right. 504multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 505 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 506 Requires<[NotN64, HasStdEnc]>; 507 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 508 Requires<[IsN64, HasStdEnc]> { 509 let DecoderNamespace = "Mips64"; 510 let isCodeGenOnly = 1; 511 } 512} 513 514// 64-bit load left/right. 515multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 516 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 517 Requires<[NotN64, HasStdEnc]>; 518 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 519 Requires<[IsN64, HasStdEnc]> { 520 let DecoderNamespace = "Mips64"; 521 let isCodeGenOnly = 1; 522 } 523} 524 525// 32-bit store left/right. 526multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 527 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 528 Requires<[NotN64, HasStdEnc]>; 529 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 530 Requires<[IsN64, HasStdEnc]> { 531 let DecoderNamespace = "Mips64"; 532 let isCodeGenOnly = 1; 533 } 534} 535 536// 64-bit store left/right. 537multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 538 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 539 Requires<[NotN64, HasStdEnc]>; 540 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 541 Requires<[IsN64, HasStdEnc]> { 542 let DecoderNamespace = "Mips64"; 543 let isCodeGenOnly = 1; 544 } 545} 546 547// Conditional Branch 548class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 549 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 550 !strconcat(opstr, "\t$rs, $rt, $offset"), 551 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 552 FrmI> { 553 let isBranch = 1; 554 let isTerminator = 1; 555 let hasDelaySlot = 1; 556 let Defs = [AT]; 557} 558 559class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 560 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 561 !strconcat(opstr, "\t$rs, $offset"), 562 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 563 let isBranch = 1; 564 let isTerminator = 1; 565 let hasDelaySlot = 1; 566 let Defs = [AT]; 567} 568 569// SetCC 570class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op, 571 RegisterClass RC>: 572 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 573 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 574 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], 575 IIAlu> { 576 let shamt = 0; 577} 578 579class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, 580 PatLeaf imm_type, RegisterClass RC>: 581 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 582 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 583 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], 584 IIAlu>; 585 586// Jump 587class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm, 588 SDPatternOperator operator, SDPatternOperator targetoperator>: 589 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"), 590 [(operator targetoperator:$target)], IIBranch> { 591 let isTerminator=1; 592 let isBarrier=1; 593 let hasDelaySlot = 1; 594 let DecoderMethod = "DecodeJumpTarget"; 595 let Defs = [AT]; 596} 597 598// Unconditional branch 599class UncondBranch<string opstr> : 600 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 601 [(br bb:$offset)], IIBranch, FrmI> { 602 let isBranch = 1; 603 let isTerminator = 1; 604 let isBarrier = 1; 605 let hasDelaySlot = 1; 606 let Predicates = [RelocPIC, HasStdEnc]; 607 let Defs = [AT]; 608} 609 610// Base class for indirect branch and return instruction classes. 611let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 612class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 613 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> { 614 let rt = 0; 615 let rd = 0; 616 let shamt = 0; 617} 618 619// Indirect branch 620class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 621 let isBranch = 1; 622 let isIndirectBranch = 1; 623} 624 625// Return instruction 626class RetBase<RegisterClass RC>: JumpFR<RC> { 627 let isReturn = 1; 628 let isCodeGenOnly = 1; 629 let hasCtrlDep = 1; 630 let hasExtraSrcRegAllocReq = 1; 631} 632 633// Jump and Link (Call) 634let isCall=1, hasDelaySlot=1, Defs = [RA] in { 635 class JumpLink<bits<6> op, string instr_asm>: 636 FJ<op, (outs), (ins calltarget:$target), 637 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 638 IIBranch> { 639 let DecoderMethod = "DecodeJumpTarget"; 640 } 641 642 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 643 RegisterClass RC>: 644 FR<op, func, (outs), (ins RC:$rs), 645 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 646 let rt = 0; 647 let rd = 31; 648 let shamt = 0; 649 } 650 651 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 652 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 653 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 654 let rt = _rt; 655 } 656} 657 658// Mul, Div 659class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 660 RegisterClass RC, list<Register> DefRegs>: 661 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 662 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 663 let rd = 0; 664 let shamt = 0; 665 let isCommutable = 1; 666 let Defs = DefRegs; 667 let neverHasSideEffects = 1; 668} 669 670class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 671 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 672 673class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 674 RegisterClass RC, list<Register> DefRegs>: 675 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 676 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 677 [(op RC:$rs, RC:$rt)], itin> { 678 let rd = 0; 679 let shamt = 0; 680 let Defs = DefRegs; 681} 682 683class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 684 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 685 686// Move from Hi/Lo 687class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC, 688 list<Register> UseRegs>: 689 FR<0x00, func, (outs RC:$rd), (ins), 690 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> { 691 let rs = 0; 692 let rt = 0; 693 let shamt = 0; 694 let Uses = UseRegs; 695 let neverHasSideEffects = 1; 696} 697 698class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC, 699 list<Register> DefRegs>: 700 FR<0x00, func, (outs), (ins RC:$rs), 701 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> { 702 let rt = 0; 703 let rd = 0; 704 let shamt = 0; 705 let Defs = DefRegs; 706 let neverHasSideEffects = 1; 707} 708 709class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 710 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 711 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 712 let isCodeGenOnly = 1; 713} 714 715// Count Leading Ones/Zeros in Word 716class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>: 717 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 718 !strconcat(instr_asm, "\t$rd, $rs"), 719 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, 720 Requires<[HasBitCount, HasStdEnc]> { 721 let shamt = 0; 722 let rt = rd; 723} 724 725class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: 726 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 727 !strconcat(instr_asm, "\t$rd, $rs"), 728 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, 729 Requires<[HasBitCount, HasStdEnc]> { 730 let shamt = 0; 731 let rt = rd; 732} 733 734// Sign Extend in Register. 735class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt, 736 RegisterClass RC>: 737 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), 738 !strconcat(instr_asm, "\t$rd, $rt"), 739 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { 740 let rs = 0; 741 let shamt = sa; 742 let Predicates = [HasSEInReg, HasStdEnc]; 743} 744 745// Subword Swap 746class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 747 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 748 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 749 let rs = 0; 750 let shamt = sa; 751 let Predicates = [HasSwap, HasStdEnc]; 752 let neverHasSideEffects = 1; 753} 754 755// Read Hardware 756class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 757 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 758 "rdhwr\t$rt, $rd", [], IIAlu> { 759 let rs = 0; 760 let shamt = 0; 761} 762 763// Ext and Ins 764class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 765 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 766 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 767 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 768 bits<5> pos; 769 bits<5> sz; 770 let rd = sz; 771 let shamt = pos; 772 let Predicates = [HasMips32r2, HasStdEnc]; 773} 774 775class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 776 FR<0x1f, _funct, (outs RC:$rt), 777 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 778 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 779 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 780 NoItinerary> { 781 bits<5> pos; 782 bits<5> sz; 783 let rd = sz; 784 let shamt = pos; 785 let Predicates = [HasMips32r2, HasStdEnc]; 786 let Constraints = "$src = $rt"; 787} 788 789// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 790class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 791 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 792 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 793 794multiclass Atomic2Ops32<PatFrag Op> { 795 def #NAME# : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 796 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 797 Requires<[IsN64, HasStdEnc]> { 798 let DecoderNamespace = "Mips64"; 799 } 800} 801 802// Atomic Compare & Swap. 803class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 804 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 805 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 806 807multiclass AtomicCmpSwap32<PatFrag Op> { 808 def #NAME# : AtomicCmpSwap<Op, CPURegs, CPURegs>, 809 Requires<[NotN64, HasStdEnc]>; 810 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 811 Requires<[IsN64, HasStdEnc]> { 812 let DecoderNamespace = "Mips64"; 813 } 814} 815 816class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 817 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 818 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 819 let mayLoad = 1; 820} 821 822class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 823 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 824 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 825 let mayStore = 1; 826 let Constraints = "$rt = $dst"; 827} 828 829//===----------------------------------------------------------------------===// 830// Pseudo instructions 831//===----------------------------------------------------------------------===// 832 833// Return RA. 834let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 835def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 836 837let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 838def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 839 [(callseq_start timm:$amt)]>; 840def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 841 [(callseq_end timm:$amt1, timm:$amt2)]>; 842} 843 844let usesCustomInserter = 1 in { 845 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 846 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 847 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 848 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 849 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 850 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 851 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 852 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 853 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 854 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 855 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 856 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 857 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 858 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 859 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 860 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 861 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 862 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 863 864 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 865 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 866 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 867 868 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 869 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 870 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 871} 872 873//===----------------------------------------------------------------------===// 874// Instruction definition 875//===----------------------------------------------------------------------===// 876 877class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 878 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 879 !strconcat(instr_asm, "\t$rt, $imm32")> ; 880def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>; 881 882class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> : 883 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr), 884 !strconcat(instr_asm, "\t$rt, $addr")> ; 885def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>; 886 887class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> : 888 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 889 !strconcat(instr_asm, "\t$rt, $imm32")> ; 890def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>; 891 892//===----------------------------------------------------------------------===// 893// MipsI Instructions 894//===----------------------------------------------------------------------===// 895 896/// Arithmetic Instructions (ALU Immediate) 897def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>, 898 ADDI_FM<0x9>, IsAsCheapAsAMove; 899def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>; 900def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; 901def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; 902def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>; 903def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>; 904def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>; 905def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; 906 907/// Arithmetic Instructions (3-Operand, R-Type) 908def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>; 909def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 910def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>; 911def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>; 912def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; 913def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; 914def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>; 915def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>; 916def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 917def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; 918 919/// Shift Instructions 920def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>; 921def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>; 922def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>; 923def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>; 924def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>; 925def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>; 926 927// Rotate Instructions 928let Predicates = [HasMips32r2, HasStdEnc] in { 929 def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>; 930 def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>; 931} 932 933/// Load and Store Instructions 934/// aligned 935defm LB : LoadM32<0x20, "lb", sextloadi8>; 936defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 937defm LH : LoadM32<0x21, "lh", sextloadi16>; 938defm LHu : LoadM32<0x25, "lhu", zextloadi16>; 939defm LW : LoadM32<0x23, "lw", load>; 940defm SB : StoreM32<0x28, "sb", truncstorei8>; 941defm SH : StoreM32<0x29, "sh", truncstorei16>; 942defm SW : StoreM32<0x2b, "sw", store>; 943 944/// load/store left/right 945defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 946defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 947defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 948defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 949 950let hasSideEffects = 1 in 951def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 952 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 953{ 954 bits<5> stype; 955 let Opcode = 0; 956 let Inst{25-11} = 0; 957 let Inst{10-6} = stype; 958 let Inst{5-0} = 15; 959} 960 961/// Load-linked, Store-conditional 962def LL : LLBase<0x30, "ll", CPURegs, mem>, 963 Requires<[NotN64, HasStdEnc]>; 964def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 965 Requires<[IsN64, HasStdEnc]> { 966 let DecoderNamespace = "Mips64"; 967} 968 969def SC : SCBase<0x38, "sc", CPURegs, mem>, 970 Requires<[NotN64, HasStdEnc]>; 971def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 972 Requires<[IsN64, HasStdEnc]> { 973 let DecoderNamespace = "Mips64"; 974} 975 976/// Jump and Branch Instructions 977def J : JumpFJ<0x02, jmptarget, "j", br, bb>, 978 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 979def JR : IndirectBranch<CPURegs>; 980def B : UncondBranch<"b">, B_FM; 981def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 982def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 983def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 984def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 985def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 986def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 987 988let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 989 hasDelaySlot = 1, Defs = [RA] in 990def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 991 992def JAL : JumpLink<0x03, "jal">; 993def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 994def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 995def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 996def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall; 997def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall; 998 999def RET : RetBase<CPURegs>; 1000 1001/// Multiply and Divide Instructions. 1002def MULT : Mult32<0x18, "mult", IIImul>; 1003def MULTu : Mult32<0x19, "multu", IIImul>; 1004def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 1005def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 1006 1007def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>; 1008def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>; 1009def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; 1010def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; 1011 1012/// Sign Ext In Register Instructions. 1013def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; 1014def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; 1015 1016/// Count Leading 1017def CLZ : CountLeading0<0x20, "clz", CPURegs>; 1018def CLO : CountLeading1<0x21, "clo", CPURegs>; 1019 1020/// Word Swap Bytes Within Halfwords 1021def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 1022 1023/// No operation 1024let addr=0 in 1025 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 1026 1027// FrameIndexes are legalized when they are operands from load/store 1028// instructions. The same not happens for stack address copies, so an 1029// add op with mem ComplexPattern is used and the stack address copy 1030// can be matched. It's similar to Sparc LEA_ADDRi 1031def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1032 1033// MADD*/MSUB* 1034def MADD : MArithR<0, "madd", MipsMAdd, 1>; 1035def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 1036def MSUB : MArithR<4, "msub", MipsMSub>; 1037def MSUBU : MArithR<5, "msubu", MipsMSubu>; 1038 1039// MUL is a assembly macro in the current used ISAs. In recent ISA's 1040// it is a real instruction. 1041def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 0x02>; 1042 1043def RDHWR : ReadHardware<CPURegs, HWRegs>; 1044 1045def EXT : ExtBase<0, "ext", CPURegs>; 1046def INS : InsBase<4, "ins", CPURegs>; 1047 1048//===----------------------------------------------------------------------===// 1049// Instruction aliases 1050//===----------------------------------------------------------------------===// 1051def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 1052def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 1053def : InstAlias<"addu $rs,$rt,$imm", 1054 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1055def : InstAlias<"add $rs,$rt,$imm", 1056 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1057def : InstAlias<"and $rs,$rt,$imm", 1058 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1059def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 1060def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 1061def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 1062def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 1063def : InstAlias<"slt $rs,$rt,$imm", 1064 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1065def : InstAlias<"xor $rs,$rt,$imm", 1066 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1067 1068//===----------------------------------------------------------------------===// 1069// Arbitrary patterns that map to one or more instructions 1070//===----------------------------------------------------------------------===// 1071 1072// Small immediates 1073def : MipsPat<(i32 immSExt16:$in), 1074 (ADDiu ZERO, imm:$in)>; 1075def : MipsPat<(i32 immZExt16:$in), 1076 (ORi ZERO, imm:$in)>; 1077def : MipsPat<(i32 immLow16Zero:$in), 1078 (LUi (HI16 imm:$in))>; 1079 1080// Arbitrary immediates 1081def : MipsPat<(i32 imm:$imm), 1082 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1083 1084// Carry MipsPatterns 1085def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1086 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1087def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1088 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1089def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1090 (ADDiu CPURegs:$src, imm:$imm)>; 1091 1092// Call 1093def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1094 (JAL tglobaladdr:$dst)>; 1095def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1096 (JAL texternalsym:$dst)>; 1097//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1098// (JALR CPURegs:$dst)>; 1099 1100// Tail call 1101def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1102 (TAILCALL tglobaladdr:$dst)>; 1103def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1104 (TAILCALL texternalsym:$dst)>; 1105// hi/lo relocs 1106def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1107def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1108def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1109def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1110def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1111def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1112 1113def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1114def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1115def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1116def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1117def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1118def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1119 1120def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1121 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1122def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1123 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1124def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1125 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1126def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1127 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1128def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1129 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1130 1131// gp_rel relocs 1132def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1133 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1134def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1135 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1136 1137// wrapper_pic 1138class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1139 MipsPat<(MipsWrapper RC:$gp, node:$in), 1140 (ADDiuOp RC:$gp, node:$in)>; 1141 1142def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1143def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1144def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1145def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1146def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1147def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1148 1149// Mips does not have "not", so we expand our way 1150def : MipsPat<(not CPURegs:$in), 1151 (NOR CPURegs:$in, ZERO)>; 1152 1153// extended loads 1154let Predicates = [NotN64, HasStdEnc] in { 1155 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1156 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1157 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1158} 1159let Predicates = [IsN64, HasStdEnc] in { 1160 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1161 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1162 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1163} 1164 1165// peepholes 1166let Predicates = [NotN64, HasStdEnc] in { 1167 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1168} 1169let Predicates = [IsN64, HasStdEnc] in { 1170 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1171} 1172 1173// brcond patterns 1174multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1175 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1176 Instruction SLTiuOp, Register ZEROReg> { 1177def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1178 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1179def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1180 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1181 1182def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1183 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1184def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1185 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1186def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1187 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1188def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1189 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1190 1191def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1192 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1193def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1194 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1195 1196def : MipsPat<(brcond RC:$cond, bb:$dst), 1197 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1198} 1199 1200defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1201 1202// setcc patterns 1203multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1204 Instruction SLTuOp, Register ZEROReg> { 1205 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1206 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1207 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1208 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1209} 1210 1211multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1212 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1213 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1214 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1215 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1216} 1217 1218multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1219 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1220 (SLTOp RC:$rhs, RC:$lhs)>; 1221 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1222 (SLTuOp RC:$rhs, RC:$lhs)>; 1223} 1224 1225multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1226 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1227 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1228 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1229 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1230} 1231 1232multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1233 Instruction SLTiuOp> { 1234 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1235 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1236 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1237 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1238} 1239 1240defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1241defm : SetlePats<CPURegs, SLT, SLTu>; 1242defm : SetgtPats<CPURegs, SLT, SLTu>; 1243defm : SetgePats<CPURegs, SLT, SLTu>; 1244defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1245 1246// bswap pattern 1247def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1248 1249//===----------------------------------------------------------------------===// 1250// Floating Point Support 1251//===----------------------------------------------------------------------===// 1252 1253include "MipsInstrFPU.td" 1254include "Mips64InstrInfo.td" 1255include "MipsCondMov.td" 1256 1257// 1258// Mips16 1259 1260include "Mips16InstrFormats.td" 1261include "Mips16InstrInfo.td" 1262 1263// DSP 1264include "MipsDSPInstrFormats.td" 1265include "MipsDSPInstrInfo.td" 1266 1267