MipsInstrInfo.td revision d35d5bdfc41ff401f938e49e844d707462405428
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>, 27 SDTCisVT<2, i32>]>; 28def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 29 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 30def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 31 SDTCisSameAs<1, 2>]>; 32def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 33 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 34 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 35def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 36 37def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 38 39def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 40 41def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 42 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 43def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 44 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 45 SDTCisSameAs<0, 4>]>; 46 47def SDTMipsLoadLR : SDTypeProfile<1, 2, 48 [SDTCisInt<0>, SDTCisPtrTy<1>, 49 SDTCisSameAs<0, 2>]>; 50 51// Call 52def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 53 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 54 SDNPVariadic]>; 55 56// Tail call 57def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 58 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 59 60// Hi and Lo nodes are used to handle global addresses. Used on 61// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 62// static model. (nothing to do with Mips Registers Hi and Lo) 63def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 64def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 65def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 66 67// TlsGd node is used to handle General Dynamic TLS 68def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 69 70// TprelHi and TprelLo nodes are used to handle Local Exec TLS 71def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 72def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 73 74// Thread pointer 75def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 76 77// Return 78def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 79 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 80 81// These are target-independent nodes, but have target-specific formats. 82def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 83 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 84def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 85 [SDNPHasChain, SDNPSideEffect, 86 SDNPOptInGlue, SDNPOutGlue]>; 87 88// Node used to extract integer from LO/HI register. 89def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>; 90 91// Node used to insert 32-bit integers to LOHI register pair. 92def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>; 93 94// Mult nodes. 95def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 96def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 97 98// MAdd*/MSub* nodes 99def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 100def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 101def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 102def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 103 104// DivRem(u) nodes 105def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 106def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 107def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, [SDNPOutGlue]>; 108def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110 111// Target constant nodes that are not part of any isel patterns and remain 112// unchanged can cause instructions with illegal operands to be emitted. 113// Wrapper node patterns give the instruction selector a chance to replace 114// target constant nodes that would otherwise remain unchanged with ADDiu 115// nodes. Without these wrapper node patterns, the following conditional move 116// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 117// compiled: 118// movn %got(d)($gp), %got(c)($gp), $4 119// This instruction is illegal since movn can take only register operands. 120 121def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 122 123def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 124 125def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 126def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 127 128def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 130def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 134def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 137 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 138def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 141 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 142def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144 145//===----------------------------------------------------------------------===// 146// Mips Instruction Predicate Definitions. 147//===----------------------------------------------------------------------===// 148def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 149 AssemblerPredicate<"FeatureSEInReg">; 150def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 151 AssemblerPredicate<"FeatureBitCount">; 152def HasSwap : Predicate<"Subtarget.hasSwap()">, 153 AssemblerPredicate<"FeatureSwap">; 154def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 155 AssemblerPredicate<"FeatureCondMov">; 156def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 157 AssemblerPredicate<"FeatureFPIdx">; 158def HasMips32 : Predicate<"Subtarget.hasMips32()">, 159 AssemblerPredicate<"FeatureMips32">; 160def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 161 AssemblerPredicate<"FeatureMips32r2">; 162def HasMips64 : Predicate<"Subtarget.hasMips64()">, 163 AssemblerPredicate<"FeatureMips64">; 164def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 165 AssemblerPredicate<"!FeatureMips64">; 166def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 167 AssemblerPredicate<"FeatureMips64r2">; 168def IsN64 : Predicate<"Subtarget.isABI_N64()">, 169 AssemblerPredicate<"FeatureN64">; 170def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 171 AssemblerPredicate<"!FeatureN64">; 172def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 173 AssemblerPredicate<"FeatureMips16">; 174def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 175 AssemblerPredicate<"FeatureMips32">; 176def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 177 AssemblerPredicate<"FeatureMips32">; 178def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 179 AssemblerPredicate<"FeatureMips32">; 180def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 181 AssemblerPredicate<"!FeatureMips16">; 182 183class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 184 let Predicates = [HasStdEnc]; 185} 186 187class IsCommutable { 188 bit isCommutable = 1; 189} 190 191class IsBranch { 192 bit isBranch = 1; 193} 194 195class IsReturn { 196 bit isReturn = 1; 197} 198 199class IsCall { 200 bit isCall = 1; 201} 202 203class IsTailCall { 204 bit isCall = 1; 205 bit isTerminator = 1; 206 bit isReturn = 1; 207 bit isBarrier = 1; 208 bit hasExtraSrcRegAllocReq = 1; 209 bit isCodeGenOnly = 1; 210} 211 212class IsAsCheapAsAMove { 213 bit isAsCheapAsAMove = 1; 214} 215 216class NeverHasSideEffects { 217 bit neverHasSideEffects = 1; 218} 219 220//===----------------------------------------------------------------------===// 221// Instruction format superclass 222//===----------------------------------------------------------------------===// 223 224include "MipsInstrFormats.td" 225 226//===----------------------------------------------------------------------===// 227// Mips Operand, Complex Patterns and Transformations Definitions. 228//===----------------------------------------------------------------------===// 229 230// Instruction operand types 231def jmptarget : Operand<OtherVT> { 232 let EncoderMethod = "getJumpTargetOpValue"; 233} 234def brtarget : Operand<OtherVT> { 235 let EncoderMethod = "getBranchTargetOpValue"; 236 let OperandType = "OPERAND_PCREL"; 237 let DecoderMethod = "DecodeBranchTarget"; 238} 239def calltarget : Operand<iPTR> { 240 let EncoderMethod = "getJumpTargetOpValue"; 241} 242def calltarget64: Operand<i64>; 243def simm16 : Operand<i32> { 244 let DecoderMethod= "DecodeSimm16"; 245} 246 247def simm20 : Operand<i32> { 248} 249 250def simm16_64 : Operand<i64>; 251def shamt : Operand<i32>; 252 253// Unsigned Operand 254def uimm16 : Operand<i32> { 255 let PrintMethod = "printUnsignedImm"; 256} 257 258def MipsMemAsmOperand : AsmOperandClass { 259 let Name = "Mem"; 260 let ParserMethod = "parseMemOperand"; 261} 262 263// Address operand 264def mem : Operand<i32> { 265 let PrintMethod = "printMemOperand"; 266 let MIOperandInfo = (ops CPURegs, simm16); 267 let EncoderMethod = "getMemEncoding"; 268 let ParserMatchClass = MipsMemAsmOperand; 269 let OperandType = "OPERAND_MEMORY"; 270} 271 272def mem64 : Operand<i64> { 273 let PrintMethod = "printMemOperand"; 274 let MIOperandInfo = (ops CPU64Regs, simm16_64); 275 let EncoderMethod = "getMemEncoding"; 276 let ParserMatchClass = MipsMemAsmOperand; 277 let OperandType = "OPERAND_MEMORY"; 278} 279 280def mem_ea : Operand<i32> { 281 let PrintMethod = "printMemOperandEA"; 282 let MIOperandInfo = (ops CPURegs, simm16); 283 let EncoderMethod = "getMemEncoding"; 284 let OperandType = "OPERAND_MEMORY"; 285} 286 287def mem_ea_64 : Operand<i64> { 288 let PrintMethod = "printMemOperandEA"; 289 let MIOperandInfo = (ops CPU64Regs, simm16_64); 290 let EncoderMethod = "getMemEncoding"; 291 let OperandType = "OPERAND_MEMORY"; 292} 293 294// size operand of ext instruction 295def size_ext : Operand<i32> { 296 let EncoderMethod = "getSizeExtEncoding"; 297 let DecoderMethod = "DecodeExtSize"; 298} 299 300// size operand of ins instruction 301def size_ins : Operand<i32> { 302 let EncoderMethod = "getSizeInsEncoding"; 303 let DecoderMethod = "DecodeInsSize"; 304} 305 306// Transformation Function - get the lower 16 bits. 307def LO16 : SDNodeXForm<imm, [{ 308 return getImm(N, N->getZExtValue() & 0xFFFF); 309}]>; 310 311// Transformation Function - get the higher 16 bits. 312def HI16 : SDNodeXForm<imm, [{ 313 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 314}]>; 315 316// Plus 1. 317def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 318 319// Node immediate fits as 16-bit sign extended on target immediate. 320// e.g. addi, andi 321def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 322 323// Node immediate fits as 16-bit sign extended on target immediate. 324// e.g. addi, andi 325def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 326 327// Node immediate fits as 15-bit sign extended on target immediate. 328// e.g. addi, andi 329def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 330 331// Node immediate fits as 16-bit zero extended on target immediate. 332// The LO16 param means that only the lower 16 bits of the node 333// immediate are caught. 334// e.g. addiu, sltiu 335def immZExt16 : PatLeaf<(imm), [{ 336 if (N->getValueType(0) == MVT::i32) 337 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 338 else 339 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 340}], LO16>; 341 342// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 343def immLow16Zero : PatLeaf<(imm), [{ 344 int64_t Val = N->getSExtValue(); 345 return isInt<32>(Val) && !(Val & 0xffff); 346}]>; 347 348// shamt field must fit in 5 bits. 349def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 350 351// True if (N + 1) fits in 16-bit field. 352def immSExt16Plus1 : PatLeaf<(imm), [{ 353 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 354}]>; 355 356// Mips Address Mode! SDNode frameindex could possibily be a match 357// since load and store instructions from stack used it. 358def addr : 359 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 360 361def addrRegImm : 362 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 363 364def addrDefault : 365 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 366 367//===----------------------------------------------------------------------===// 368// Instructions specific format 369//===----------------------------------------------------------------------===// 370 371// Arithmetic and logical instructions with 3 register operands. 372class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 373 InstrItinClass Itin = NoItinerary, 374 SDPatternOperator OpNode = null_frag>: 375 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 376 !strconcat(opstr, "\t$rd, $rs, $rt"), 377 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { 378 let isCommutable = isComm; 379 let isReMaterializable = 1; 380 string BaseOpcode; 381 string Arch; 382} 383 384// Arithmetic and logical instructions with 2 register operands. 385class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 386 SDPatternOperator imm_type = null_frag, 387 SDPatternOperator OpNode = null_frag> : 388 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 389 !strconcat(opstr, "\t$rt, $rs, $imm16"), 390 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> { 391 let isReMaterializable = 1; 392} 393 394// Arithmetic Multiply ADD/SUB 395class MArithR<string opstr, bit isComm = 0> : 396 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 397 !strconcat(opstr, "\t$rs, $rt"), [], IIImul, FrmR> { 398 let Defs = [HI, LO]; 399 let Uses = [HI, LO]; 400 let isCommutable = isComm; 401} 402 403// Logical 404class LogicNOR<string opstr, RegisterOperand RC>: 405 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 406 !strconcat(opstr, "\t$rd, $rs, $rt"), 407 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 408 let isCommutable = 1; 409} 410 411// Shifts 412class shift_rotate_imm<string opstr, Operand ImmOpnd, 413 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 414 SDPatternOperator PF = null_frag> : 415 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 416 !strconcat(opstr, "\t$rd, $rt, $shamt"), 417 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 418 419class shift_rotate_reg<string opstr, RegisterOperand RC, 420 SDPatternOperator OpNode = null_frag>: 421 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 422 !strconcat(opstr, "\t$rd, $rt, $rs"), 423 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR>; 424 425// Load Upper Imediate 426class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 427 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 428 [], IIAlu, FrmI>, IsAsCheapAsAMove { 429 let neverHasSideEffects = 1; 430 let isReMaterializable = 1; 431} 432 433class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 434 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 435 bits<21> addr; 436 let Inst{25-21} = addr{20-16}; 437 let Inst{15-0} = addr{15-0}; 438 let DecoderMethod = "DecodeMem"; 439} 440 441// Memory Load/Store 442class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 443 Operand MemOpnd, ComplexPattern Addr> : 444 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 445 [(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI> { 446 let DecoderMethod = "DecodeMem"; 447 let canFoldAsLoad = 1; 448 let mayLoad = 1; 449} 450 451class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 452 Operand MemOpnd, ComplexPattern Addr> : 453 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 454 [(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI> { 455 let DecoderMethod = "DecodeMem"; 456 let mayStore = 1; 457} 458 459multiclass LoadM<string opstr, RegisterClass RC, 460 SDPatternOperator OpNode = null_frag, 461 ComplexPattern Addr = addr> { 462 def NAME : Load<opstr, OpNode, RC, mem, Addr>, Requires<[NotN64, HasStdEnc]>; 463 def _P8 : Load<opstr, OpNode, RC, mem64, Addr>, 464 Requires<[IsN64, HasStdEnc]> { 465 let DecoderNamespace = "Mips64"; 466 let isCodeGenOnly = 1; 467 } 468} 469 470multiclass StoreM<string opstr, RegisterClass RC, 471 SDPatternOperator OpNode = null_frag, 472 ComplexPattern Addr = addr> { 473 def NAME : Store<opstr, OpNode, RC, mem, Addr>, Requires<[NotN64, HasStdEnc]>; 474 def _P8 : Store<opstr, OpNode, RC, mem64, Addr>, 475 Requires<[IsN64, HasStdEnc]> { 476 let DecoderNamespace = "Mips64"; 477 let isCodeGenOnly = 1; 478 } 479} 480 481// Load/Store Left/Right 482let canFoldAsLoad = 1 in 483class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 484 Operand MemOpnd> : 485 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 486 !strconcat(opstr, "\t$rt, $addr"), 487 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 488 let DecoderMethod = "DecodeMem"; 489 string Constraints = "$src = $rt"; 490} 491 492class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 493 Operand MemOpnd>: 494 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 495 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 496 let DecoderMethod = "DecodeMem"; 497} 498 499multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 500 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 501 Requires<[NotN64, HasStdEnc]>; 502 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 503 Requires<[IsN64, HasStdEnc]> { 504 let DecoderNamespace = "Mips64"; 505 let isCodeGenOnly = 1; 506 } 507} 508 509multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 510 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 511 Requires<[NotN64, HasStdEnc]>; 512 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 513 Requires<[IsN64, HasStdEnc]> { 514 let DecoderNamespace = "Mips64"; 515 let isCodeGenOnly = 1; 516 } 517} 518 519// Conditional Branch 520class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 521 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 522 !strconcat(opstr, "\t$rs, $rt, $offset"), 523 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 524 FrmI> { 525 let isBranch = 1; 526 let isTerminator = 1; 527 let hasDelaySlot = 1; 528 let Defs = [AT]; 529} 530 531class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 532 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 533 !strconcat(opstr, "\t$rs, $offset"), 534 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 535 let isBranch = 1; 536 let isTerminator = 1; 537 let hasDelaySlot = 1; 538 let Defs = [AT]; 539} 540 541// SetCC 542class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 543 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 544 !strconcat(opstr, "\t$rd, $rs, $rt"), 545 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 546 547class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 548 RegisterClass RC>: 549 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 550 !strconcat(opstr, "\t$rt, $rs, $imm16"), 551 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 552 IIAlu, FrmI>; 553 554// Jump 555class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 556 SDPatternOperator targetoperator> : 557 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 558 [(operator targetoperator:$target)], IIBranch, FrmJ> { 559 let isTerminator=1; 560 let isBarrier=1; 561 let hasDelaySlot = 1; 562 let DecoderMethod = "DecodeJumpTarget"; 563 let Defs = [AT]; 564} 565 566// Unconditional branch 567class UncondBranch<string opstr> : 568 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 569 [(br bb:$offset)], IIBranch, FrmI> { 570 let isBranch = 1; 571 let isTerminator = 1; 572 let isBarrier = 1; 573 let hasDelaySlot = 1; 574 let Predicates = [RelocPIC, HasStdEnc]; 575 let Defs = [AT]; 576} 577 578// Base class for indirect branch and return instruction classes. 579let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 580class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 581 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 582 583// Indirect branch 584class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 585 let isBranch = 1; 586 let isIndirectBranch = 1; 587} 588 589// Return instruction 590class RetBase<RegisterClass RC>: JumpFR<RC> { 591 let isReturn = 1; 592 let isCodeGenOnly = 1; 593 let hasCtrlDep = 1; 594 let hasExtraSrcRegAllocReq = 1; 595} 596 597// Jump and Link (Call) 598let isCall=1, hasDelaySlot=1, Defs = [RA] in { 599 class JumpLink<string opstr> : 600 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 601 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 602 let DecoderMethod = "DecodeJumpTarget"; 603 } 604 605 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, 606 Register RetReg>: 607 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, 608 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; 609 610 class JumpLinkReg<string opstr, RegisterClass RC>: 611 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 612 [], IIBranch, FrmR>; 613 614 class BGEZAL_FT<string opstr, RegisterOperand RO> : 615 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 616 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 617 618} 619 620class BAL_FT : 621 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 622 let isBranch = 1; 623 let isTerminator = 1; 624 let isBarrier = 1; 625 let hasDelaySlot = 1; 626 let Defs = [RA]; 627} 628 629// Sync 630let hasSideEffects = 1 in 631class SYNC_FT : 632 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 633 NoItinerary, FrmOther>; 634 635// Mul, Div 636class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 637 list<Register> DefRegs> : 638 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 639 itin, FrmR> { 640 let isCommutable = 1; 641 let Defs = DefRegs; 642 let neverHasSideEffects = 1; 643} 644 645// Pseudo multiply/divide instruction with explicit accumulator register 646// operands. 647class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 648 SDPatternOperator OpNode, InstrItinClass Itin, 649 bit IsComm = 1, bit HasSideEffects = 0> : 650 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 651 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 652 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 653 let isCommutable = IsComm; 654 let hasSideEffects = HasSideEffects; 655} 656 657// Pseudo multiply add/sub instruction with explicit accumulator register 658// operands. 659class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 660 : PseudoSE<(outs ACRegs:$ac), 661 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin), 662 [(set ACRegs:$ac, 663 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))], 664 IIImul>, 665 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> { 666 string Constraints = "$acin = $ac"; 667} 668 669class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 670 list<Register> DefRegs> : 671 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 672 [], itin, FrmR> { 673 let Defs = DefRegs; 674} 675 676// Move from Hi/Lo 677class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 678 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 679 let Uses = UseRegs; 680 let neverHasSideEffects = 1; 681} 682 683class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 684 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 685 let Defs = DefRegs; 686 let neverHasSideEffects = 1; 687} 688 689class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 690 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 691 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 692 let isCodeGenOnly = 1; 693 let DecoderMethod = "DecodeMem"; 694} 695 696// Count Leading Ones/Zeros in Word 697class CountLeading0<string opstr, RegisterOperand RO>: 698 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 699 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 700 Requires<[HasBitCount, HasStdEnc]>; 701 702class CountLeading1<string opstr, RegisterOperand RO>: 703 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 704 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 705 Requires<[HasBitCount, HasStdEnc]>; 706 707 708// Sign Extend in Register. 709class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 710 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 711 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 712 let Predicates = [HasSEInReg, HasStdEnc]; 713} 714 715// Subword Swap 716class SubwordSwap<string opstr, RegisterOperand RO>: 717 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 718 NoItinerary, FrmR> { 719 let Predicates = [HasSwap, HasStdEnc]; 720 let neverHasSideEffects = 1; 721} 722 723// Read Hardware 724class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 725 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 726 IIAlu, FrmR>; 727 728// Ext and Ins 729class ExtBase<string opstr, RegisterOperand RO>: 730 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 731 !strconcat(opstr, " $rt, $rs, $pos, $size"), 732 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 733 FrmR> { 734 let Predicates = [HasMips32r2, HasStdEnc]; 735} 736 737class InsBase<string opstr, RegisterOperand RO>: 738 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 739 !strconcat(opstr, " $rt, $rs, $pos, $size"), 740 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 741 NoItinerary, FrmR> { 742 let Predicates = [HasMips32r2, HasStdEnc]; 743 let Constraints = "$src = $rt"; 744} 745 746// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 747class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 748 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 749 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 750 751multiclass Atomic2Ops32<PatFrag Op> { 752 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 753 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 754 Requires<[IsN64, HasStdEnc]> { 755 let DecoderNamespace = "Mips64"; 756 } 757} 758 759// Atomic Compare & Swap. 760class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 761 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 762 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 763 764multiclass AtomicCmpSwap32<PatFrag Op> { 765 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 766 Requires<[NotN64, HasStdEnc]>; 767 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 768 Requires<[IsN64, HasStdEnc]> { 769 let DecoderNamespace = "Mips64"; 770 } 771} 772 773class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 774 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 775 [], NoItinerary, FrmI> { 776 let DecoderMethod = "DecodeMem"; 777 let mayLoad = 1; 778} 779 780class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 781 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 782 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 783 let DecoderMethod = "DecodeMem"; 784 let mayStore = 1; 785 let Constraints = "$rt = $dst"; 786} 787 788class MFC3OP<dag outs, dag ins, string asmstr> : 789 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 790 791//===----------------------------------------------------------------------===// 792// Pseudo instructions 793//===----------------------------------------------------------------------===// 794 795// Return RA. 796let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 797def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 798 799let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 800def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 801 [(callseq_start timm:$amt)]>; 802def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 803 [(callseq_end timm:$amt1, timm:$amt2)]>; 804} 805 806let usesCustomInserter = 1 in { 807 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 808 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 809 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 810 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 811 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 812 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 813 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 814 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 815 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 816 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 817 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 818 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 819 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 820 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 821 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 822 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 823 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 824 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 825 826 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 827 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 828 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 829 830 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 831 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 832 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 833} 834 835/// Pseudo instructions for loading, storing and copying accumulator registers. 836let isPseudo = 1 in { 837 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>; 838 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>; 839} 840 841def COPY_AC64 : PseudoSE<(outs ACRegs:$dst), (ins ACRegs:$src), []>; 842 843//===----------------------------------------------------------------------===// 844// Instruction definition 845//===----------------------------------------------------------------------===// 846//===----------------------------------------------------------------------===// 847// MipsI Instructions 848//===----------------------------------------------------------------------===// 849 850/// Arithmetic Instructions (ALU Immediate) 851def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 852 ADDI_FM<0x9>, IsAsCheapAsAMove; 853def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 854def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 855def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 856def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 857 ADDI_FM<0xc>; 858def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 859 ADDI_FM<0xd>; 860def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 861 ADDI_FM<0xe>; 862def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 863 864/// Arithmetic Instructions (3-Operand, R-Type) 865def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>; 866def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 867def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 868def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 869def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 870def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 871def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 872def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 873def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 874def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 875def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 876 877/// Shift Instructions 878def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 879 SRA_FM<0, 0>; 880def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 881 SRA_FM<2, 0>; 882def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 883 SRA_FM<3, 0>; 884def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 885def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 886def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 887 888// Rotate Instructions 889let Predicates = [HasMips32r2, HasStdEnc] in { 890 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>, 891 SRA_FM<2, 1>; 892 def ROTRV : shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, SRLV_FM<6, 1>; 893} 894 895/// Load and Store Instructions 896/// aligned 897defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>; 898defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, LW_FM<0x24>; 899defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, LW_FM<0x21>; 900defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>; 901defm LW : LoadM<"lw", CPURegs, load, addrDefault>, LW_FM<0x23>; 902defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>; 903defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>; 904defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>; 905 906/// load/store left/right 907defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 908defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 909defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 910defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 911 912def SYNC : SYNC_FT, SYNC_FM; 913 914/// Load-linked, Store-conditional 915let Predicates = [NotN64, HasStdEnc] in { 916 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 917 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 918} 919 920let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 921 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 922 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 923} 924 925/// Jump and Branch Instructions 926def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 927 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 928def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 929def B : UncondBranch<"b">, B_FM; 930def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 931def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 932def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 933def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 934def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 935def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 936 937def BAL_BR: BAL_FT, BAL_FM; 938 939def JAL : JumpLink<"jal">, FJ<3>; 940def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 941def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; 942def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 943def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 944def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 945def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 946 947def RET : RetBase<CPURegs>, MTLO_FM<8>; 948 949// Exception handling related node and instructions. 950// The conversion sequence is: 951// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 952// MIPSeh_return -> (stack change + indirect branch) 953// 954// MIPSeh_return takes the place of regular return instruction 955// but takes two arguments (V1, V0) which are used for storing 956// the offset and return address respectively. 957def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 958 959def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 960 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 961 962let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 963 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst), 964 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>; 965 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff, 966 CPU64Regs:$dst), 967 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>; 968} 969 970/// Multiply and Divide Instructions. 971def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>; 972def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>; 973def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>; 974def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>; 975def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>; 976def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>; 977def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv, 0>; 978def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv, 979 0>; 980 981def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 982def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 983def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 984def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 985 986/// Sign Ext In Register Instructions. 987def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 988def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 989 990/// Count Leading 991def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 992def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 993 994/// Word Swap Bytes Within Halfwords 995def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 996 997/// No operation. 998def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 999 1000// FrameIndexes are legalized when they are operands from load/store 1001// instructions. The same not happens for stack address copies, so an 1002// add op with mem ComplexPattern is used and the stack address copy 1003// can be matched. It's similar to Sparc LEA_ADDRi 1004def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 1005 1006// MADD*/MSUB* 1007def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1008def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1009def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>; 1010def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>; 1011def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1012def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1013def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1014def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1015 1016def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 1017 1018def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 1019def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 1020 1021/// Move Control Registers From/To CPU Registers 1022def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1023 (ins CPURegsOpnd:$rd, uimm16:$sel), 1024 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 1025 1026def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1027 (ins CPURegsOpnd:$rt), 1028 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 1029 1030def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1031 (ins CPURegsOpnd:$rd, uimm16:$sel), 1032 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 1033 1034def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1035 (ins CPURegsOpnd:$rt), 1036 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 1037 1038//===----------------------------------------------------------------------===// 1039// Instruction aliases 1040//===----------------------------------------------------------------------===// 1041def : InstAlias<"move $dst, $src", 1042 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1043 Requires<[NotMips64]>; 1044def : InstAlias<"move $dst, $src", 1045 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1046 Requires<[NotMips64]>; 1047def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; 1048def : InstAlias<"addu $rs, $rt, $imm", 1049 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1050def : InstAlias<"add $rs, $rt, $imm", 1051 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1052def : InstAlias<"and $rs, $rt, $imm", 1053 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1054def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, 1055 Requires<[NotMips64]>; 1056def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; 1057def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>; 1058def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>, 1059 Requires<[NotMips64]>; 1060def : InstAlias<"not $rt, $rs", 1061 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; 1062def : InstAlias<"neg $rt, $rs", 1063 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1064def : InstAlias<"negu $rt, $rs", 1065 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1066def : InstAlias<"slt $rs, $rt, $imm", 1067 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; 1068def : InstAlias<"xor $rs, $rt, $imm", 1069 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, 1070 Requires<[NotMips64]>; 1071def : InstAlias<"or $rs, $rt, $imm", 1072 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>, 1073 Requires<[NotMips64]>; 1074def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1075def : InstAlias<"mfc0 $rt, $rd", 1076 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1077def : InstAlias<"mtc0 $rt, $rd", 1078 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1079def : InstAlias<"mfc2 $rt, $rd", 1080 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1081def : InstAlias<"mtc2 $rt, $rd", 1082 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1083 1084//===----------------------------------------------------------------------===// 1085// Assembler Pseudo Instructions 1086//===----------------------------------------------------------------------===// 1087 1088class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1089 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1090 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1091def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 1092 1093class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1094 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1095 !strconcat(instr_asm, "\t$rt, $addr")> ; 1096def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 1097 1098class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1099 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1100 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1101def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 1102 1103 1104 1105//===----------------------------------------------------------------------===// 1106// Arbitrary patterns that map to one or more instructions 1107//===----------------------------------------------------------------------===// 1108 1109// Load/store pattern templates. 1110class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1111 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1112 1113class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1114 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1115 1116// Small immediates 1117def : MipsPat<(i32 immSExt16:$in), 1118 (ADDiu ZERO, imm:$in)>; 1119def : MipsPat<(i32 immZExt16:$in), 1120 (ORi ZERO, imm:$in)>; 1121def : MipsPat<(i32 immLow16Zero:$in), 1122 (LUi (HI16 imm:$in))>; 1123 1124// Arbitrary immediates 1125def : MipsPat<(i32 imm:$imm), 1126 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1127 1128// Carry MipsPatterns 1129def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1130 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1131def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1132 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1133def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1134 (ADDiu CPURegs:$src, imm:$imm)>; 1135 1136// Call 1137def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1138 (JAL tglobaladdr:$dst)>; 1139def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1140 (JAL texternalsym:$dst)>; 1141//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1142// (JALR CPURegs:$dst)>; 1143 1144// Tail call 1145def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1146 (TAILCALL tglobaladdr:$dst)>; 1147def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1148 (TAILCALL texternalsym:$dst)>; 1149// hi/lo relocs 1150def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1151def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1152def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1153def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1154def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1155def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1156 1157def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1158def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1159def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1160def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1161def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1162def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1163 1164def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1165 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1166def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1167 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1168def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1169 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1170def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1171 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1172def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1173 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1174 1175// gp_rel relocs 1176def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1177 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1178def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1179 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1180 1181// wrapper_pic 1182class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1183 MipsPat<(MipsWrapper RC:$gp, node:$in), 1184 (ADDiuOp RC:$gp, node:$in)>; 1185 1186def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1187def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1188def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1189def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1190def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1191def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1192 1193// Mips does not have "not", so we expand our way 1194def : MipsPat<(not CPURegs:$in), 1195 (NOR CPURegsOpnd:$in, ZERO)>; 1196 1197// extended loads 1198let Predicates = [NotN64, HasStdEnc] in { 1199 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1200 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1201 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1202} 1203let Predicates = [IsN64, HasStdEnc] in { 1204 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1205 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1206 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1207} 1208 1209// peepholes 1210let Predicates = [NotN64, HasStdEnc] in { 1211 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1212} 1213let Predicates = [IsN64, HasStdEnc] in { 1214 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1215} 1216 1217// brcond patterns 1218multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1219 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1220 Instruction SLTiuOp, Register ZEROReg> { 1221def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1222 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1223def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1224 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1225 1226def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1227 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1228def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1229 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1230def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1231 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1232def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1233 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1234 1235def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1236 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1237def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1238 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1239 1240def : MipsPat<(brcond RC:$cond, bb:$dst), 1241 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1242} 1243 1244defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1245 1246// setcc patterns 1247multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1248 Instruction SLTuOp, Register ZEROReg> { 1249 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1250 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1251 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1252 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1253} 1254 1255multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1256 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1257 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1258 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1259 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1260} 1261 1262multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1263 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1264 (SLTOp RC:$rhs, RC:$lhs)>; 1265 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1266 (SLTuOp RC:$rhs, RC:$lhs)>; 1267} 1268 1269multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1270 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1271 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1272 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1273 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1274} 1275 1276multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1277 Instruction SLTiuOp> { 1278 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1279 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1280 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1281 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1282} 1283 1284defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1285defm : SetlePats<CPURegs, SLT, SLTu>; 1286defm : SetgtPats<CPURegs, SLT, SLTu>; 1287defm : SetgePats<CPURegs, SLT, SLTu>; 1288defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1289 1290// bswap pattern 1291def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1292 1293// mflo/hi patterns. 1294def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)), 1295 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>; 1296 1297// Load halfword/word patterns. 1298let AddedComplexity = 40 in { 1299 let Predicates = [NotN64, HasStdEnc] in { 1300 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1301 def : LoadRegImmPat<LH, i32, sextloadi16>; 1302 def : LoadRegImmPat<LW, i32, load>; 1303 } 1304 let Predicates = [IsN64, HasStdEnc] in { 1305 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>; 1306 def : LoadRegImmPat<LH_P8, i32, sextloadi16>; 1307 def : LoadRegImmPat<LW_P8, i32, load>; 1308 } 1309} 1310 1311//===----------------------------------------------------------------------===// 1312// Floating Point Support 1313//===----------------------------------------------------------------------===// 1314 1315include "MipsInstrFPU.td" 1316include "Mips64InstrInfo.td" 1317include "MipsCondMov.td" 1318 1319// 1320// Mips16 1321 1322include "Mips16InstrFormats.td" 1323include "Mips16InstrInfo.td" 1324 1325// DSP 1326include "MipsDSPInstrFormats.td" 1327include "MipsDSPInstrInfo.td" 1328 1329