MipsInstrInfo.td revision de3322746280b957d552cc5e69e121b38c07406c
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, 37 SDTCisSameAs<0, 1>]>; 38def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 39 40def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 42def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 44 SDTCisSameAs<0, 4>]>; 45 46def SDTMipsLoadLR : SDTypeProfile<1, 2, 47 [SDTCisInt<0>, SDTCisPtrTy<1>, 48 SDTCisSameAs<0, 2>]>; 49 50// Call 51def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 53 SDNPVariadic]>; 54 55// Hi and Lo nodes are used to handle global addresses. Used on 56// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 57// static model. (nothing to do with Mips Registers Hi and Lo) 58def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 59def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 60def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 61 62// TlsGd node is used to handle General Dynamic TLS 63def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 64 65// TprelHi and TprelLo nodes are used to handle Local Exec TLS 66def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 67def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 68 69// Thread pointer 70def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 71 72// Return 73def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 74 75// These are target-independent nodes, but have target-specific formats. 76def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 77 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 78def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 79 [SDNPHasChain, SDNPSideEffect, 80 SDNPOptInGlue, SDNPOutGlue]>; 81 82// MAdd*/MSub* nodes 83def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 84 [SDNPOptInGlue, SDNPOutGlue]>; 85def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91 92// DivRem(u) nodes 93def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 94 [SDNPOutGlue]>; 95def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97 98// Target constant nodes that are not part of any isel patterns and remain 99// unchanged can cause instructions with illegal operands to be emitted. 100// Wrapper node patterns give the instruction selector a chance to replace 101// target constant nodes that would otherwise remain unchanged with ADDiu 102// nodes. Without these wrapper node patterns, the following conditional move 103// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 104// compiled: 105// movn %got(d)($gp), %got(c)($gp), $4 106// This instruction is illegal since movn can take only register operands. 107 108def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 109 110// Pointer to dynamically allocated stack area. 111def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc, 112 [SDNPHasChain, SDNPInGlue]>; 113 114def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 115 116def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 117def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 118 119def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 122 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 123def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 126 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 127def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 131def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 135 136//===----------------------------------------------------------------------===// 137// Mips Instruction Predicate Definitions. 138//===----------------------------------------------------------------------===// 139def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 140 AssemblerPredicate<"FeatureSEInReg">; 141def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 142 AssemblerPredicate<"FeatureBitCount">; 143def HasSwap : Predicate<"Subtarget.hasSwap()">, 144 AssemblerPredicate<"FeatureSwap">; 145def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 146 AssemblerPredicate<"FeatureCondMov">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">, 154 AssemblerPredicate<"FeatureMips32r2,FeatureMips64">; 155def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 156 AssemblerPredicate<"!FeatureMips64">; 157def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 158 AssemblerPredicate<"FeatureMips64r2">; 159def IsN64 : Predicate<"Subtarget.isABI_N64()">, 160 AssemblerPredicate<"FeatureN64">; 161def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 162 AssemblerPredicate<"!FeatureN64">; 163def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 164 AssemblerPredicate<"FeatureMips16">; 165def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 166 AssemblerPredicate<"FeatureMips32">; 167def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 168 AssemblerPredicate<"FeatureMips32">; 169def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 170 AssemblerPredicate<"FeatureMips32">; 171def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">, 172 AssemblerPredicate<"!FeatureMips16">; 173 174class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 175 let Predicates = [HasStandardEncoding]; 176} 177 178//===----------------------------------------------------------------------===// 179// Instruction format superclass 180//===----------------------------------------------------------------------===// 181 182include "MipsInstrFormats.td" 183 184//===----------------------------------------------------------------------===// 185// Mips Operand, Complex Patterns and Transformations Definitions. 186//===----------------------------------------------------------------------===// 187 188// Instruction operand types 189def jmptarget : Operand<OtherVT> { 190 let EncoderMethod = "getJumpTargetOpValue"; 191} 192def brtarget : Operand<OtherVT> { 193 let EncoderMethod = "getBranchTargetOpValue"; 194 let OperandType = "OPERAND_PCREL"; 195 let DecoderMethod = "DecodeBranchTarget"; 196} 197def calltarget : Operand<iPTR> { 198 let EncoderMethod = "getJumpTargetOpValue"; 199} 200def calltarget64: Operand<i64>; 201def simm16 : Operand<i32> { 202 let DecoderMethod= "DecodeSimm16"; 203} 204def simm16_64 : Operand<i64>; 205def shamt : Operand<i32>; 206 207// Unsigned Operand 208def uimm16 : Operand<i32> { 209 let PrintMethod = "printUnsignedImm"; 210} 211 212def MipsMemAsmOperand : AsmOperandClass { 213 let Name = "Mem"; 214 let ParserMethod = "parseMemOperand"; 215} 216 217// Address operand 218def mem : Operand<i32> { 219 let PrintMethod = "printMemOperand"; 220 let MIOperandInfo = (ops CPURegs, simm16); 221 let EncoderMethod = "getMemEncoding"; 222 let ParserMatchClass = MipsMemAsmOperand; 223} 224 225def mem64 : Operand<i64> { 226 let PrintMethod = "printMemOperand"; 227 let MIOperandInfo = (ops CPU64Regs, simm16_64); 228 let EncoderMethod = "getMemEncoding"; 229 let ParserMatchClass = MipsMemAsmOperand; 230} 231 232def mem_ea : Operand<i32> { 233 let PrintMethod = "printMemOperandEA"; 234 let MIOperandInfo = (ops CPURegs, simm16); 235 let EncoderMethod = "getMemEncoding"; 236} 237 238def mem_ea_64 : Operand<i64> { 239 let PrintMethod = "printMemOperandEA"; 240 let MIOperandInfo = (ops CPU64Regs, simm16_64); 241 let EncoderMethod = "getMemEncoding"; 242} 243 244// size operand of ext instruction 245def size_ext : Operand<i32> { 246 let EncoderMethod = "getSizeExtEncoding"; 247 let DecoderMethod = "DecodeExtSize"; 248} 249 250// size operand of ins instruction 251def size_ins : Operand<i32> { 252 let EncoderMethod = "getSizeInsEncoding"; 253 let DecoderMethod = "DecodeInsSize"; 254} 255 256// Transformation Function - get the lower 16 bits. 257def LO16 : SDNodeXForm<imm, [{ 258 return getImm(N, N->getZExtValue() & 0xFFFF); 259}]>; 260 261// Transformation Function - get the higher 16 bits. 262def HI16 : SDNodeXForm<imm, [{ 263 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 264}]>; 265 266// Node immediate fits as 16-bit sign extended on target immediate. 267// e.g. addi, andi 268def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 269 270// Node immediate fits as 16-bit zero extended on target immediate. 271// The LO16 param means that only the lower 16 bits of the node 272// immediate are caught. 273// e.g. addiu, sltiu 274def immZExt16 : PatLeaf<(imm), [{ 275 if (N->getValueType(0) == MVT::i32) 276 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 277 else 278 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 279}], LO16>; 280 281// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 282def immLow16Zero : PatLeaf<(imm), [{ 283 int64_t Val = N->getSExtValue(); 284 return isInt<32>(Val) && !(Val & 0xffff); 285}]>; 286 287// shamt field must fit in 5 bits. 288def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 289 290// Mips Address Mode! SDNode frameindex could possibily be a match 291// since load and store instructions from stack used it. 292def addr : 293 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 294 295//===----------------------------------------------------------------------===// 296// Instructions specific format 297//===----------------------------------------------------------------------===// 298 299/// Move Control Registers From/To CPU Registers 300def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt), 301 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">; 302def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 303 304def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel), 305 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">; 306def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 307 308def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt), 309 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">; 310def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 311 312def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel), 313 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">; 314def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 315 316// Arithmetic and logical instructions with 3 register operands. 317class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode, 318 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 319 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 320 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 321 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> { 322 let shamt = 0; 323 let isCommutable = isComm; 324 let isReMaterializable = 1; 325} 326 327class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm, 328 InstrItinClass itin, RegisterClass RC, bit isComm = 0>: 329 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 330 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> { 331 let shamt = 0; 332 let isCommutable = isComm; 333} 334 335// Arithmetic and logical instructions with 2 register operands. 336class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode, 337 Operand Od, PatLeaf imm_type, RegisterClass RC> : 338 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 339 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 340 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> { 341 let isReMaterializable = 1; 342} 343 344class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode, 345 Operand Od, PatLeaf imm_type, RegisterClass RC> : 346 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 347 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>; 348 349// Arithmetic Multiply ADD/SUB 350let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in 351class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> : 352 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), 353 !strconcat(instr_asm, "\t$rs, $rt"), 354 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { 355 let rd = 0; 356 let shamt = 0; 357 let isCommutable = isComm; 358} 359 360// Logical 361class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>: 362 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), 363 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 364 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> { 365 let shamt = 0; 366 let isCommutable = 1; 367} 368 369// Shifts 370class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm, 371 SDNode OpNode, PatFrag PF, Operand ImmOpnd, 372 RegisterClass RC>: 373 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 374 !strconcat(instr_asm, "\t$rd, $rt, $shamt"), 375 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> { 376 let rs = isRotate; 377} 378 379// 32-bit shift instructions. 380class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm, 381 SDNode OpNode>: 382 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>; 383 384class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm, 385 SDNode OpNode, RegisterClass RC>: 386 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt), 387 !strconcat(instr_asm, "\t$rd, $rt, $rs"), 388 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> { 389 let shamt = isRotate; 390} 391 392// Load Upper Imediate 393class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>: 394 FI<op, (outs RC:$rt), (ins Imm:$imm16), 395 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> { 396 let rs = 0; 397 let neverHasSideEffects = 1; 398 let isReMaterializable = 1; 399} 400 401class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 402 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 403 bits<21> addr; 404 let Inst{25-21} = addr{20-16}; 405 let Inst{15-0} = addr{15-0}; 406 let DecoderMethod = "DecodeMem"; 407} 408 409// Memory Load/Store 410let canFoldAsLoad = 1 in 411class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 412 Operand MemOpnd, bit Pseudo>: 413 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), 414 !strconcat(instr_asm, "\t$rt, $addr"), 415 [(set RC:$rt, (OpNode addr:$addr))], IILoad> { 416 let isPseudo = Pseudo; 417} 418 419class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, 420 Operand MemOpnd, bit Pseudo>: 421 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 422 !strconcat(instr_asm, "\t$rt, $addr"), 423 [(OpNode RC:$rt, addr:$addr)], IIStore> { 424 let isPseudo = Pseudo; 425} 426 427// 32-bit load. 428multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode, 429 bit Pseudo = 0> { 430 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 431 Requires<[NotN64, HasStandardEncoding]>; 432 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 433 Requires<[IsN64, HasStandardEncoding]> { 434 let DecoderNamespace = "Mips64"; 435 let isCodeGenOnly = 1; 436 } 437} 438 439// 64-bit load. 440multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode, 441 bit Pseudo = 0> { 442 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 443 Requires<[NotN64, HasStandardEncoding]>; 444 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 445 Requires<[IsN64, HasStandardEncoding]> { 446 let DecoderNamespace = "Mips64"; 447 let isCodeGenOnly = 1; 448 } 449} 450 451// 32-bit store. 452multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode, 453 bit Pseudo = 0> { 454 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>, 455 Requires<[NotN64, HasStandardEncoding]>; 456 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>, 457 Requires<[IsN64, HasStandardEncoding]> { 458 let DecoderNamespace = "Mips64"; 459 let isCodeGenOnly = 1; 460 } 461} 462 463// 64-bit store. 464multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode, 465 bit Pseudo = 0> { 466 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>, 467 Requires<[NotN64, HasStandardEncoding]>; 468 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>, 469 Requires<[IsN64, HasStandardEncoding]> { 470 let DecoderNamespace = "Mips64"; 471 let isCodeGenOnly = 1; 472 } 473} 474 475// Load/Store Left/Right 476let canFoldAsLoad = 1 in 477class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 478 RegisterClass RC, Operand MemOpnd> : 479 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 480 !strconcat(instr_asm, "\t$rt, $addr"), 481 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> { 482 string Constraints = "$src = $rt"; 483} 484 485class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode, 486 RegisterClass RC, Operand MemOpnd>: 487 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), 488 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)], 489 IIStore>; 490 491// 32-bit load left/right. 492multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 493 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 494 Requires<[NotN64, HasStandardEncoding]>; 495 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 496 Requires<[IsN64, HasStandardEncoding]> { 497 let DecoderNamespace = "Mips64"; 498 let isCodeGenOnly = 1; 499 } 500} 501 502// 64-bit load left/right. 503multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 504 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 505 Requires<[NotN64, HasStandardEncoding]>; 506 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 507 Requires<[IsN64, HasStandardEncoding]> { 508 let DecoderNamespace = "Mips64"; 509 let isCodeGenOnly = 1; 510 } 511} 512 513// 32-bit store left/right. 514multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> { 515 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>, 516 Requires<[NotN64, HasStandardEncoding]>; 517 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>, 518 Requires<[IsN64, HasStandardEncoding]> { 519 let DecoderNamespace = "Mips64"; 520 let isCodeGenOnly = 1; 521 } 522} 523 524// 64-bit store left/right. 525multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> { 526 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>, 527 Requires<[NotN64, HasStandardEncoding]>; 528 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>, 529 Requires<[IsN64, HasStandardEncoding]> { 530 let DecoderNamespace = "Mips64"; 531 let isCodeGenOnly = 1; 532 } 533} 534 535// Conditional Branch 536class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>: 537 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16), 538 !strconcat(instr_asm, "\t$rs, $rt, $imm16"), 539 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { 540 let isBranch = 1; 541 let isTerminator = 1; 542 let hasDelaySlot = 1; 543 let Defs = [AT]; 544} 545 546class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op, 547 RegisterClass RC>: 548 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16), 549 !strconcat(instr_asm, "\t$rs, $imm16"), 550 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> { 551 let rt = _rt; 552 let isBranch = 1; 553 let isTerminator = 1; 554 let hasDelaySlot = 1; 555 let Defs = [AT]; 556} 557 558// SetCC 559class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op, 560 RegisterClass RC>: 561 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), 562 !strconcat(instr_asm, "\t$rd, $rs, $rt"), 563 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], 564 IIAlu> { 565 let shamt = 0; 566} 567 568class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, 569 PatLeaf imm_type, RegisterClass RC>: 570 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16), 571 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 572 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))], 573 IIAlu>; 574 575// Jump 576class JumpFJ<bits<6> op, string instr_asm>: 577 FJ<op, (outs), (ins jmptarget:$target), 578 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> { 579 let isBranch=1; 580 let isTerminator=1; 581 let isBarrier=1; 582 let hasDelaySlot = 1; 583 let Predicates = [RelocStatic, HasStandardEncoding]; 584 let DecoderMethod = "DecodeJumpTarget"; 585 let Defs = [AT]; 586} 587 588// Unconditional branch 589class UncondBranch<bits<6> op, string instr_asm>: 590 BranchBase<op, (outs), (ins brtarget:$imm16), 591 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> { 592 let rs = 0; 593 let rt = 0; 594 let isBranch = 1; 595 let isTerminator = 1; 596 let isBarrier = 1; 597 let hasDelaySlot = 1; 598 let Predicates = [RelocPIC, HasStandardEncoding]; 599 let Defs = [AT]; 600} 601 602// Base class for indirect branch and return instruction classes. 603let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 604class JumpFR<RegisterClass RC, list<dag> pattern>: 605 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", pattern, IIBranch> { 606 let rt = 0; 607 let rd = 0; 608 let shamt = 0; 609} 610 611// Indirect branch 612class IndirectBranch<RegisterClass RC>: JumpFR<RC, [(brind RC:$rs)]> { 613 let isBranch = 1; 614 let isIndirectBranch = 1; 615} 616 617// Return instruction 618class RetBase<RegisterClass RC>: JumpFR<RC, []> { 619 let isReturn = 1; 620 let isCodeGenOnly = 1; 621 let hasCtrlDep = 1; 622 let hasExtraSrcRegAllocReq = 1; 623} 624 625// Jump and Link (Call) 626let isCall=1, hasDelaySlot=1, Defs = [RA] in { 627 class JumpLink<bits<6> op, string instr_asm>: 628 FJ<op, (outs), (ins calltarget:$target), 629 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], 630 IIBranch> { 631 let DecoderMethod = "DecodeJumpTarget"; 632 } 633 634 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm, 635 RegisterClass RC>: 636 FR<op, func, (outs), (ins RC:$rs), 637 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> { 638 let rt = 0; 639 let rd = 31; 640 let shamt = 0; 641 } 642 643 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>: 644 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16), 645 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> { 646 let rt = _rt; 647 } 648} 649 650// Mul, Div 651class Mult<bits<6> func, string instr_asm, InstrItinClass itin, 652 RegisterClass RC, list<Register> DefRegs>: 653 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 654 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> { 655 let rd = 0; 656 let shamt = 0; 657 let isCommutable = 1; 658 let Defs = DefRegs; 659 let neverHasSideEffects = 1; 660} 661 662class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>: 663 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>; 664 665class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin, 666 RegisterClass RC, list<Register> DefRegs>: 667 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), 668 !strconcat(instr_asm, "\t$$zero, $rs, $rt"), 669 [(op RC:$rs, RC:$rt)], itin> { 670 let rd = 0; 671 let shamt = 0; 672 let Defs = DefRegs; 673} 674 675class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: 676 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>; 677 678// Move from Hi/Lo 679class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC, 680 list<Register> UseRegs>: 681 FR<0x00, func, (outs RC:$rd), (ins), 682 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> { 683 let rs = 0; 684 let rt = 0; 685 let shamt = 0; 686 let Uses = UseRegs; 687 let neverHasSideEffects = 1; 688} 689 690class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC, 691 list<Register> DefRegs>: 692 FR<0x00, func, (outs), (ins RC:$rs), 693 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> { 694 let rt = 0; 695 let rd = 0; 696 let shamt = 0; 697 let Defs = DefRegs; 698 let neverHasSideEffects = 1; 699} 700 701class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> : 702 FMem<opc, (outs RC:$rt), (ins Mem:$addr), 703 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> { 704 let isCodeGenOnly = 1; 705} 706 707// Count Leading Ones/Zeros in Word 708class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>: 709 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 710 !strconcat(instr_asm, "\t$rd, $rs"), 711 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>, 712 Requires<[HasBitCount, HasStandardEncoding]> { 713 let shamt = 0; 714 let rt = rd; 715} 716 717class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>: 718 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs), 719 !strconcat(instr_asm, "\t$rd, $rs"), 720 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>, 721 Requires<[HasBitCount, HasStandardEncoding]> { 722 let shamt = 0; 723 let rt = rd; 724} 725 726// Sign Extend in Register. 727class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt, 728 RegisterClass RC>: 729 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt), 730 !strconcat(instr_asm, "\t$rd, $rt"), 731 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> { 732 let rs = 0; 733 let shamt = sa; 734 let Predicates = [HasSEInReg, HasStandardEncoding]; 735} 736 737// Subword Swap 738class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>: 739 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt), 740 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> { 741 let rs = 0; 742 let shamt = sa; 743 let Predicates = [HasSwap, HasStandardEncoding]; 744 let neverHasSideEffects = 1; 745} 746 747// Read Hardware 748class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass> 749 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd), 750 "rdhwr\t$rt, $rd", [], IIAlu> { 751 let rs = 0; 752 let shamt = 0; 753} 754 755// Ext and Ins 756class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 757 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz), 758 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 759 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> { 760 bits<5> pos; 761 bits<5> sz; 762 let rd = sz; 763 let shamt = pos; 764 let Predicates = [HasMips32r2, HasStandardEncoding]; 765} 766 767class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>: 768 FR<0x1f, _funct, (outs RC:$rt), 769 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src), 770 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"), 771 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))], 772 NoItinerary> { 773 bits<5> pos; 774 bits<5> sz; 775 let rd = sz; 776 let shamt = pos; 777 let Predicates = [HasMips32r2, HasStandardEncoding]; 778 let Constraints = "$src = $rt"; 779} 780 781// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 782class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC, 783 RegisterClass PRC> : 784 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 785 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"), 786 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 787 788multiclass Atomic2Ops32<PatFrag Op, string Opstr> { 789 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, 790 Requires<[NotN64, HasStandardEncoding]>; 791 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, 792 Requires<[IsN64, HasStandardEncoding]> { 793 let DecoderNamespace = "Mips64"; 794 } 795} 796 797// Atomic Compare & Swap. 798class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC, 799 RegisterClass PRC> : 800 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 801 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"), 802 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 803 804multiclass AtomicCmpSwap32<PatFrag Op, string Width> { 805 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, 806 Requires<[NotN64, HasStandardEncoding]>; 807 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, 808 Requires<[IsN64, HasStandardEncoding]> { 809 let DecoderNamespace = "Mips64"; 810 } 811} 812 813class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 814 FMem<Opc, (outs RC:$rt), (ins Mem:$addr), 815 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> { 816 let mayLoad = 1; 817} 818 819class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> : 820 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr), 821 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> { 822 let mayStore = 1; 823 let Constraints = "$rt = $dst"; 824} 825 826//===----------------------------------------------------------------------===// 827// Pseudo instructions 828//===----------------------------------------------------------------------===// 829 830// Return RA. 831let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 832def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>; 833 834let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 835def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 836 "!ADJCALLSTACKDOWN $amt", 837 [(callseq_start timm:$amt)]>; 838def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 839 "!ADJCALLSTACKUP $amt1", 840 [(callseq_end timm:$amt1, timm:$amt2)]>; 841} 842 843// When handling PIC code the assembler needs .cpload and .cprestore 844// directives. If the real instructions corresponding these directives 845// are used, we have the same behavior, but get also a bunch of warnings 846// from the assembler. 847let neverHasSideEffects = 1 in 848def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp), 849 ".cprestore\t$loc", []>; 850 851let usesCustomInserter = 1 in { 852 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">; 853 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">; 854 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">; 855 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">; 856 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">; 857 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">; 858 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">; 859 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">; 860 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">; 861 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">; 862 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">; 863 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">; 864 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">; 865 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">; 866 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">; 867 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">; 868 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">; 869 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">; 870 871 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">; 872 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">; 873 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">; 874 875 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">; 876 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">; 877 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">; 878} 879 880//===----------------------------------------------------------------------===// 881// Instruction definition 882//===----------------------------------------------------------------------===// 883 884class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> : 885 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32), 886 !strconcat(instr_asm, "\t$rt, $imm32")> ; 887def LoadImm32Reg : LoadImm32<"li",shamt,CPURegs>; 888//===----------------------------------------------------------------------===// 889// MipsI Instructions 890//===----------------------------------------------------------------------===// 891 892/// Arithmetic Instructions (ALU Immediate) 893def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>; 894def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>; 895def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>; 896def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>; 897def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>; 898def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>; 899def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>; 900def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>; 901 902/// Arithmetic Instructions (3-Operand, R-Type) 903def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>; 904def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>; 905def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>; 906def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>; 907def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>; 908def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>; 909def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>; 910def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>; 911def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>; 912def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>; 913 914/// Shift Instructions 915def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>; 916def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>; 917def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>; 918def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>; 919def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>; 920def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>; 921 922// Rotate Instructions 923let Predicates = [HasMips32r2, HasStandardEncoding] in { 924 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>; 925 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>; 926} 927 928/// Load and Store Instructions 929/// aligned 930defm LB : LoadM32<0x20, "lb", sextloadi8>; 931defm LBu : LoadM32<0x24, "lbu", zextloadi8>; 932defm LH : LoadM32<0x21, "lh", sextloadi16>; 933defm LHu : LoadM32<0x25, "lhu", zextloadi16>; 934defm LW : LoadM32<0x23, "lw", load>; 935defm SB : StoreM32<0x28, "sb", truncstorei8>; 936defm SH : StoreM32<0x29, "sh", truncstorei16>; 937defm SW : StoreM32<0x2b, "sw", store>; 938 939/// load/store left/right 940defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>; 941defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>; 942defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>; 943defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>; 944 945let hasSideEffects = 1 in 946def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype", 947 [(MipsSync imm:$stype)], NoItinerary, FrmOther> 948{ 949 bits<5> stype; 950 let Opcode = 0; 951 let Inst{25-11} = 0; 952 let Inst{10-6} = stype; 953 let Inst{5-0} = 15; 954} 955 956/// Load-linked, Store-conditional 957def LL : LLBase<0x30, "ll", CPURegs, mem>, 958 Requires<[NotN64, HasStandardEncoding]>; 959def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, 960 Requires<[IsN64, HasStandardEncoding]> { 961 let DecoderNamespace = "Mips64"; 962} 963 964def SC : SCBase<0x38, "sc", CPURegs, mem>, 965 Requires<[NotN64, HasStandardEncoding]>; 966def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, 967 Requires<[IsN64, HasStandardEncoding]> { 968 let DecoderNamespace = "Mips64"; 969} 970 971/// Jump and Branch Instructions 972def J : JumpFJ<0x02, "j">; 973def JR : IndirectBranch<CPURegs>; 974def B : UncondBranch<0x04, "b">; 975def BEQ : CBranch<0x04, "beq", seteq, CPURegs>; 976def BNE : CBranch<0x05, "bne", setne, CPURegs>; 977def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>; 978def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>; 979def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>; 980def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>; 981 982let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1, 983 hasDelaySlot = 1, Defs = [RA] in 984def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>; 985 986def JAL : JumpLink<0x03, "jal">; 987def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>; 988def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>; 989def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>; 990 991def RET : RetBase<CPURegs>; 992 993/// Multiply and Divide Instructions. 994def MULT : Mult32<0x18, "mult", IIImul>; 995def MULTu : Mult32<0x19, "multu", IIImul>; 996def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>; 997def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>; 998 999def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>; 1000def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>; 1001def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>; 1002def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>; 1003 1004/// Sign Ext In Register Instructions. 1005def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>; 1006def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>; 1007 1008/// Count Leading 1009def CLZ : CountLeading0<0x20, "clz", CPURegs>; 1010def CLO : CountLeading1<0x21, "clo", CPURegs>; 1011 1012/// Word Swap Bytes Within Halfwords 1013def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>; 1014 1015/// No operation 1016let addr=0 in 1017 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>; 1018 1019// FrameIndexes are legalized when they are operands from load/store 1020// instructions. The same not happens for stack address copies, so an 1021// add op with mem ComplexPattern is used and the stack address copy 1022// can be matched. It's similar to Sparc LEA_ADDRi 1023def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1024 1025// DynAlloc node points to dynamically allocated stack space. 1026// $sp is added to the list of implicitly used registers to prevent dead code 1027// elimination from removing instructions that modify $sp. 1028let Uses = [SP] in 1029def DynAlloc : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>; 1030 1031// MADD*/MSUB* 1032def MADD : MArithR<0, "madd", MipsMAdd, 1>; 1033def MADDU : MArithR<1, "maddu", MipsMAddu, 1>; 1034def MSUB : MArithR<4, "msub", MipsMSub>; 1035def MSUBU : MArithR<5, "msubu", MipsMSubu>; 1036 1037// MUL is a assembly macro in the current used ISAs. In recent ISA's 1038// it is a real instruction. 1039def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>, 1040 Requires<[HasMips32, HasStandardEncoding]>; 1041 1042def RDHWR : ReadHardware<CPURegs, HWRegs>; 1043 1044def EXT : ExtBase<0, "ext", CPURegs>; 1045def INS : InsBase<4, "ins", CPURegs>; 1046 1047//===----------------------------------------------------------------------===// 1048// Instruction aliases 1049//===----------------------------------------------------------------------===// 1050def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>; 1051def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>; 1052def : InstAlias<"addu $rs,$rt,$imm", 1053 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1054def : InstAlias<"add $rs,$rt,$imm", 1055 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1056def : InstAlias<"and $rs,$rt,$imm", 1057 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1058def : InstAlias<"j $rs", (JR CPURegs:$rs)>; 1059def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>; 1060def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>; 1061def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>; 1062def : InstAlias<"slt $rs,$rt,$imm", 1063 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1064def : InstAlias<"xor $rs,$rt,$imm", 1065 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>; 1066 1067//===----------------------------------------------------------------------===// 1068// Arbitrary patterns that map to one or more instructions 1069//===----------------------------------------------------------------------===// 1070 1071// Small immediates 1072def : MipsPat<(i32 immSExt16:$in), 1073 (ADDiu ZERO, imm:$in)>; 1074def : MipsPat<(i32 immZExt16:$in), 1075 (ORi ZERO, imm:$in)>; 1076def : MipsPat<(i32 immLow16Zero:$in), 1077 (LUi (HI16 imm:$in))>; 1078 1079// Arbitrary immediates 1080def : MipsPat<(i32 imm:$imm), 1081 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1082 1083// Carry MipsPatterns 1084def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1085 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1086def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1087 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1088def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1089 (ADDiu CPURegs:$src, imm:$imm)>; 1090 1091// Call 1092def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1093 (JAL tglobaladdr:$dst)>; 1094def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1095 (JAL texternalsym:$dst)>; 1096//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1097// (JALR CPURegs:$dst)>; 1098 1099// hi/lo relocs 1100def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1101def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1102def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1103def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1104def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1105 1106def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1107def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1108def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1109def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1110def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1111 1112def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1113 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1114def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1115 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1116def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1117 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1118def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1119 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1120def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1121 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1122 1123// gp_rel relocs 1124def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1125 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1126def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1127 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1128 1129// wrapper_pic 1130class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1131 MipsPat<(MipsWrapper RC:$gp, node:$in), 1132 (ADDiuOp RC:$gp, node:$in)>; 1133 1134def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1135def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1136def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1137def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1138def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1139def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1140 1141// Mips does not have "not", so we expand our way 1142def : MipsPat<(not CPURegs:$in), 1143 (NOR CPURegs:$in, ZERO)>; 1144 1145// extended loads 1146let Predicates = [NotN64, HasStandardEncoding] in { 1147 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1148 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1149 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1150} 1151let Predicates = [IsN64, HasStandardEncoding] in { 1152 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1153 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1154 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1155} 1156 1157// peepholes 1158let Predicates = [NotN64, HasStandardEncoding] in { 1159 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1160} 1161let Predicates = [IsN64, HasStandardEncoding] in { 1162 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1163} 1164 1165// brcond patterns 1166multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1167 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1168 Instruction SLTiuOp, Register ZEROReg> { 1169def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1170 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1171def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1172 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1173 1174def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1175 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1176def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1177 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1178def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1179 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1180def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1181 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1182 1183def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1184 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1185def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1186 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1187 1188def : MipsPat<(brcond RC:$cond, bb:$dst), 1189 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1190} 1191 1192defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1193 1194// setcc patterns 1195multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1196 Instruction SLTuOp, Register ZEROReg> { 1197 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1198 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1199 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1200 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1201} 1202 1203multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1204 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1205 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1206 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1207 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1208} 1209 1210multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1211 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1212 (SLTOp RC:$rhs, RC:$lhs)>; 1213 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1214 (SLTuOp RC:$rhs, RC:$lhs)>; 1215} 1216 1217multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1218 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1219 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1220 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1221 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1222} 1223 1224multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1225 Instruction SLTiuOp> { 1226 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1227 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1228 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1229 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1230} 1231 1232defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1233defm : SetlePats<CPURegs, SLT, SLTu>; 1234defm : SetgtPats<CPURegs, SLT, SLTu>; 1235defm : SetgePats<CPURegs, SLT, SLTu>; 1236defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1237 1238// select MipsDynAlloc 1239def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>; 1240 1241// bswap pattern 1242def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1243 1244//===----------------------------------------------------------------------===// 1245// Floating Point Support 1246//===----------------------------------------------------------------------===// 1247 1248include "MipsInstrFPU.td" 1249include "Mips64InstrInfo.td" 1250include "MipsCondMov.td" 1251 1252// 1253// Mips16 1254 1255include "Mips16InstrFormats.td" 1256include "Mips16InstrInfo.td" 1257 1258// DSP 1259include "MipsDSPInstrFormats.td" 1260include "MipsDSPInstrInfo.td" 1261 1262