MipsInstrInfo.td revision e351865b65e92bea8ceeb32ad757d783d0ecea0f
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>, 27 SDTCisVT<2, i32>]>; 28def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 29 SDTCisVT<1, i32>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 36def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 37 38def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 39 40def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 41 42def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 44def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 46 SDTCisSameAs<0, 4>]>; 47 48def SDTMipsLoadLR : SDTypeProfile<1, 2, 49 [SDTCisInt<0>, SDTCisPtrTy<1>, 50 SDTCisSameAs<0, 2>]>; 51 52// Call 53def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 55 SDNPVariadic]>; 56 57// Tail call 58def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 60 61// Hi and Lo nodes are used to handle global addresses. Used on 62// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 63// static model. (nothing to do with Mips Registers Hi and Lo) 64def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 65def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 66def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 67 68// TlsGd node is used to handle General Dynamic TLS 69def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 70 71// TprelHi and TprelLo nodes are used to handle Local Exec TLS 72def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 73def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 74 75// Thread pointer 76def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 77 78// Return 79def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 81 82// These are target-independent nodes, but have target-specific formats. 83def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 85def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 86 [SDNPHasChain, SDNPSideEffect, 87 SDNPOptInGlue, SDNPOutGlue]>; 88 89// Node used to extract integer from LO/HI register. 90def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>; 91 92// Node used to insert 32-bit integers to LOHI register pair. 93def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>; 94 95// Mult nodes. 96def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 97def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 98 99// MAdd*/MSub* nodes 100def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 101def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 102def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 103def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 104 105// DivRem(u) nodes 106def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 107def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 108def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 111 [SDNPOutGlue]>; 112 113// Target constant nodes that are not part of any isel patterns and remain 114// unchanged can cause instructions with illegal operands to be emitted. 115// Wrapper node patterns give the instruction selector a chance to replace 116// target constant nodes that would otherwise remain unchanged with ADDiu 117// nodes. Without these wrapper node patterns, the following conditional move 118// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 119// compiled: 120// movn %got(d)($gp), %got(c)($gp), $4 121// This instruction is illegal since movn can take only register operands. 122 123def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 124 125def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 126 127def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 128def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 129 130def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 134def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 138def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 142def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 146 147//===----------------------------------------------------------------------===// 148// Mips Instruction Predicate Definitions. 149//===----------------------------------------------------------------------===// 150def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 151 AssemblerPredicate<"FeatureSEInReg">; 152def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 153 AssemblerPredicate<"FeatureBitCount">; 154def HasSwap : Predicate<"Subtarget.hasSwap()">, 155 AssemblerPredicate<"FeatureSwap">; 156def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 157 AssemblerPredicate<"FeatureCondMov">; 158def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 159 AssemblerPredicate<"FeatureFPIdx">; 160def HasMips32 : Predicate<"Subtarget.hasMips32()">, 161 AssemblerPredicate<"FeatureMips32">; 162def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 163 AssemblerPredicate<"FeatureMips32r2">; 164def HasMips64 : Predicate<"Subtarget.hasMips64()">, 165 AssemblerPredicate<"FeatureMips64">; 166def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 167 AssemblerPredicate<"!FeatureMips64">; 168def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 169 AssemblerPredicate<"FeatureMips64r2">; 170def IsN64 : Predicate<"Subtarget.isABI_N64()">, 171 AssemblerPredicate<"FeatureN64">; 172def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 173 AssemblerPredicate<"!FeatureN64">; 174def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 175 AssemblerPredicate<"FeatureMips16">; 176def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 177 AssemblerPredicate<"FeatureMips32">; 178def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 179 AssemblerPredicate<"FeatureMips32">; 180def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 181 AssemblerPredicate<"FeatureMips32">; 182def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 183 AssemblerPredicate<"!FeatureMips16">; 184def NotDSP : Predicate<"!Subtarget.hasDSP()">; 185 186class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 187 let Predicates = [HasStdEnc]; 188} 189 190class IsCommutable { 191 bit isCommutable = 1; 192} 193 194class IsBranch { 195 bit isBranch = 1; 196} 197 198class IsReturn { 199 bit isReturn = 1; 200} 201 202class IsCall { 203 bit isCall = 1; 204} 205 206class IsTailCall { 207 bit isCall = 1; 208 bit isTerminator = 1; 209 bit isReturn = 1; 210 bit isBarrier = 1; 211 bit hasExtraSrcRegAllocReq = 1; 212 bit isCodeGenOnly = 1; 213} 214 215class IsAsCheapAsAMove { 216 bit isAsCheapAsAMove = 1; 217} 218 219class NeverHasSideEffects { 220 bit neverHasSideEffects = 1; 221} 222 223//===----------------------------------------------------------------------===// 224// Instruction format superclass 225//===----------------------------------------------------------------------===// 226 227include "MipsInstrFormats.td" 228 229//===----------------------------------------------------------------------===// 230// Mips Operand, Complex Patterns and Transformations Definitions. 231//===----------------------------------------------------------------------===// 232 233// Instruction operand types 234def jmptarget : Operand<OtherVT> { 235 let EncoderMethod = "getJumpTargetOpValue"; 236} 237def brtarget : Operand<OtherVT> { 238 let EncoderMethod = "getBranchTargetOpValue"; 239 let OperandType = "OPERAND_PCREL"; 240 let DecoderMethod = "DecodeBranchTarget"; 241} 242def calltarget : Operand<iPTR> { 243 let EncoderMethod = "getJumpTargetOpValue"; 244} 245def calltarget64: Operand<i64>; 246def simm16 : Operand<i32> { 247 let DecoderMethod= "DecodeSimm16"; 248} 249 250def simm20 : Operand<i32> { 251} 252 253def simm16_64 : Operand<i64>; 254def shamt : Operand<i32>; 255 256// Unsigned Operand 257def uimm16 : Operand<i32> { 258 let PrintMethod = "printUnsignedImm"; 259} 260 261def MipsMemAsmOperand : AsmOperandClass { 262 let Name = "Mem"; 263 let ParserMethod = "parseMemOperand"; 264} 265 266// Address operand 267def mem : Operand<i32> { 268 let PrintMethod = "printMemOperand"; 269 let MIOperandInfo = (ops CPURegs, simm16); 270 let EncoderMethod = "getMemEncoding"; 271 let ParserMatchClass = MipsMemAsmOperand; 272 let OperandType = "OPERAND_MEMORY"; 273} 274 275def mem64 : Operand<i64> { 276 let PrintMethod = "printMemOperand"; 277 let MIOperandInfo = (ops CPU64Regs, simm16_64); 278 let EncoderMethod = "getMemEncoding"; 279 let ParserMatchClass = MipsMemAsmOperand; 280 let OperandType = "OPERAND_MEMORY"; 281} 282 283def mem_ea : Operand<i32> { 284 let PrintMethod = "printMemOperandEA"; 285 let MIOperandInfo = (ops CPURegs, simm16); 286 let EncoderMethod = "getMemEncoding"; 287 let OperandType = "OPERAND_MEMORY"; 288} 289 290def mem_ea_64 : Operand<i64> { 291 let PrintMethod = "printMemOperandEA"; 292 let MIOperandInfo = (ops CPU64Regs, simm16_64); 293 let EncoderMethod = "getMemEncoding"; 294 let OperandType = "OPERAND_MEMORY"; 295} 296 297// size operand of ext instruction 298def size_ext : Operand<i32> { 299 let EncoderMethod = "getSizeExtEncoding"; 300 let DecoderMethod = "DecodeExtSize"; 301} 302 303// size operand of ins instruction 304def size_ins : Operand<i32> { 305 let EncoderMethod = "getSizeInsEncoding"; 306 let DecoderMethod = "DecodeInsSize"; 307} 308 309// Transformation Function - get the lower 16 bits. 310def LO16 : SDNodeXForm<imm, [{ 311 return getImm(N, N->getZExtValue() & 0xFFFF); 312}]>; 313 314// Transformation Function - get the higher 16 bits. 315def HI16 : SDNodeXForm<imm, [{ 316 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 317}]>; 318 319// Plus 1. 320def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 321 322// Node immediate fits as 16-bit sign extended on target immediate. 323// e.g. addi, andi 324def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 325 326// Node immediate fits as 16-bit sign extended on target immediate. 327// e.g. addi, andi 328def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 329 330// Node immediate fits as 15-bit sign extended on target immediate. 331// e.g. addi, andi 332def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 333 334// Node immediate fits as 16-bit zero extended on target immediate. 335// The LO16 param means that only the lower 16 bits of the node 336// immediate are caught. 337// e.g. addiu, sltiu 338def immZExt16 : PatLeaf<(imm), [{ 339 if (N->getValueType(0) == MVT::i32) 340 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 341 else 342 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 343}], LO16>; 344 345// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 346def immLow16Zero : PatLeaf<(imm), [{ 347 int64_t Val = N->getSExtValue(); 348 return isInt<32>(Val) && !(Val & 0xffff); 349}]>; 350 351// shamt field must fit in 5 bits. 352def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 353 354// True if (N + 1) fits in 16-bit field. 355def immSExt16Plus1 : PatLeaf<(imm), [{ 356 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 357}]>; 358 359// Mips Address Mode! SDNode frameindex could possibily be a match 360// since load and store instructions from stack used it. 361def addr : 362 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 363 364def addrRegImm : 365 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 366 367def addrDefault : 368 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 369 370//===----------------------------------------------------------------------===// 371// Instructions specific format 372//===----------------------------------------------------------------------===// 373 374// Arithmetic and logical instructions with 3 register operands. 375class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 376 InstrItinClass Itin = NoItinerary, 377 SDPatternOperator OpNode = null_frag>: 378 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 379 !strconcat(opstr, "\t$rd, $rs, $rt"), 380 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 381 let isCommutable = isComm; 382 let isReMaterializable = 1; 383} 384 385// Arithmetic and logical instructions with 2 register operands. 386class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 387 SDPatternOperator imm_type = null_frag, 388 SDPatternOperator OpNode = null_frag> : 389 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 390 !strconcat(opstr, "\t$rt, $rs, $imm16"), 391 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 392 IIAlu, FrmI, opstr> { 393 let isReMaterializable = 1; 394 let TwoOperandAliasConstraint = "$rs = $rt"; 395} 396 397// Arithmetic Multiply ADD/SUB 398class MArithR<string opstr, bit isComm = 0> : 399 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 400 !strconcat(opstr, "\t$rs, $rt"), [], IIImul, FrmR> { 401 let Defs = [HI, LO]; 402 let Uses = [HI, LO]; 403 let isCommutable = isComm; 404} 405 406// Logical 407class LogicNOR<string opstr, RegisterOperand RC>: 408 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 409 !strconcat(opstr, "\t$rd, $rs, $rt"), 410 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> { 411 let isCommutable = 1; 412} 413 414// Shifts 415class shift_rotate_imm<string opstr, Operand ImmOpnd, 416 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 417 SDPatternOperator PF = null_frag> : 418 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 419 !strconcat(opstr, "\t$rd, $rt, $shamt"), 420 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR, opstr>; 421 422class shift_rotate_reg<string opstr, RegisterOperand RC, 423 SDPatternOperator OpNode = null_frag>: 424 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 425 !strconcat(opstr, "\t$rd, $rt, $rs"), 426 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR, opstr>; 427 428// Load Upper Imediate 429class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 430 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 431 [], IIAlu, FrmI>, IsAsCheapAsAMove { 432 let neverHasSideEffects = 1; 433 let isReMaterializable = 1; 434} 435 436class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 437 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 438 bits<21> addr; 439 let Inst{25-21} = addr{20-16}; 440 let Inst{15-0} = addr{15-0}; 441 let DecoderMethod = "DecodeMem"; 442} 443 444// Memory Load/Store 445class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 446 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> : 447 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 448 [(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, 449 !strconcat(opstr, ofsuffix)> { 450 let DecoderMethod = "DecodeMem"; 451 let canFoldAsLoad = 1; 452 let mayLoad = 1; 453} 454 455class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 456 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> : 457 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 458 [(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI, 459 !strconcat(opstr, ofsuffix)> { 460 let DecoderMethod = "DecodeMem"; 461 let mayStore = 1; 462} 463 464multiclass LoadM<string opstr, RegisterClass RC, 465 SDPatternOperator OpNode = null_frag, 466 ComplexPattern Addr = addr> { 467 def NAME : Load<opstr, OpNode, RC, mem, Addr, "">, 468 Requires<[NotN64, HasStdEnc]>; 469 def _P8 : Load<opstr, OpNode, RC, mem64, Addr, "_p8">, 470 Requires<[IsN64, HasStdEnc]> { 471 let DecoderNamespace = "Mips64"; 472 let isCodeGenOnly = 1; 473 } 474} 475 476multiclass StoreM<string opstr, RegisterClass RC, 477 SDPatternOperator OpNode = null_frag, 478 ComplexPattern Addr = addr> { 479 def NAME : Store<opstr, OpNode, RC, mem, Addr, "">, 480 Requires<[NotN64, HasStdEnc]>; 481 def _P8 : Store<opstr, OpNode, RC, mem64, Addr, "_p8">, 482 Requires<[IsN64, HasStdEnc]> { 483 let DecoderNamespace = "Mips64"; 484 let isCodeGenOnly = 1; 485 } 486} 487 488// Load/Store Left/Right 489let canFoldAsLoad = 1 in 490class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 491 Operand MemOpnd> : 492 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 493 !strconcat(opstr, "\t$rt, $addr"), 494 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 495 let DecoderMethod = "DecodeMem"; 496 string Constraints = "$src = $rt"; 497} 498 499class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 500 Operand MemOpnd>: 501 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 502 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 503 let DecoderMethod = "DecodeMem"; 504} 505 506multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 507 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 508 Requires<[NotN64, HasStdEnc]>; 509 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 510 Requires<[IsN64, HasStdEnc]> { 511 let DecoderNamespace = "Mips64"; 512 let isCodeGenOnly = 1; 513 } 514} 515 516multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 517 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 518 Requires<[NotN64, HasStdEnc]>; 519 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 520 Requires<[IsN64, HasStdEnc]> { 521 let DecoderNamespace = "Mips64"; 522 let isCodeGenOnly = 1; 523 } 524} 525 526// Conditional Branch 527class CBranch<string opstr, PatFrag cond_op, RegisterOperand RC> : 528 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 529 !strconcat(opstr, "\t$rs, $rt, $offset"), 530 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 531 FrmI> { 532 let isBranch = 1; 533 let isTerminator = 1; 534 let hasDelaySlot = 1; 535 let Defs = [AT]; 536} 537 538class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RC> : 539 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 540 !strconcat(opstr, "\t$rs, $offset"), 541 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 542 let isBranch = 1; 543 let isTerminator = 1; 544 let hasDelaySlot = 1; 545 let Defs = [AT]; 546} 547 548// SetCC 549class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 550 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 551 !strconcat(opstr, "\t$rd, $rs, $rt"), 552 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], 553 IIAlu, FrmR, opstr>; 554 555class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 556 RegisterClass RC>: 557 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 558 !strconcat(opstr, "\t$rt, $rs, $imm16"), 559 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 560 IIAlu, FrmI, opstr>; 561 562// Jump 563class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 564 SDPatternOperator targetoperator> : 565 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 566 [(operator targetoperator:$target)], IIBranch, FrmJ> { 567 let isTerminator=1; 568 let isBarrier=1; 569 let hasDelaySlot = 1; 570 let DecoderMethod = "DecodeJumpTarget"; 571 let Defs = [AT]; 572} 573 574// Unconditional branch 575class UncondBranch<string opstr> : 576 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 577 [(br bb:$offset)], IIBranch, FrmI> { 578 let isBranch = 1; 579 let isTerminator = 1; 580 let isBarrier = 1; 581 let hasDelaySlot = 1; 582 let Predicates = [RelocPIC, HasStdEnc]; 583 let Defs = [AT]; 584} 585 586// Base class for indirect branch and return instruction classes. 587let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 588class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 589 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 590 591// Indirect branch 592class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 593 let isBranch = 1; 594 let isIndirectBranch = 1; 595} 596 597// Return instruction 598class RetBase<RegisterClass RC>: JumpFR<RC> { 599 let isReturn = 1; 600 let isCodeGenOnly = 1; 601 let hasCtrlDep = 1; 602 let hasExtraSrcRegAllocReq = 1; 603} 604 605// Jump and Link (Call) 606let isCall=1, hasDelaySlot=1, Defs = [RA] in { 607 class JumpLink<string opstr> : 608 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 609 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 610 let DecoderMethod = "DecodeJumpTarget"; 611 } 612 613 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, 614 Register RetReg>: 615 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, 616 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; 617 618 class JumpLinkReg<string opstr, RegisterClass RC>: 619 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 620 [], IIBranch, FrmR>; 621 622 class BGEZAL_FT<string opstr, RegisterOperand RO> : 623 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 624 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 625 626} 627 628class BAL_FT : 629 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 630 let isBranch = 1; 631 let isTerminator = 1; 632 let isBarrier = 1; 633 let hasDelaySlot = 1; 634 let Defs = [RA]; 635} 636 637// Sync 638let hasSideEffects = 1 in 639class SYNC_FT : 640 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 641 NoItinerary, FrmOther>; 642 643// Mul, Div 644class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 645 list<Register> DefRegs> : 646 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 647 itin, FrmR, opstr> { 648 let isCommutable = 1; 649 let Defs = DefRegs; 650 let neverHasSideEffects = 1; 651} 652 653// Pseudo multiply/divide instruction with explicit accumulator register 654// operands. 655class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 656 SDPatternOperator OpNode, InstrItinClass Itin, 657 bit IsComm = 1, bit HasSideEffects = 0> : 658 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 659 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 660 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 661 let isCommutable = IsComm; 662 let hasSideEffects = HasSideEffects; 663} 664 665// Pseudo multiply add/sub instruction with explicit accumulator register 666// operands. 667class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 668 : PseudoSE<(outs ACRegs:$ac), 669 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin), 670 [(set ACRegs:$ac, 671 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))], 672 IIImul>, 673 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> { 674 string Constraints = "$acin = $ac"; 675} 676 677class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 678 list<Register> DefRegs> : 679 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 680 [], itin, FrmR> { 681 let Defs = DefRegs; 682} 683 684// Move from Hi/Lo 685class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 686 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 687 let Uses = UseRegs; 688 let neverHasSideEffects = 1; 689} 690 691class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 692 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 693 let Defs = DefRegs; 694 let neverHasSideEffects = 1; 695} 696 697class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 698 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 699 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 700 let isCodeGenOnly = 1; 701 let DecoderMethod = "DecodeMem"; 702} 703 704// Count Leading Ones/Zeros in Word 705class CountLeading0<string opstr, RegisterOperand RO>: 706 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 707 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 708 Requires<[HasBitCount, HasStdEnc]>; 709 710class CountLeading1<string opstr, RegisterOperand RO>: 711 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 712 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 713 Requires<[HasBitCount, HasStdEnc]>; 714 715 716// Sign Extend in Register. 717class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 718 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 719 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 720 let Predicates = [HasSEInReg, HasStdEnc]; 721} 722 723// Subword Swap 724class SubwordSwap<string opstr, RegisterOperand RO>: 725 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 726 NoItinerary, FrmR> { 727 let Predicates = [HasSwap, HasStdEnc]; 728 let neverHasSideEffects = 1; 729} 730 731// Read Hardware 732class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 733 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 734 IIAlu, FrmR>; 735 736// Ext and Ins 737class ExtBase<string opstr, RegisterOperand RO>: 738 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 739 !strconcat(opstr, " $rt, $rs, $pos, $size"), 740 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 741 FrmR> { 742 let Predicates = [HasMips32r2, HasStdEnc]; 743} 744 745class InsBase<string opstr, RegisterOperand RO>: 746 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 747 !strconcat(opstr, " $rt, $rs, $pos, $size"), 748 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 749 NoItinerary, FrmR> { 750 let Predicates = [HasMips32r2, HasStdEnc]; 751 let Constraints = "$src = $rt"; 752} 753 754// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 755class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 756 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 757 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 758 759multiclass Atomic2Ops32<PatFrag Op> { 760 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 761 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 762 Requires<[IsN64, HasStdEnc]> { 763 let DecoderNamespace = "Mips64"; 764 } 765} 766 767// Atomic Compare & Swap. 768class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 769 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 770 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 771 772multiclass AtomicCmpSwap32<PatFrag Op> { 773 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 774 Requires<[NotN64, HasStdEnc]>; 775 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 776 Requires<[IsN64, HasStdEnc]> { 777 let DecoderNamespace = "Mips64"; 778 } 779} 780 781class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 782 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 783 [], NoItinerary, FrmI> { 784 let DecoderMethod = "DecodeMem"; 785 let mayLoad = 1; 786} 787 788class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 789 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 790 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 791 let DecoderMethod = "DecodeMem"; 792 let mayStore = 1; 793 let Constraints = "$rt = $dst"; 794} 795 796class MFC3OP<dag outs, dag ins, string asmstr> : 797 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 798 799//===----------------------------------------------------------------------===// 800// Pseudo instructions 801//===----------------------------------------------------------------------===// 802 803// Return RA. 804let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 805def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 806 807let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 808def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 809 [(callseq_start timm:$amt)]>; 810def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 811 [(callseq_end timm:$amt1, timm:$amt2)]>; 812} 813 814let usesCustomInserter = 1 in { 815 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 816 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 817 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 818 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 819 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 820 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 821 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 822 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 823 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 824 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 825 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 826 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 827 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 828 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 829 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 830 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 831 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 832 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 833 834 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 835 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 836 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 837 838 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 839 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 840 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 841} 842 843/// Pseudo instructions for loading and storing accumulator registers. 844let isPseudo = 1 in { 845 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>; 846 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>; 847} 848 849//===----------------------------------------------------------------------===// 850// Instruction definition 851//===----------------------------------------------------------------------===// 852//===----------------------------------------------------------------------===// 853// MipsI Instructions 854//===----------------------------------------------------------------------===// 855 856/// Arithmetic Instructions (ALU Immediate) 857def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 858 ADDI_FM<0x9>, IsAsCheapAsAMove; 859def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 860def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, 861 SLTI_FM<0xa>; 862def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, 863 SLTI_FM<0xb>; 864def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 865 ADDI_FM<0xc>; 866def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 867 ADDI_FM<0xd>; 868def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 869 ADDI_FM<0xe>; 870def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 871 872/// Arithmetic Instructions (3-Operand, R-Type) 873def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, 874 ADD_FM<0, 0x21>; 875def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, 876 ADD_FM<0, 0x23>; 877def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, 878 ADD_FM<0x1c, 2>; 879def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 880def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 881def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 882def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 883def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, 884 ADD_FM<0, 0x24>; 885def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, 886 ADD_FM<0, 0x25>; 887def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, 888 ADD_FM<0, 0x26>; 889def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 890 891/// Shift Instructions 892def SLL : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 893 SRA_FM<0, 0>; 894def SRL : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 895 SRA_FM<2, 0>; 896def SRA : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 897 SRA_FM<3, 0>; 898def SLLV : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 899def SRLV : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 900def SRAV : MMRel, shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 901 902// Rotate Instructions 903let Predicates = [HasMips32r2, HasStdEnc] in { 904 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, 905 immZExt5>, 906 SRA_FM<2, 1>; 907 def ROTRV : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, 908 SRLV_FM<6, 1>; 909} 910 911/// Load and Store Instructions 912/// aligned 913defm LB : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM<0x20>; 914defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, MMRel, LW_FM<0x24>; 915defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, MMRel, LW_FM<0x21>; 916defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM<0x25>; 917defm LW : LoadM<"lw", CPURegs, load, addrDefault>, MMRel, LW_FM<0x23>; 918defm SB : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM<0x28>; 919defm SH : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM<0x29>; 920defm SW : StoreM<"sw", CPURegs, store>, MMRel, LW_FM<0x2b>; 921 922/// load/store left/right 923defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 924defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 925defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 926defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 927 928def SYNC : SYNC_FT, SYNC_FM; 929 930/// Load-linked, Store-conditional 931let Predicates = [NotN64, HasStdEnc] in { 932 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 933 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 934} 935 936let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 937 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 938 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 939} 940 941/// Jump and Branch Instructions 942def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 943 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 944def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 945def B : UncondBranch<"b">, B_FM; 946def BEQ : CBranch<"beq", seteq, CPURegsOpnd>, BEQ_FM<4>; 947def BNE : CBranch<"bne", setne, CPURegsOpnd>, BEQ_FM<5>; 948def BGEZ : CBranchZero<"bgez", setge, CPURegsOpnd>, BGEZ_FM<1, 1>; 949def BGTZ : CBranchZero<"bgtz", setgt, CPURegsOpnd>, BGEZ_FM<7, 0>; 950def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>; 951def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>; 952 953def BAL_BR: BAL_FT, BAL_FM; 954 955def JAL : JumpLink<"jal">, FJ<3>; 956def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 957def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; 958def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 959def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 960def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 961def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 962 963def RET : RetBase<CPURegs>, MTLO_FM<8>; 964 965// Exception handling related node and instructions. 966// The conversion sequence is: 967// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 968// MIPSeh_return -> (stack change + indirect branch) 969// 970// MIPSeh_return takes the place of regular return instruction 971// but takes two arguments (V1, V0) which are used for storing 972// the offset and return address respectively. 973def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 974 975def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 976 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 977 978let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 979 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst), 980 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>; 981 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff, 982 CPU64Regs:$dst), 983 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>; 984} 985 986/// Multiply and Divide Instructions. 987def MULT : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, 988 MULT_FM<0, 0x18>; 989def MULTu : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, 990 MULT_FM<0, 0x19>; 991def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>; 992def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>; 993def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>; 994def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>; 995def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv, 996 0>; 997def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv, 998 0>; 999 1000def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 1001def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 1002def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 1003def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 1004 1005/// Sign Ext In Register Instructions. 1006def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 1007def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 1008 1009/// Count Leading 1010def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 1011def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 1012 1013/// Word Swap Bytes Within Halfwords 1014def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 1015 1016/// No operation. 1017def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1018 1019// FrameIndexes are legalized when they are operands from load/store 1020// instructions. The same not happens for stack address copies, so an 1021// add op with mem ComplexPattern is used and the stack address copy 1022// can be matched. It's similar to Sparc LEA_ADDRi 1023def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 1024 1025// MADD*/MSUB* 1026def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1027def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1028def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>; 1029def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>; 1030def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1031def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1032def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1033def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1034 1035def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 1036 1037def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 1038def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 1039 1040/// Move Control Registers From/To CPU Registers 1041def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1042 (ins CPURegsOpnd:$rd, uimm16:$sel), 1043 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 1044 1045def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1046 (ins CPURegsOpnd:$rt), 1047 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 1048 1049def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1050 (ins CPURegsOpnd:$rd, uimm16:$sel), 1051 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 1052 1053def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1054 (ins CPURegsOpnd:$rt), 1055 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 1056 1057//===----------------------------------------------------------------------===// 1058// Instruction aliases 1059//===----------------------------------------------------------------------===// 1060def : InstAlias<"move $dst, $src", 1061 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1062 Requires<[NotMips64]>; 1063def : InstAlias<"move $dst, $src", 1064 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1065 Requires<[NotMips64]>; 1066def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; 1067def : InstAlias<"addu $rs, $rt, $imm", 1068 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1069def : InstAlias<"add $rs, $rt, $imm", 1070 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1071def : InstAlias<"and $rs, $rt, $imm", 1072 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1073def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, 1074 Requires<[NotMips64]>; 1075def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; 1076def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>; 1077def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>, 1078 Requires<[NotMips64]>; 1079def : InstAlias<"not $rt, $rs", 1080 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; 1081def : InstAlias<"neg $rt, $rs", 1082 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1083def : InstAlias<"negu $rt, $rs", 1084 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1085def : InstAlias<"slt $rs, $rt, $imm", 1086 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; 1087def : InstAlias<"xor $rs, $rt, $imm", 1088 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>, 1089 Requires<[NotMips64]>; 1090def : InstAlias<"or $rs, $rt, $imm", 1091 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>, 1092 Requires<[NotMips64]>; 1093def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1094def : InstAlias<"mfc0 $rt, $rd", 1095 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1096def : InstAlias<"mtc0 $rt, $rd", 1097 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1098def : InstAlias<"mfc2 $rt, $rd", 1099 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1100def : InstAlias<"mtc2 $rt, $rd", 1101 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1102def : InstAlias<"bnez $rs,$offset", 1103 (BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, 1104 Requires<[NotMips64]>; 1105def : InstAlias<"beqz $rs,$offset", 1106 (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, 1107 Requires<[NotMips64]>; 1108//===----------------------------------------------------------------------===// 1109// Assembler Pseudo Instructions 1110//===----------------------------------------------------------------------===// 1111 1112class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1113 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1114 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1115def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 1116 1117class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1118 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1119 !strconcat(instr_asm, "\t$rt, $addr")> ; 1120def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 1121 1122class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1123 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1124 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1125def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 1126 1127 1128 1129//===----------------------------------------------------------------------===// 1130// Arbitrary patterns that map to one or more instructions 1131//===----------------------------------------------------------------------===// 1132 1133// Load/store pattern templates. 1134class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1135 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1136 1137class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1138 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1139 1140// Small immediates 1141def : MipsPat<(i32 immSExt16:$in), 1142 (ADDiu ZERO, imm:$in)>; 1143def : MipsPat<(i32 immZExt16:$in), 1144 (ORi ZERO, imm:$in)>; 1145def : MipsPat<(i32 immLow16Zero:$in), 1146 (LUi (HI16 imm:$in))>; 1147 1148// Arbitrary immediates 1149def : MipsPat<(i32 imm:$imm), 1150 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1151 1152// Carry MipsPatterns 1153def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1154 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1155let Predicates = [HasStdEnc, NotDSP] in { 1156 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1157 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1158 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1159 (ADDiu CPURegs:$src, imm:$imm)>; 1160} 1161 1162// Call 1163def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1164 (JAL tglobaladdr:$dst)>; 1165def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1166 (JAL texternalsym:$dst)>; 1167//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1168// (JALR CPURegs:$dst)>; 1169 1170// Tail call 1171def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1172 (TAILCALL tglobaladdr:$dst)>; 1173def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1174 (TAILCALL texternalsym:$dst)>; 1175// hi/lo relocs 1176def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1177def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1178def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1179def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1180def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1181def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1182 1183def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1184def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1185def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1186def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1187def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1188def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1189 1190def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1191 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1192def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1193 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1194def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1195 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1196def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1197 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1198def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1199 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1200 1201// gp_rel relocs 1202def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1203 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1204def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1205 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1206 1207// wrapper_pic 1208class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1209 MipsPat<(MipsWrapper RC:$gp, node:$in), 1210 (ADDiuOp RC:$gp, node:$in)>; 1211 1212def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1213def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1214def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1215def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1216def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1217def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1218 1219// Mips does not have "not", so we expand our way 1220def : MipsPat<(not CPURegs:$in), 1221 (NOR CPURegsOpnd:$in, ZERO)>; 1222 1223// extended loads 1224let Predicates = [NotN64, HasStdEnc] in { 1225 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1226 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1227 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1228} 1229let Predicates = [IsN64, HasStdEnc] in { 1230 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1231 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1232 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1233} 1234 1235// peepholes 1236let Predicates = [NotN64, HasStdEnc] in { 1237 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1238} 1239let Predicates = [IsN64, HasStdEnc] in { 1240 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1241} 1242 1243// brcond patterns 1244multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1245 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1246 Instruction SLTiuOp, Register ZEROReg> { 1247def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1248 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1249def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1250 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1251 1252def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1253 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1254def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1255 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1256def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1257 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1258def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1259 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1260 1261def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1262 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1263def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1264 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1265 1266def : MipsPat<(brcond RC:$cond, bb:$dst), 1267 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1268} 1269 1270defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1271 1272// setcc patterns 1273multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1274 Instruction SLTuOp, Register ZEROReg> { 1275 def : MipsPat<(seteq RC:$lhs, 0), 1276 (SLTiuOp RC:$lhs, 1)>; 1277 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1278 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1279 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1280 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1281} 1282 1283multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1284 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1285 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1286 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1287 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1288} 1289 1290multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1291 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1292 (SLTOp RC:$rhs, RC:$lhs)>; 1293 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1294 (SLTuOp RC:$rhs, RC:$lhs)>; 1295} 1296 1297multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1298 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1299 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1300 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1301 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1302} 1303 1304multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1305 Instruction SLTiuOp> { 1306 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1307 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1308 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1309 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1310} 1311 1312defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1313defm : SetlePats<CPURegs, SLT, SLTu>; 1314defm : SetgtPats<CPURegs, SLT, SLTu>; 1315defm : SetgePats<CPURegs, SLT, SLTu>; 1316defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1317 1318// bswap pattern 1319def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1320 1321// mflo/hi patterns. 1322def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)), 1323 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>; 1324 1325// Load halfword/word patterns. 1326let AddedComplexity = 40 in { 1327 let Predicates = [NotN64, HasStdEnc] in { 1328 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1329 def : LoadRegImmPat<LH, i32, sextloadi16>; 1330 def : LoadRegImmPat<LW, i32, load>; 1331 } 1332 let Predicates = [IsN64, HasStdEnc] in { 1333 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>; 1334 def : LoadRegImmPat<LH_P8, i32, sextloadi16>; 1335 def : LoadRegImmPat<LW_P8, i32, load>; 1336 } 1337} 1338 1339//===----------------------------------------------------------------------===// 1340// Floating Point Support 1341//===----------------------------------------------------------------------===// 1342 1343include "MipsInstrFPU.td" 1344include "Mips64InstrInfo.td" 1345include "MipsCondMov.td" 1346 1347// 1348// Mips16 1349 1350include "Mips16InstrFormats.td" 1351include "Mips16InstrInfo.td" 1352 1353// DSP 1354include "MipsDSPInstrFormats.td" 1355include "MipsDSPInstrInfo.td" 1356 1357// Micromips 1358include "MicroMipsInstrFormats.td" 1359include "MicroMipsInstrInfo.td" 1360