MipsInstrInfo.td revision ec3199f675b17b12fd779df557c6bff25aa4e862
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_MipsMAddMSub : SDTypeProfile<0, 4, 27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>, 28 SDTCisSameAs<1, 2>, 29 SDTCisSameAs<2, 3>]>; 30def SDT_MipsDivRem : SDTypeProfile<0, 2, 31 [SDTCisInt<0>, 32 SDTCisSameAs<0, 1>]>; 33 34def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 35 36def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 37 38def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 40def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 42 SDTCisSameAs<0, 4>]>; 43 44def SDTMipsLoadLR : SDTypeProfile<1, 2, 45 [SDTCisInt<0>, SDTCisPtrTy<1>, 46 SDTCisSameAs<0, 2>]>; 47 48// Call 49def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 51 SDNPVariadic]>; 52 53// Tail call 54def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 56 57// Hi and Lo nodes are used to handle global addresses. Used on 58// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 59// static model. (nothing to do with Mips Registers Hi and Lo) 60def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 61def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 62def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 63 64// TlsGd node is used to handle General Dynamic TLS 65def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 66 67// TprelHi and TprelLo nodes are used to handle Local Exec TLS 68def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 69def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 70 71// Thread pointer 72def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 73 74// Return 75def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; 76 77// These are target-independent nodes, but have target-specific formats. 78def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 80def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 81 [SDNPHasChain, SDNPSideEffect, 82 SDNPOptInGlue, SDNPOutGlue]>; 83 84// MAdd*/MSub* nodes 85def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub, 86 [SDNPOptInGlue, SDNPOutGlue]>; 87def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub, 88 [SDNPOptInGlue, SDNPOutGlue]>; 89def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub, 90 [SDNPOptInGlue, SDNPOutGlue]>; 91def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub, 92 [SDNPOptInGlue, SDNPOutGlue]>; 93 94// DivRem(u) nodes 95def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem, 96 [SDNPOutGlue]>; 97def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem, 98 [SDNPOutGlue]>; 99 100// Target constant nodes that are not part of any isel patterns and remain 101// unchanged can cause instructions with illegal operands to be emitted. 102// Wrapper node patterns give the instruction selector a chance to replace 103// target constant nodes that would otherwise remain unchanged with ADDiu 104// nodes. Without these wrapper node patterns, the following conditional move 105// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 106// compiled: 107// movn %got(d)($gp), %got(c)($gp), $4 108// This instruction is illegal since movn can take only register operands. 109 110def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 111 112def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 113 114def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 115def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 116 117def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 119def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 121def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 123def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 125def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 127def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 129def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 131def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 133 134//===----------------------------------------------------------------------===// 135// Mips Instruction Predicate Definitions. 136//===----------------------------------------------------------------------===// 137def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 138 AssemblerPredicate<"FeatureSEInReg">; 139def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 140 AssemblerPredicate<"FeatureBitCount">; 141def HasSwap : Predicate<"Subtarget.hasSwap()">, 142 AssemblerPredicate<"FeatureSwap">; 143def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 144 AssemblerPredicate<"FeatureCondMov">; 145def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 146 AssemblerPredicate<"FeatureFPIdx">; 147def HasMips32 : Predicate<"Subtarget.hasMips32()">, 148 AssemblerPredicate<"FeatureMips32">; 149def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 150 AssemblerPredicate<"FeatureMips32r2">; 151def HasMips64 : Predicate<"Subtarget.hasMips64()">, 152 AssemblerPredicate<"FeatureMips64">; 153def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 154 AssemblerPredicate<"!FeatureMips64">; 155def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 156 AssemblerPredicate<"FeatureMips64r2">; 157def IsN64 : Predicate<"Subtarget.isABI_N64()">, 158 AssemblerPredicate<"FeatureN64">; 159def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 160 AssemblerPredicate<"!FeatureN64">; 161def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 162 AssemblerPredicate<"FeatureMips16">; 163def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 164 AssemblerPredicate<"FeatureMips32">; 165def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 166 AssemblerPredicate<"FeatureMips32">; 167def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 168 AssemblerPredicate<"FeatureMips32">; 169def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 170 AssemblerPredicate<"!FeatureMips16">; 171 172class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 173 let Predicates = [HasStdEnc]; 174} 175 176class IsCommutable { 177 bit isCommutable = 1; 178} 179 180class IsBranch { 181 bit isBranch = 1; 182} 183 184class IsReturn { 185 bit isReturn = 1; 186} 187 188class IsCall { 189 bit isCall = 1; 190} 191 192class IsTailCall { 193 bit isCall = 1; 194 bit isTerminator = 1; 195 bit isReturn = 1; 196 bit isBarrier = 1; 197 bit hasExtraSrcRegAllocReq = 1; 198 bit isCodeGenOnly = 1; 199} 200 201class IsAsCheapAsAMove { 202 bit isAsCheapAsAMove = 1; 203} 204 205class NeverHasSideEffects { 206 bit neverHasSideEffects = 1; 207} 208 209//===----------------------------------------------------------------------===// 210// Instruction format superclass 211//===----------------------------------------------------------------------===// 212 213include "MipsInstrFormats.td" 214 215//===----------------------------------------------------------------------===// 216// Mips Operand, Complex Patterns and Transformations Definitions. 217//===----------------------------------------------------------------------===// 218 219// Instruction operand types 220def jmptarget : Operand<OtherVT> { 221 let EncoderMethod = "getJumpTargetOpValue"; 222} 223def brtarget : Operand<OtherVT> { 224 let EncoderMethod = "getBranchTargetOpValue"; 225 let OperandType = "OPERAND_PCREL"; 226 let DecoderMethod = "DecodeBranchTarget"; 227} 228def calltarget : Operand<iPTR> { 229 let EncoderMethod = "getJumpTargetOpValue"; 230} 231def calltarget64: Operand<i64>; 232def simm16 : Operand<i32> { 233 let DecoderMethod= "DecodeSimm16"; 234} 235def simm16_64 : Operand<i64>; 236def shamt : Operand<i32>; 237 238// Unsigned Operand 239def uimm16 : Operand<i32> { 240 let PrintMethod = "printUnsignedImm"; 241} 242 243def MipsMemAsmOperand : AsmOperandClass { 244 let Name = "Mem"; 245 let ParserMethod = "parseMemOperand"; 246} 247 248// Address operand 249def mem : Operand<i32> { 250 let PrintMethod = "printMemOperand"; 251 let MIOperandInfo = (ops CPURegs, simm16); 252 let EncoderMethod = "getMemEncoding"; 253 let ParserMatchClass = MipsMemAsmOperand; 254} 255 256def mem64 : Operand<i64> { 257 let PrintMethod = "printMemOperand"; 258 let MIOperandInfo = (ops CPU64Regs, simm16_64); 259 let EncoderMethod = "getMemEncoding"; 260 let ParserMatchClass = MipsMemAsmOperand; 261} 262 263def mem_ea : Operand<i32> { 264 let PrintMethod = "printMemOperandEA"; 265 let MIOperandInfo = (ops CPURegs, simm16); 266 let EncoderMethod = "getMemEncoding"; 267} 268 269def mem_ea_64 : Operand<i64> { 270 let PrintMethod = "printMemOperandEA"; 271 let MIOperandInfo = (ops CPU64Regs, simm16_64); 272 let EncoderMethod = "getMemEncoding"; 273} 274 275// size operand of ext instruction 276def size_ext : Operand<i32> { 277 let EncoderMethod = "getSizeExtEncoding"; 278 let DecoderMethod = "DecodeExtSize"; 279} 280 281// size operand of ins instruction 282def size_ins : Operand<i32> { 283 let EncoderMethod = "getSizeInsEncoding"; 284 let DecoderMethod = "DecodeInsSize"; 285} 286 287// Transformation Function - get the lower 16 bits. 288def LO16 : SDNodeXForm<imm, [{ 289 return getImm(N, N->getZExtValue() & 0xFFFF); 290}]>; 291 292// Transformation Function - get the higher 16 bits. 293def HI16 : SDNodeXForm<imm, [{ 294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 295}]>; 296 297// Node immediate fits as 16-bit sign extended on target immediate. 298// e.g. addi, andi 299def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 300 301// Node immediate fits as 15-bit sign extended on target immediate. 302// e.g. addi, andi 303def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 304 305// Node immediate fits as 16-bit zero extended on target immediate. 306// The LO16 param means that only the lower 16 bits of the node 307// immediate are caught. 308// e.g. addiu, sltiu 309def immZExt16 : PatLeaf<(imm), [{ 310 if (N->getValueType(0) == MVT::i32) 311 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 312 else 313 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 314}], LO16>; 315 316// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 317def immLow16Zero : PatLeaf<(imm), [{ 318 int64_t Val = N->getSExtValue(); 319 return isInt<32>(Val) && !(Val & 0xffff); 320}]>; 321 322// shamt field must fit in 5 bits. 323def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 324 325// Mips Address Mode! SDNode frameindex could possibily be a match 326// since load and store instructions from stack used it. 327def addr : 328 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; 329 330//===----------------------------------------------------------------------===// 331// Instructions specific format 332//===----------------------------------------------------------------------===// 333 334// Arithmetic and logical instructions with 3 register operands. 335class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 336 InstrItinClass Itin = NoItinerary, 337 SDPatternOperator OpNode = null_frag>: 338 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 339 !strconcat(opstr, "\t$rd, $rs, $rt"), 340 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { 341 let isCommutable = isComm; 342 let isReMaterializable = 1; 343 string BaseOpcode; 344 string Arch; 345} 346 347// Arithmetic and logical instructions with 2 register operands. 348class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 349 SDPatternOperator imm_type = null_frag, 350 SDPatternOperator OpNode = null_frag> : 351 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 352 !strconcat(opstr, "\t$rt, $rs, $imm16"), 353 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> { 354 let isReMaterializable = 1; 355} 356 357// Arithmetic Multiply ADD/SUB 358class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> : 359 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 360 !strconcat(opstr, "\t$rs, $rt"), 361 [(op CPURegsOpnd:$rs, CPURegsOpnd:$rt, LO, HI)], IIImul, FrmR> { 362 let Defs = [HI, LO]; 363 let Uses = [HI, LO]; 364 let isCommutable = isComm; 365} 366 367// Logical 368class LogicNOR<string opstr, RegisterOperand RC>: 369 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 370 !strconcat(opstr, "\t$rd, $rs, $rt"), 371 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> { 372 let isCommutable = 1; 373} 374 375// Shifts 376class shift_rotate_imm<string opstr, Operand ImmOpnd, 377 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 378 SDPatternOperator PF = null_frag> : 379 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 380 !strconcat(opstr, "\t$rd, $rt, $shamt"), 381 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>; 382 383class shift_rotate_reg<string opstr, RegisterOperand RC, 384 SDPatternOperator OpNode = null_frag>: 385 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 386 !strconcat(opstr, "\t$rd, $rt, $rs"), 387 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR>; 388 389// Load Upper Imediate 390class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 391 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 392 [], IIAlu, FrmI>, IsAsCheapAsAMove { 393 let neverHasSideEffects = 1; 394 let isReMaterializable = 1; 395} 396 397class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 398 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 399 bits<21> addr; 400 let Inst{25-21} = addr{20-16}; 401 let Inst{15-0} = addr{15-0}; 402 let DecoderMethod = "DecodeMem"; 403} 404 405// Memory Load/Store 406class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 407 Operand MemOpnd> : 408 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 409 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> { 410 let DecoderMethod = "DecodeMem"; 411 let canFoldAsLoad = 1; 412} 413 414class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 415 Operand MemOpnd> : 416 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 417 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 418 let DecoderMethod = "DecodeMem"; 419} 420 421multiclass LoadM<string opstr, RegisterClass RC, 422 SDPatternOperator OpNode = null_frag> { 423 def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 424 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 425 let DecoderNamespace = "Mips64"; 426 let isCodeGenOnly = 1; 427 } 428} 429 430multiclass StoreM<string opstr, RegisterClass RC, 431 SDPatternOperator OpNode = null_frag> { 432 def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>; 433 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> { 434 let DecoderNamespace = "Mips64"; 435 let isCodeGenOnly = 1; 436 } 437} 438 439// Load/Store Left/Right 440let canFoldAsLoad = 1 in 441class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 442 Operand MemOpnd> : 443 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 444 !strconcat(opstr, "\t$rt, $addr"), 445 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 446 let DecoderMethod = "DecodeMem"; 447 string Constraints = "$src = $rt"; 448} 449 450class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 451 Operand MemOpnd>: 452 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 453 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 454 let DecoderMethod = "DecodeMem"; 455} 456 457multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 458 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 459 Requires<[NotN64, HasStdEnc]>; 460 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 461 Requires<[IsN64, HasStdEnc]> { 462 let DecoderNamespace = "Mips64"; 463 let isCodeGenOnly = 1; 464 } 465} 466 467multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 468 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 469 Requires<[NotN64, HasStdEnc]>; 470 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 471 Requires<[IsN64, HasStdEnc]> { 472 let DecoderNamespace = "Mips64"; 473 let isCodeGenOnly = 1; 474 } 475} 476 477// Conditional Branch 478class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> : 479 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 480 !strconcat(opstr, "\t$rs, $rt, $offset"), 481 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 482 FrmI> { 483 let isBranch = 1; 484 let isTerminator = 1; 485 let hasDelaySlot = 1; 486 let Defs = [AT]; 487} 488 489class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> : 490 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 491 !strconcat(opstr, "\t$rs, $offset"), 492 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 493 let isBranch = 1; 494 let isTerminator = 1; 495 let hasDelaySlot = 1; 496 let Defs = [AT]; 497} 498 499// SetCC 500class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 501 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 502 !strconcat(opstr, "\t$rd, $rs, $rt"), 503 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>; 504 505class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 506 RegisterClass RC>: 507 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 508 !strconcat(opstr, "\t$rt, $rs, $imm16"), 509 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], IIAlu, FrmI>; 510 511// Jump 512class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 513 SDPatternOperator targetoperator> : 514 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 515 [(operator targetoperator:$target)], IIBranch, FrmJ> { 516 let isTerminator=1; 517 let isBarrier=1; 518 let hasDelaySlot = 1; 519 let DecoderMethod = "DecodeJumpTarget"; 520 let Defs = [AT]; 521} 522 523// Unconditional branch 524class UncondBranch<string opstr> : 525 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 526 [(br bb:$offset)], IIBranch, FrmI> { 527 let isBranch = 1; 528 let isTerminator = 1; 529 let isBarrier = 1; 530 let hasDelaySlot = 1; 531 let Predicates = [RelocPIC, HasStdEnc]; 532 let Defs = [AT]; 533} 534 535// Base class for indirect branch and return instruction classes. 536let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 537class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 538 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 539 540// Indirect branch 541class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 542 let isBranch = 1; 543 let isIndirectBranch = 1; 544} 545 546// Return instruction 547class RetBase<RegisterClass RC>: JumpFR<RC> { 548 let isReturn = 1; 549 let isCodeGenOnly = 1; 550 let hasCtrlDep = 1; 551 let hasExtraSrcRegAllocReq = 1; 552} 553 554// Jump and Link (Call) 555let isCall=1, hasDelaySlot=1, Defs = [RA] in { 556 class JumpLink<string opstr> : 557 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 558 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 559 let DecoderMethod = "DecodeJumpTarget"; 560 } 561 562 class JumpLinkReg<string opstr, RegisterClass RC>: 563 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), 564 [(MipsJmpLink RC:$rs)], IIBranch, FrmR>; 565 566 class BGEZAL_FT<string opstr, RegisterOperand RO> : 567 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 568 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 569 570} 571 572class BAL_FT : 573 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 574 let isBranch = 1; 575 let isTerminator = 1; 576 let isBarrier = 1; 577 let hasDelaySlot = 1; 578 let Defs = [RA]; 579} 580 581// Sync 582let hasSideEffects = 1 in 583class SYNC_FT : 584 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 585 NoItinerary, FrmOther>; 586 587// Mul, Div 588class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 589 list<Register> DefRegs> : 590 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 591 itin, FrmR> { 592 let isCommutable = 1; 593 let Defs = DefRegs; 594 let neverHasSideEffects = 1; 595} 596 597class Div<SDNode op, string opstr, InstrItinClass itin, RegisterOperand RO, 598 list<Register> DefRegs> : 599 InstSE<(outs), (ins RO:$rs, RO:$rt), 600 !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RO:$rs, RO:$rt)], itin, 601 FrmR> { 602 let Defs = DefRegs; 603} 604 605// Move from Hi/Lo 606class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 607 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 608 let Uses = UseRegs; 609 let neverHasSideEffects = 1; 610} 611 612class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 613 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 614 let Defs = DefRegs; 615 let neverHasSideEffects = 1; 616} 617 618class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 619 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 620 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 621 let isCodeGenOnly = 1; 622 let DecoderMethod = "DecodeMem"; 623} 624 625// Count Leading Ones/Zeros in Word 626class CountLeading0<string opstr, RegisterOperand RO>: 627 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 628 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 629 Requires<[HasBitCount, HasStdEnc]>; 630 631class CountLeading1<string opstr, RegisterOperand RO>: 632 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 633 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 634 Requires<[HasBitCount, HasStdEnc]>; 635 636 637// Sign Extend in Register. 638class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 639 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 640 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 641 let Predicates = [HasSEInReg, HasStdEnc]; 642} 643 644// Subword Swap 645class SubwordSwap<string opstr, RegisterOperand RO>: 646 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 647 NoItinerary, FrmR> { 648 let Predicates = [HasSwap, HasStdEnc]; 649 let neverHasSideEffects = 1; 650} 651 652// Read Hardware 653class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 654 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 655 IIAlu, FrmR>; 656 657// Ext and Ins 658class ExtBase<string opstr, RegisterOperand RO>: 659 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 660 !strconcat(opstr, " $rt, $rs, $pos, $size"), 661 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 662 FrmR> { 663 let Predicates = [HasMips32r2, HasStdEnc]; 664} 665 666class InsBase<string opstr, RegisterOperand RO>: 667 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 668 !strconcat(opstr, " $rt, $rs, $pos, $size"), 669 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 670 NoItinerary, FrmR> { 671 let Predicates = [HasMips32r2, HasStdEnc]; 672 let Constraints = "$src = $rt"; 673} 674 675// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 676class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 677 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 678 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 679 680multiclass Atomic2Ops32<PatFrag Op> { 681 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 682 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 683 Requires<[IsN64, HasStdEnc]> { 684 let DecoderNamespace = "Mips64"; 685 } 686} 687 688// Atomic Compare & Swap. 689class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 690 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 691 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 692 693multiclass AtomicCmpSwap32<PatFrag Op> { 694 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 695 Requires<[NotN64, HasStdEnc]>; 696 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 697 Requires<[IsN64, HasStdEnc]> { 698 let DecoderNamespace = "Mips64"; 699 } 700} 701 702class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 703 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 704 [], NoItinerary, FrmI> { 705 let DecoderMethod = "DecodeMem"; 706 let mayLoad = 1; 707} 708 709class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 710 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 711 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 712 let DecoderMethod = "DecodeMem"; 713 let mayStore = 1; 714 let Constraints = "$rt = $dst"; 715} 716 717class MFC3OP<dag outs, dag ins, string asmstr> : 718 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 719 720//===----------------------------------------------------------------------===// 721// Pseudo instructions 722//===----------------------------------------------------------------------===// 723 724// Return RA. 725let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 726def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 727 728let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 729def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 730 [(callseq_start timm:$amt)]>; 731def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 732 [(callseq_end timm:$amt1, timm:$amt2)]>; 733} 734 735let usesCustomInserter = 1 in { 736 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 737 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 738 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 739 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 740 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 741 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 742 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 743 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 744 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 745 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 746 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 747 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 748 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 749 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 750 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 751 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 752 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 753 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 754 755 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 756 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 757 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 758 759 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 760 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 761 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 762} 763 764//===----------------------------------------------------------------------===// 765// Instruction definition 766//===----------------------------------------------------------------------===// 767//===----------------------------------------------------------------------===// 768// MipsI Instructions 769//===----------------------------------------------------------------------===// 770 771/// Arithmetic Instructions (ALU Immediate) 772def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 773 ADDI_FM<0x9>, IsAsCheapAsAMove; 774def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 775def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>; 776def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>; 777def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, ADDI_FM<0xc>; 778def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, ADDI_FM<0xd>; 779def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, ADDI_FM<0xe>; 780def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 781 782/// Arithmetic Instructions (3-Operand, R-Type) 783def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>; 784def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>; 785def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>; 786def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 787def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 788def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 789def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 790def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>; 791def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>; 792def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>; 793def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 794 795/// Shift Instructions 796def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, SRA_FM<0, 0>; 797def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, SRA_FM<2, 0>; 798def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, SRA_FM<3, 0>; 799def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 800def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 801def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 802 803// Rotate Instructions 804let Predicates = [HasMips32r2, HasStdEnc] in { 805 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>, 806 SRA_FM<2, 1>; 807 def ROTRV : shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, SRLV_FM<6, 1>; 808} 809 810/// Load and Store Instructions 811/// aligned 812defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>; 813defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>; 814defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>; 815defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>; 816defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>; 817defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>; 818defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>; 819defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>; 820 821/// load/store left/right 822defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 823defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 824defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 825defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 826 827def SYNC : SYNC_FT, SYNC_FM; 828 829/// Load-linked, Store-conditional 830let Predicates = [NotN64, HasStdEnc] in { 831 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 832 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 833} 834 835let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 836 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 837 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 838} 839 840/// Jump and Branch Instructions 841def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 842 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 843def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 844def B : UncondBranch<"b">, B_FM; 845def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>; 846def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>; 847def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>; 848def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>; 849def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>; 850def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>; 851 852def BAL_BR: BAL_FT, BAL_FM; 853 854def JAL : JumpLink<"jal">, FJ<3>; 855def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 856def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 857def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 858def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 859def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 860 861def RET : RetBase<CPURegs>, MTLO_FM<8>; 862 863/// Multiply and Divide Instructions. 864def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>; 865def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>; 866def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>; 867def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>, 868 MULT_FM<0, 0x1b>; 869 870def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 871def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 872def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 873def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 874 875/// Sign Ext In Register Instructions. 876def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 877def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 878 879/// Count Leading 880def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 881def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 882 883/// Word Swap Bytes Within Halfwords 884def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 885 886/// No operation. 887/// FIXME: NOP should be an alias of "sll $0, $0, 0". 888def NOP : InstSE<(outs), (ins), "nop", [], IIAlu, FrmJ>, NOP_FM; 889 890// FrameIndexes are legalized when they are operands from load/store 891// instructions. The same not happens for stack address copies, so an 892// add op with mem ComplexPattern is used and the stack address copy 893// can be matched. It's similar to Sparc LEA_ADDRi 894def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 895 896// MADD*/MSUB* 897def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>; 898def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>; 899def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>; 900def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>; 901 902def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 903 904def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 905def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 906 907/// Move Control Registers From/To CPU Registers 908def MFC0_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel), 909 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 910 911def MTC0_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt), 912 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 913 914def MFC2_3OP : MFC3OP<(outs CPURegs:$rt), (ins CPURegs:$rd, uimm16:$sel), 915 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 916 917def MTC2_3OP : MFC3OP<(outs CPURegs:$rd, uimm16:$sel), (ins CPURegs:$rt), 918 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 919 920//===----------------------------------------------------------------------===// 921// Instruction aliases 922//===----------------------------------------------------------------------===// 923def : InstAlias<"move $dst,$src", (ADDu CPURegsOpnd:$dst, 924 CPURegsOpnd:$src,ZERO)>, Requires<[NotMips64]>; 925def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset)>; 926def : InstAlias<"addu $rs, $rt, $imm", 927 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>; 928def : InstAlias<"add $rs, $rt, $imm", 929 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>; 930def : InstAlias<"and $rs, $rt, $imm", 931 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>; 932def : InstAlias<"j $rs", (JR CPURegs:$rs)>, Requires<[NotMips64]>; 933def : InstAlias<"not $rt, $rs", (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO)>; 934def : InstAlias<"neg $rt, $rs", (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs)>; 935def : InstAlias<"negu $rt, $rs", (SUBu CPURegsOpnd:$rt, ZERO, 936 CPURegsOpnd:$rs)>; 937def : InstAlias<"slt $rs, $rt, $imm", 938 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm)>; 939def : InstAlias<"xor $rs, $rt, $imm", 940 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm)>, 941 Requires<[NotMips64]>; 942def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 943def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 944def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>; 945def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>; 946 947//===----------------------------------------------------------------------===// 948// Assembler Pseudo Instructions 949//===----------------------------------------------------------------------===// 950 951class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 952 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 953 !strconcat(instr_asm, "\t$rt, $imm32")> ; 954def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 955 956class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 957 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 958 !strconcat(instr_asm, "\t$rt, $addr")> ; 959def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 960 961class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 962 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 963 !strconcat(instr_asm, "\t$rt, $imm32")> ; 964def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 965 966 967 968//===----------------------------------------------------------------------===// 969// Arbitrary patterns that map to one or more instructions 970//===----------------------------------------------------------------------===// 971 972// Small immediates 973def : MipsPat<(i32 immSExt16:$in), 974 (ADDiu ZERO, imm:$in)>; 975def : MipsPat<(i32 immZExt16:$in), 976 (ORi ZERO, imm:$in)>; 977def : MipsPat<(i32 immLow16Zero:$in), 978 (LUi (HI16 imm:$in))>; 979 980// Arbitrary immediates 981def : MipsPat<(i32 imm:$imm), 982 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 983 984// Carry MipsPatterns 985def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 986 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 987def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 988 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 989def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 990 (ADDiu CPURegs:$src, imm:$imm)>; 991 992// Call 993def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 994 (JAL tglobaladdr:$dst)>; 995def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 996 (JAL texternalsym:$dst)>; 997//def : MipsPat<(MipsJmpLink CPURegs:$dst), 998// (JALR CPURegs:$dst)>; 999 1000// Tail call 1001def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1002 (TAILCALL tglobaladdr:$dst)>; 1003def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1004 (TAILCALL texternalsym:$dst)>; 1005// hi/lo relocs 1006def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1007def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1008def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1009def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1010def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1011def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1012 1013def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1014def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1015def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1016def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1017def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1018def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1019 1020def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1021 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1022def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1023 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1024def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1025 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1026def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1027 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1028def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1029 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1030 1031// gp_rel relocs 1032def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1033 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1034def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1035 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1036 1037// wrapper_pic 1038class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1039 MipsPat<(MipsWrapper RC:$gp, node:$in), 1040 (ADDiuOp RC:$gp, node:$in)>; 1041 1042def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1043def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1044def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1045def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1046def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1047def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1048 1049// Mips does not have "not", so we expand our way 1050def : MipsPat<(not CPURegs:$in), 1051 (NOR CPURegsOpnd:$in, ZERO)>; 1052 1053// extended loads 1054let Predicates = [NotN64, HasStdEnc] in { 1055 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1056 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1057 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1058} 1059let Predicates = [IsN64, HasStdEnc] in { 1060 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1061 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1062 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1063} 1064 1065// peepholes 1066let Predicates = [NotN64, HasStdEnc] in { 1067 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1068} 1069let Predicates = [IsN64, HasStdEnc] in { 1070 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1071} 1072 1073// brcond patterns 1074multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1075 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1076 Instruction SLTiuOp, Register ZEROReg> { 1077def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1078 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1079def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1080 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1081 1082def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1083 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1084def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1085 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1086def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1087 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1088def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1089 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1090 1091def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1092 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1093def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1094 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1095 1096def : MipsPat<(brcond RC:$cond, bb:$dst), 1097 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1098} 1099 1100defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1101 1102// setcc patterns 1103multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1104 Instruction SLTuOp, Register ZEROReg> { 1105 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1106 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1107 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1108 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1109} 1110 1111multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1112 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1113 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1114 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1115 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1116} 1117 1118multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1119 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1120 (SLTOp RC:$rhs, RC:$lhs)>; 1121 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1122 (SLTuOp RC:$rhs, RC:$lhs)>; 1123} 1124 1125multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1126 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1127 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1128 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1129 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1130} 1131 1132multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1133 Instruction SLTiuOp> { 1134 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1135 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1136 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1137 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1138} 1139 1140defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1141defm : SetlePats<CPURegs, SLT, SLTu>; 1142defm : SetgtPats<CPURegs, SLT, SLTu>; 1143defm : SetgePats<CPURegs, SLT, SLTu>; 1144defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1145 1146// bswap pattern 1147def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1148 1149//===----------------------------------------------------------------------===// 1150// Floating Point Support 1151//===----------------------------------------------------------------------===// 1152 1153include "MipsInstrFPU.td" 1154include "Mips64InstrInfo.td" 1155include "MipsCondMov.td" 1156 1157// 1158// Mips16 1159 1160include "Mips16InstrFormats.td" 1161include "Mips16InstrInfo.td" 1162 1163// DSP 1164include "MipsDSPInstrFormats.td" 1165include "MipsDSPInstrInfo.td" 1166 1167