MipsInstrInfo.td revision f894199a14fff1399f6ee9d78c6a601d86649155
1//===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the Mips implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14 15//===----------------------------------------------------------------------===// 16// Mips profiles and nodes 17//===----------------------------------------------------------------------===// 18 19def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 20def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, 21 SDTCisSameAs<1, 2>, 22 SDTCisSameAs<3, 4>, 23 SDTCisInt<4>]>; 24def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 25def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 26def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>, 27 SDTCisVT<2, i32>]>; 28def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, 29 SDTCisVT<1, i32>, 30 SDTCisSameAs<1, 2>]>; 31def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>, 32 SDTCisSameAs<1, 2>]>; 33def SDT_MipsMAddMSub : SDTypeProfile<1, 3, 34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>, 35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>; 36def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>; 37 38def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; 39 40def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; 41 42def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>; 44def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>, 45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>, 46 SDTCisSameAs<0, 4>]>; 47 48def SDTMipsLoadLR : SDTypeProfile<1, 2, 49 [SDTCisInt<0>, SDTCisPtrTy<1>, 50 SDTCisSameAs<0, 2>]>; 51 52// Call 53def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, 54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 55 SDNPVariadic]>; 56 57// Tail call 58def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink, 59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 60 61// Hi and Lo nodes are used to handle global addresses. Used on 62// MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol 63// static model. (nothing to do with Mips Registers Hi and Lo) 64def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>; 65def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; 66def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; 67 68// TlsGd node is used to handle General Dynamic TLS 69def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; 70 71// TprelHi and TprelLo nodes are used to handle Local Exec TLS 72def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; 73def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; 74 75// Thread pointer 76def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; 77 78// Return 79def MipsRet : SDNode<"MipsISD::Ret", SDTNone, 80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 81 82// These are target-independent nodes, but have target-specific formats. 83def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart, 84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 85def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd, 86 [SDNPHasChain, SDNPSideEffect, 87 SDNPOptInGlue, SDNPOutGlue]>; 88 89// Node used to extract integer from LO/HI register. 90def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>; 91 92// Node used to insert 32-bit integers to LOHI register pair. 93def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>; 94 95// Mult nodes. 96def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>; 97def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>; 98 99// MAdd*/MSub* nodes 100def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>; 101def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>; 102def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>; 103def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>; 104 105// DivRem(u) nodes 106def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>; 107def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>; 108def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, 109 [SDNPOutGlue]>; 110def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16, 111 [SDNPOutGlue]>; 112 113// Target constant nodes that are not part of any isel patterns and remain 114// unchanged can cause instructions with illegal operands to be emitted. 115// Wrapper node patterns give the instruction selector a chance to replace 116// target constant nodes that would otherwise remain unchanged with ADDiu 117// nodes. Without these wrapper node patterns, the following conditional move 118// instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is 119// compiled: 120// movn %got(d)($gp), %got(c)($gp), $4 121// This instruction is illegal since movn can take only register operands. 122 123def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>; 124 125def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>; 126 127def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>; 128def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>; 129 130def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR, 131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 132def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR, 133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 134def MipsSWL : SDNode<"MipsISD::SWL", SDTStore, 135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 136def MipsSWR : SDNode<"MipsISD::SWR", SDTStore, 137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 138def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR, 139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 140def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR, 141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; 142def MipsSDL : SDNode<"MipsISD::SDL", SDTStore, 143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 144def MipsSDR : SDNode<"MipsISD::SDR", SDTStore, 145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>; 146 147//===----------------------------------------------------------------------===// 148// Mips Instruction Predicate Definitions. 149//===----------------------------------------------------------------------===// 150def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">, 151 AssemblerPredicate<"FeatureSEInReg">; 152def HasBitCount : Predicate<"Subtarget.hasBitCount()">, 153 AssemblerPredicate<"FeatureBitCount">; 154def HasSwap : Predicate<"Subtarget.hasSwap()">, 155 AssemblerPredicate<"FeatureSwap">; 156def HasCondMov : Predicate<"Subtarget.hasCondMov()">, 157 AssemblerPredicate<"FeatureCondMov">; 158def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">, 159 AssemblerPredicate<"FeatureFPIdx">; 160def HasMips32 : Predicate<"Subtarget.hasMips32()">, 161 AssemblerPredicate<"FeatureMips32">; 162def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, 163 AssemblerPredicate<"FeatureMips32r2">; 164def HasMips64 : Predicate<"Subtarget.hasMips64()">, 165 AssemblerPredicate<"FeatureMips64">; 166def NotMips64 : Predicate<"!Subtarget.hasMips64()">, 167 AssemblerPredicate<"!FeatureMips64">; 168def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, 169 AssemblerPredicate<"FeatureMips64r2">; 170def IsN64 : Predicate<"Subtarget.isABI_N64()">, 171 AssemblerPredicate<"FeatureN64">; 172def NotN64 : Predicate<"!Subtarget.isABI_N64()">, 173 AssemblerPredicate<"!FeatureN64">; 174def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, 175 AssemblerPredicate<"FeatureMips16">; 176def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">, 177 AssemblerPredicate<"FeatureMips32">; 178def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">, 179 AssemblerPredicate<"FeatureMips32">; 180def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">, 181 AssemblerPredicate<"FeatureMips32">; 182def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">, 183 AssemblerPredicate<"!FeatureMips16">; 184def NotDSP : Predicate<"!Subtarget.hasDSP()">; 185 186class MipsPat<dag pattern, dag result> : Pat<pattern, result> { 187 let Predicates = [HasStdEnc]; 188} 189 190class IsCommutable { 191 bit isCommutable = 1; 192} 193 194class IsBranch { 195 bit isBranch = 1; 196} 197 198class IsReturn { 199 bit isReturn = 1; 200} 201 202class IsCall { 203 bit isCall = 1; 204} 205 206class IsTailCall { 207 bit isCall = 1; 208 bit isTerminator = 1; 209 bit isReturn = 1; 210 bit isBarrier = 1; 211 bit hasExtraSrcRegAllocReq = 1; 212 bit isCodeGenOnly = 1; 213} 214 215class IsAsCheapAsAMove { 216 bit isAsCheapAsAMove = 1; 217} 218 219class NeverHasSideEffects { 220 bit neverHasSideEffects = 1; 221} 222 223//===----------------------------------------------------------------------===// 224// Instruction format superclass 225//===----------------------------------------------------------------------===// 226 227include "MipsInstrFormats.td" 228 229//===----------------------------------------------------------------------===// 230// Mips Operand, Complex Patterns and Transformations Definitions. 231//===----------------------------------------------------------------------===// 232 233// Instruction operand types 234def jmptarget : Operand<OtherVT> { 235 let EncoderMethod = "getJumpTargetOpValue"; 236} 237def brtarget : Operand<OtherVT> { 238 let EncoderMethod = "getBranchTargetOpValue"; 239 let OperandType = "OPERAND_PCREL"; 240 let DecoderMethod = "DecodeBranchTarget"; 241} 242def calltarget : Operand<iPTR> { 243 let EncoderMethod = "getJumpTargetOpValue"; 244} 245def calltarget64: Operand<i64>; 246def simm16 : Operand<i32> { 247 let DecoderMethod= "DecodeSimm16"; 248} 249 250def simm20 : Operand<i32> { 251} 252 253def simm16_64 : Operand<i64>; 254def shamt : Operand<i32>; 255 256// Unsigned Operand 257def uimm16 : Operand<i32> { 258 let PrintMethod = "printUnsignedImm"; 259} 260 261def MipsMemAsmOperand : AsmOperandClass { 262 let Name = "Mem"; 263 let ParserMethod = "parseMemOperand"; 264} 265 266// Address operand 267def mem : Operand<i32> { 268 let PrintMethod = "printMemOperand"; 269 let MIOperandInfo = (ops CPURegs, simm16); 270 let EncoderMethod = "getMemEncoding"; 271 let ParserMatchClass = MipsMemAsmOperand; 272 let OperandType = "OPERAND_MEMORY"; 273} 274 275def mem64 : Operand<i64> { 276 let PrintMethod = "printMemOperand"; 277 let MIOperandInfo = (ops CPU64Regs, simm16_64); 278 let EncoderMethod = "getMemEncoding"; 279 let ParserMatchClass = MipsMemAsmOperand; 280 let OperandType = "OPERAND_MEMORY"; 281} 282 283def mem_ea : Operand<i32> { 284 let PrintMethod = "printMemOperandEA"; 285 let MIOperandInfo = (ops CPURegs, simm16); 286 let EncoderMethod = "getMemEncoding"; 287 let OperandType = "OPERAND_MEMORY"; 288} 289 290def mem_ea_64 : Operand<i64> { 291 let PrintMethod = "printMemOperandEA"; 292 let MIOperandInfo = (ops CPU64Regs, simm16_64); 293 let EncoderMethod = "getMemEncoding"; 294 let OperandType = "OPERAND_MEMORY"; 295} 296 297// size operand of ext instruction 298def size_ext : Operand<i32> { 299 let EncoderMethod = "getSizeExtEncoding"; 300 let DecoderMethod = "DecodeExtSize"; 301} 302 303// size operand of ins instruction 304def size_ins : Operand<i32> { 305 let EncoderMethod = "getSizeInsEncoding"; 306 let DecoderMethod = "DecodeInsSize"; 307} 308 309// Transformation Function - get the lower 16 bits. 310def LO16 : SDNodeXForm<imm, [{ 311 return getImm(N, N->getZExtValue() & 0xFFFF); 312}]>; 313 314// Transformation Function - get the higher 16 bits. 315def HI16 : SDNodeXForm<imm, [{ 316 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF); 317}]>; 318 319// Plus 1. 320def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>; 321 322// Node immediate fits as 16-bit sign extended on target immediate. 323// e.g. addi, andi 324def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; 325 326// Node immediate fits as 16-bit sign extended on target immediate. 327// e.g. addi, andi 328def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; 329 330// Node immediate fits as 15-bit sign extended on target immediate. 331// e.g. addi, andi 332def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; 333 334// Node immediate fits as 16-bit zero extended on target immediate. 335// The LO16 param means that only the lower 16 bits of the node 336// immediate are caught. 337// e.g. addiu, sltiu 338def immZExt16 : PatLeaf<(imm), [{ 339 if (N->getValueType(0) == MVT::i32) 340 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 341 else 342 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); 343}], LO16>; 344 345// Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). 346def immLow16Zero : PatLeaf<(imm), [{ 347 int64_t Val = N->getSExtValue(); 348 return isInt<32>(Val) && !(Val & 0xffff); 349}]>; 350 351// shamt field must fit in 5 bits. 352def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; 353 354// True if (N + 1) fits in 16-bit field. 355def immSExt16Plus1 : PatLeaf<(imm), [{ 356 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1); 357}]>; 358 359// Mips Address Mode! SDNode frameindex could possibily be a match 360// since load and store instructions from stack used it. 361def addr : 362 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>; 363 364def addrRegImm : 365 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>; 366 367def addrDefault : 368 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; 369 370//===----------------------------------------------------------------------===// 371// Instructions specific format 372//===----------------------------------------------------------------------===// 373 374// Arithmetic and logical instructions with 3 register operands. 375class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0, 376 InstrItinClass Itin = NoItinerary, 377 SDPatternOperator OpNode = null_frag>: 378 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt), 379 !strconcat(opstr, "\t$rd, $rs, $rt"), 380 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> { 381 let isCommutable = isComm; 382 let isReMaterializable = 1; 383} 384 385// Arithmetic and logical instructions with 2 register operands. 386class ArithLogicI<string opstr, Operand Od, RegisterOperand RO, 387 SDPatternOperator imm_type = null_frag, 388 SDPatternOperator OpNode = null_frag> : 389 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16), 390 !strconcat(opstr, "\t$rt, $rs, $imm16"), 391 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], 392 IIAlu, FrmI, opstr> { 393 let isReMaterializable = 1; 394 let TwoOperandAliasConstraint = "$rs = $rt"; 395} 396 397// Arithmetic Multiply ADD/SUB 398class MArithR<string opstr, bit isComm = 0> : 399 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt), 400 !strconcat(opstr, "\t$rs, $rt"), [], IIImul, FrmR> { 401 let Defs = [HI, LO]; 402 let Uses = [HI, LO]; 403 let isCommutable = isComm; 404} 405 406// Logical 407class LogicNOR<string opstr, RegisterOperand RC>: 408 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt), 409 !strconcat(opstr, "\t$rd, $rs, $rt"), 410 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> { 411 let isCommutable = 1; 412} 413 414// Shifts 415class shift_rotate_imm<string opstr, Operand ImmOpnd, 416 RegisterOperand RC, SDPatternOperator OpNode = null_frag, 417 SDPatternOperator PF = null_frag> : 418 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt), 419 !strconcat(opstr, "\t$rd, $rt, $shamt"), 420 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR, opstr>; 421 422class shift_rotate_reg<string opstr, RegisterOperand RC, 423 SDPatternOperator OpNode = null_frag>: 424 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt), 425 !strconcat(opstr, "\t$rd, $rt, $rs"), 426 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR, opstr>; 427 428// Load Upper Imediate 429class LoadUpper<string opstr, RegisterClass RC, Operand Imm>: 430 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"), 431 [], IIAlu, FrmI>, IsAsCheapAsAMove { 432 let neverHasSideEffects = 1; 433 let isReMaterializable = 1; 434} 435 436class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern, 437 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> { 438 bits<21> addr; 439 let Inst{25-21} = addr{20-16}; 440 let Inst{15-0} = addr{15-0}; 441 let DecoderMethod = "DecodeMem"; 442} 443 444// Memory Load/Store 445class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC, 446 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> : 447 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 448 [(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, 449 !strconcat(opstr, ofsuffix)> { 450 let DecoderMethod = "DecodeMem"; 451 let canFoldAsLoad = 1; 452 let mayLoad = 1; 453} 454 455class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC, 456 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> : 457 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 458 [(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI, 459 !strconcat(opstr, ofsuffix)> { 460 let DecoderMethod = "DecodeMem"; 461 let mayStore = 1; 462} 463 464multiclass LoadM<string opstr, RegisterClass RC, 465 SDPatternOperator OpNode = null_frag, 466 ComplexPattern Addr = addr> { 467 def NAME : Load<opstr, OpNode, RC, mem, Addr, "">, 468 Requires<[NotN64, HasStdEnc]>; 469 def _P8 : Load<opstr, OpNode, RC, mem64, Addr, "_p8">, 470 Requires<[IsN64, HasStdEnc]> { 471 let DecoderNamespace = "Mips64"; 472 let isCodeGenOnly = 1; 473 } 474} 475 476multiclass StoreM<string opstr, RegisterClass RC, 477 SDPatternOperator OpNode = null_frag, 478 ComplexPattern Addr = addr> { 479 def NAME : Store<opstr, OpNode, RC, mem, Addr, "">, 480 Requires<[NotN64, HasStdEnc]>; 481 def _P8 : Store<opstr, OpNode, RC, mem64, Addr, "_p8">, 482 Requires<[IsN64, HasStdEnc]> { 483 let DecoderNamespace = "Mips64"; 484 let isCodeGenOnly = 1; 485 } 486} 487 488// Load/Store Left/Right 489let canFoldAsLoad = 1 in 490class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 491 Operand MemOpnd> : 492 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src), 493 !strconcat(opstr, "\t$rt, $addr"), 494 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> { 495 let DecoderMethod = "DecodeMem"; 496 string Constraints = "$src = $rt"; 497} 498 499class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC, 500 Operand MemOpnd>: 501 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), 502 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> { 503 let DecoderMethod = "DecodeMem"; 504} 505 506multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 507 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>, 508 Requires<[NotN64, HasStdEnc]>; 509 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>, 510 Requires<[IsN64, HasStdEnc]> { 511 let DecoderNamespace = "Mips64"; 512 let isCodeGenOnly = 1; 513 } 514} 515 516multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> { 517 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>, 518 Requires<[NotN64, HasStdEnc]>; 519 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>, 520 Requires<[IsN64, HasStdEnc]> { 521 let DecoderNamespace = "Mips64"; 522 let isCodeGenOnly = 1; 523 } 524} 525 526// Conditional Branch 527class CBranch<string opstr, PatFrag cond_op, RegisterOperand RC> : 528 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset), 529 !strconcat(opstr, "\t$rs, $rt, $offset"), 530 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch, 531 FrmI> { 532 let isBranch = 1; 533 let isTerminator = 1; 534 let hasDelaySlot = 1; 535 let Defs = [AT]; 536} 537 538class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RC> : 539 InstSE<(outs), (ins RC:$rs, brtarget:$offset), 540 !strconcat(opstr, "\t$rs, $offset"), 541 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> { 542 let isBranch = 1; 543 let isTerminator = 1; 544 let hasDelaySlot = 1; 545 let Defs = [AT]; 546} 547 548// SetCC 549class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> : 550 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt), 551 !strconcat(opstr, "\t$rd, $rs, $rt"), 552 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], 553 IIAlu, FrmR, opstr>; 554 555class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type, 556 RegisterClass RC>: 557 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16), 558 !strconcat(opstr, "\t$rt, $rs, $imm16"), 559 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))], 560 IIAlu, FrmI, opstr>; 561 562// Jump 563class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator, 564 SDPatternOperator targetoperator> : 565 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), 566 [(operator targetoperator:$target)], IIBranch, FrmJ> { 567 let isTerminator=1; 568 let isBarrier=1; 569 let hasDelaySlot = 1; 570 let DecoderMethod = "DecodeJumpTarget"; 571 let Defs = [AT]; 572} 573 574// Unconditional branch 575class UncondBranch<string opstr> : 576 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"), 577 [(br bb:$offset)], IIBranch, FrmI> { 578 let isBranch = 1; 579 let isTerminator = 1; 580 let isBarrier = 1; 581 let hasDelaySlot = 1; 582 let Predicates = [RelocPIC, HasStdEnc]; 583 let Defs = [AT]; 584} 585 586// Base class for indirect branch and return instruction classes. 587let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in 588class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>: 589 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>; 590 591// Indirect branch 592class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> { 593 let isBranch = 1; 594 let isIndirectBranch = 1; 595} 596 597// Return instruction 598class RetBase<RegisterClass RC>: JumpFR<RC> { 599 let isReturn = 1; 600 let isCodeGenOnly = 1; 601 let hasCtrlDep = 1; 602 let hasExtraSrcRegAllocReq = 1; 603} 604 605// Jump and Link (Call) 606let isCall=1, hasDelaySlot=1, Defs = [RA] in { 607 class JumpLink<string opstr> : 608 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"), 609 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> { 610 let DecoderMethod = "DecodeJumpTarget"; 611 } 612 613 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst, 614 Register RetReg>: 615 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>, 616 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>; 617 618 class JumpLinkReg<string opstr, RegisterClass RC>: 619 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"), 620 [], IIBranch, FrmR>; 621 622 class BGEZAL_FT<string opstr, RegisterOperand RO> : 623 InstSE<(outs), (ins RO:$rs, brtarget:$offset), 624 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>; 625 626} 627 628class BAL_FT : 629 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> { 630 let isBranch = 1; 631 let isTerminator = 1; 632 let isBarrier = 1; 633 let hasDelaySlot = 1; 634 let Defs = [RA]; 635} 636 637// Sync 638let hasSideEffects = 1 in 639class SYNC_FT : 640 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)], 641 NoItinerary, FrmOther>; 642 643let hasSideEffects = 1 in 644class TEQ_FT<string opstr, RegisterOperand RO> : 645 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_), 646 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>; 647 648// Mul, Div 649class Mult<string opstr, InstrItinClass itin, RegisterOperand RO, 650 list<Register> DefRegs> : 651 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [], 652 itin, FrmR, opstr> { 653 let isCommutable = 1; 654 let Defs = DefRegs; 655 let neverHasSideEffects = 1; 656} 657 658// Pseudo multiply/divide instruction with explicit accumulator register 659// operands. 660class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1, 661 SDPatternOperator OpNode, InstrItinClass Itin, 662 bit IsComm = 1, bit HasSideEffects = 0, 663 bit UsesCustomInserter = 0> : 664 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt), 665 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>, 666 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> { 667 let isCommutable = IsComm; 668 let hasSideEffects = HasSideEffects; 669 let usesCustomInserter = UsesCustomInserter; 670} 671 672// Pseudo multiply add/sub instruction with explicit accumulator register 673// operands. 674class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode> 675 : PseudoSE<(outs ACRegs:$ac), 676 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin), 677 [(set ACRegs:$ac, 678 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))], 679 IIImul>, 680 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> { 681 string Constraints = "$acin = $ac"; 682} 683 684class Div<string opstr, InstrItinClass itin, RegisterOperand RO, 685 list<Register> DefRegs> : 686 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"), 687 [], itin, FrmR> { 688 let Defs = DefRegs; 689} 690 691// Move from Hi/Lo 692class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>: 693 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> { 694 let Uses = UseRegs; 695 let neverHasSideEffects = 1; 696} 697 698class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>: 699 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> { 700 let Defs = DefRegs; 701 let neverHasSideEffects = 1; 702} 703 704class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> : 705 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 706 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> { 707 let isCodeGenOnly = 1; 708 let DecoderMethod = "DecodeMem"; 709} 710 711// Count Leading Ones/Zeros in Word 712class CountLeading0<string opstr, RegisterOperand RO>: 713 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 714 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>, 715 Requires<[HasBitCount, HasStdEnc]>; 716 717class CountLeading1<string opstr, RegisterOperand RO>: 718 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), 719 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>, 720 Requires<[HasBitCount, HasStdEnc]>; 721 722 723// Sign Extend in Register. 724class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> : 725 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"), 726 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> { 727 let Predicates = [HasSEInReg, HasStdEnc]; 728} 729 730// Subword Swap 731class SubwordSwap<string opstr, RegisterOperand RO>: 732 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], 733 NoItinerary, FrmR> { 734 let Predicates = [HasSwap, HasStdEnc]; 735 let neverHasSideEffects = 1; 736} 737 738// Read Hardware 739class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> : 740 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [], 741 IIAlu, FrmR>; 742 743// Ext and Ins 744class ExtBase<string opstr, RegisterOperand RO>: 745 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size), 746 !strconcat(opstr, " $rt, $rs, $pos, $size"), 747 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary, 748 FrmR> { 749 let Predicates = [HasMips32r2, HasStdEnc]; 750} 751 752class InsBase<string opstr, RegisterOperand RO>: 753 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src), 754 !strconcat(opstr, " $rt, $rs, $pos, $size"), 755 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))], 756 NoItinerary, FrmR> { 757 let Predicates = [HasMips32r2, HasStdEnc]; 758 let Constraints = "$src = $rt"; 759} 760 761// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*). 762class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 763 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr), 764 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>; 765 766multiclass Atomic2Ops32<PatFrag Op> { 767 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>; 768 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>, 769 Requires<[IsN64, HasStdEnc]> { 770 let DecoderNamespace = "Mips64"; 771 } 772} 773 774// Atomic Compare & Swap. 775class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> : 776 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap), 777 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>; 778 779multiclass AtomicCmpSwap32<PatFrag Op> { 780 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>, 781 Requires<[NotN64, HasStdEnc]>; 782 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>, 783 Requires<[IsN64, HasStdEnc]> { 784 let DecoderNamespace = "Mips64"; 785 } 786} 787 788class LLBase<string opstr, RegisterOperand RO, Operand Mem> : 789 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"), 790 [], NoItinerary, FrmI> { 791 let DecoderMethod = "DecodeMem"; 792 let mayLoad = 1; 793} 794 795class SCBase<string opstr, RegisterOperand RO, Operand Mem> : 796 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr), 797 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { 798 let DecoderMethod = "DecodeMem"; 799 let mayStore = 1; 800 let Constraints = "$rt = $dst"; 801} 802 803class MFC3OP<dag outs, dag ins, string asmstr> : 804 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>; 805 806//===----------------------------------------------------------------------===// 807// Pseudo instructions 808//===----------------------------------------------------------------------===// 809 810// Return RA. 811let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in 812def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>; 813 814let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 815def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt), 816 [(callseq_start timm:$amt)]>; 817def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 818 [(callseq_end timm:$amt1, timm:$amt2)]>; 819} 820 821let usesCustomInserter = 1 in { 822 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>; 823 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>; 824 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>; 825 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>; 826 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>; 827 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>; 828 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>; 829 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>; 830 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>; 831 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>; 832 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>; 833 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>; 834 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>; 835 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>; 836 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>; 837 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>; 838 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>; 839 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>; 840 841 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>; 842 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>; 843 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>; 844 845 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>; 846 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>; 847 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>; 848} 849 850/// Pseudo instructions for loading and storing accumulator registers. 851let isPseudo = 1 in { 852 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>; 853 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>; 854} 855 856//===----------------------------------------------------------------------===// 857// Instruction definition 858//===----------------------------------------------------------------------===// 859//===----------------------------------------------------------------------===// 860// MipsI Instructions 861//===----------------------------------------------------------------------===// 862 863/// Arithmetic Instructions (ALU Immediate) 864def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>, 865 ADDI_FM<0x9>, IsAsCheapAsAMove; 866def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>; 867def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, 868 SLTI_FM<0xa>; 869def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, 870 SLTI_FM<0xb>; 871def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>, 872 ADDI_FM<0xc>; 873def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>, 874 ADDI_FM<0xd>; 875def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>, 876 ADDI_FM<0xe>; 877def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM; 878 879/// Arithmetic Instructions (3-Operand, R-Type) 880def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, 881 ADD_FM<0, 0x21>; 882def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, 883 ADD_FM<0, 0x23>; 884def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, 885 ADD_FM<0x1c, 2>; 886def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>; 887def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>; 888def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>; 889def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>; 890def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, 891 ADD_FM<0, 0x24>; 892def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, 893 ADD_FM<0, 0x25>; 894def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, 895 ADD_FM<0, 0x26>; 896def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>; 897 898/// Shift Instructions 899def SLL : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>, 900 SRA_FM<0, 0>; 901def SRL : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>, 902 SRA_FM<2, 0>; 903def SRA : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>, 904 SRA_FM<3, 0>; 905def SLLV : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>; 906def SRLV : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>; 907def SRAV : MMRel, shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>; 908 909// Rotate Instructions 910let Predicates = [HasMips32r2, HasStdEnc] in { 911 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, 912 immZExt5>, 913 SRA_FM<2, 1>; 914 def ROTRV : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, 915 SRLV_FM<6, 1>; 916} 917 918/// Load and Store Instructions 919/// aligned 920defm LB : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM<0x20>; 921defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, MMRel, LW_FM<0x24>; 922defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, MMRel, LW_FM<0x21>; 923defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM<0x25>; 924defm LW : LoadM<"lw", CPURegs, load, addrDefault>, MMRel, LW_FM<0x23>; 925defm SB : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM<0x28>; 926defm SH : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM<0x29>; 927defm SW : StoreM<"sw", CPURegs, store>, MMRel, LW_FM<0x2b>; 928 929/// load/store left/right 930defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>; 931defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>; 932defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>; 933defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>; 934 935def SYNC : SYNC_FT, SYNC_FM; 936def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>; 937 938/// Load-linked, Store-conditional 939let Predicates = [NotN64, HasStdEnc] in { 940 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>; 941 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>; 942} 943 944let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in { 945 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>; 946 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>; 947} 948 949/// Jump and Branch Instructions 950def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>, 951 Requires<[RelocStatic, HasStdEnc]>, IsBranch; 952def JR : IndirectBranch<CPURegs>, MTLO_FM<8>; 953def B : UncondBranch<"b">, B_FM; 954def BEQ : CBranch<"beq", seteq, CPURegsOpnd>, BEQ_FM<4>; 955def BNE : CBranch<"bne", setne, CPURegsOpnd>, BEQ_FM<5>; 956def BGEZ : CBranchZero<"bgez", setge, CPURegsOpnd>, BGEZ_FM<1, 1>; 957def BGTZ : CBranchZero<"bgtz", setgt, CPURegsOpnd>, BGEZ_FM<7, 0>; 958def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>; 959def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>; 960 961def BAL_BR: BAL_FT, BAL_FM; 962 963def JAL : JumpLink<"jal">, FJ<3>; 964def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM; 965def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>; 966def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>; 967def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>; 968def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall; 969def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall; 970 971def RET : RetBase<CPURegs>, MTLO_FM<8>; 972 973// Exception handling related node and instructions. 974// The conversion sequence is: 975// ISD::EH_RETURN -> MipsISD::EH_RETURN -> 976// MIPSeh_return -> (stack change + indirect branch) 977// 978// MIPSeh_return takes the place of regular return instruction 979// but takes two arguments (V1, V0) which are used for storing 980// the offset and return address respectively. 981def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>; 982 983def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET, 984 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 985 986let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in { 987 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst), 988 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>; 989 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff, 990 CPU64Regs:$dst), 991 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>; 992} 993 994/// Multiply and Divide Instructions. 995def MULT : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, 996 MULT_FM<0, 0x18>; 997def MULTu : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, 998 MULT_FM<0, 0x19>; 999def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>; 1000def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>; 1001def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>; 1002def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>; 1003def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv, 1004 0, 1, 1>; 1005def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv, 1006 0, 1, 1>; 1007 1008def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>; 1009def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>; 1010def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>; 1011def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>; 1012 1013/// Sign Ext In Register Instructions. 1014def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>; 1015def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>; 1016 1017/// Count Leading 1018def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>; 1019def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>; 1020 1021/// Word Swap Bytes Within Halfwords 1022def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>; 1023 1024/// No operation. 1025def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>; 1026 1027// FrameIndexes are legalized when they are operands from load/store 1028// instructions. The same not happens for stack address copies, so an 1029// add op with mem ComplexPattern is used and the stack address copy 1030// can be matched. It's similar to Sparc LEA_ADDRi 1031def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>; 1032 1033// MADD*/MSUB* 1034def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>; 1035def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>; 1036def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>; 1037def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>; 1038def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>; 1039def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>; 1040def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>; 1041def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>; 1042 1043def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM; 1044 1045def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>; 1046def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>; 1047 1048/// Move Control Registers From/To CPU Registers 1049def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1050 (ins CPURegsOpnd:$rd, uimm16:$sel), 1051 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>; 1052 1053def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1054 (ins CPURegsOpnd:$rt), 1055 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>; 1056 1057def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt), 1058 (ins CPURegsOpnd:$rd, uimm16:$sel), 1059 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>; 1060 1061def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel), 1062 (ins CPURegsOpnd:$rt), 1063 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>; 1064 1065//===----------------------------------------------------------------------===// 1066// Instruction aliases 1067//===----------------------------------------------------------------------===// 1068def : InstAlias<"move $dst, $src", 1069 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1070 Requires<[NotMips64]>; 1071def : InstAlias<"move $dst, $src", 1072 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>, 1073 Requires<[NotMips64]>; 1074def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>; 1075def : InstAlias<"addu $rs, $rt, $imm", 1076 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1077def : InstAlias<"add $rs, $rt, $imm", 1078 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1079def : InstAlias<"and $rs, $rt, $imm", 1080 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>; 1081def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>, 1082 Requires<[NotMips64]>; 1083def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>; 1084def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>; 1085def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>, 1086 Requires<[NotMips64]>; 1087def : InstAlias<"not $rt, $rs", 1088 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>; 1089def : InstAlias<"neg $rt, $rs", 1090 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1091def : InstAlias<"negu $rt, $rs", 1092 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>; 1093def : InstAlias<"slt $rs, $rt, $imm", 1094 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>; 1095def : InstAlias<"xor $rs, $rt, $imm", 1096 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>, 1097 Requires<[NotMips64]>; 1098def : InstAlias<"or $rs, $rt, $imm", 1099 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>, 1100 Requires<[NotMips64]>; 1101def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; 1102def : InstAlias<"mfc0 $rt, $rd", 1103 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1104def : InstAlias<"mtc0 $rt, $rd", 1105 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1106def : InstAlias<"mfc2 $rt, $rd", 1107 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>; 1108def : InstAlias<"mtc2 $rt, $rd", 1109 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>; 1110def : InstAlias<"bnez $rs,$offset", 1111 (BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, 1112 Requires<[NotMips64]>; 1113def : InstAlias<"beqz $rs,$offset", 1114 (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>, 1115 Requires<[NotMips64]>; 1116//===----------------------------------------------------------------------===// 1117// Assembler Pseudo Instructions 1118//===----------------------------------------------------------------------===// 1119 1120class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> : 1121 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1122 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1123def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>; 1124 1125class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> : 1126 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr), 1127 !strconcat(instr_asm, "\t$rt, $addr")> ; 1128def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>; 1129 1130class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> : 1131 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), 1132 !strconcat(instr_asm, "\t$rt, $imm32")> ; 1133def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>; 1134 1135 1136 1137//===----------------------------------------------------------------------===// 1138// Arbitrary patterns that map to one or more instructions 1139//===----------------------------------------------------------------------===// 1140 1141// Load/store pattern templates. 1142class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : 1143 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>; 1144 1145class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : 1146 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; 1147 1148// Small immediates 1149def : MipsPat<(i32 immSExt16:$in), 1150 (ADDiu ZERO, imm:$in)>; 1151def : MipsPat<(i32 immZExt16:$in), 1152 (ORi ZERO, imm:$in)>; 1153def : MipsPat<(i32 immLow16Zero:$in), 1154 (LUi (HI16 imm:$in))>; 1155 1156// Arbitrary immediates 1157def : MipsPat<(i32 imm:$imm), 1158 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; 1159 1160// Carry MipsPatterns 1161def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs), 1162 (SUBu CPURegs:$lhs, CPURegs:$rhs)>; 1163let Predicates = [HasStdEnc, NotDSP] in { 1164 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs), 1165 (ADDu CPURegs:$lhs, CPURegs:$rhs)>; 1166 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm), 1167 (ADDiu CPURegs:$src, imm:$imm)>; 1168} 1169 1170// Call 1171def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)), 1172 (JAL tglobaladdr:$dst)>; 1173def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)), 1174 (JAL texternalsym:$dst)>; 1175//def : MipsPat<(MipsJmpLink CPURegs:$dst), 1176// (JALR CPURegs:$dst)>; 1177 1178// Tail call 1179def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), 1180 (TAILCALL tglobaladdr:$dst)>; 1181def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), 1182 (TAILCALL texternalsym:$dst)>; 1183// hi/lo relocs 1184def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>; 1185def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>; 1186def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>; 1187def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>; 1188def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; 1189def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>; 1190 1191def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>; 1192def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>; 1193def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>; 1194def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>; 1195def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>; 1196def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>; 1197 1198def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)), 1199 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>; 1200def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)), 1201 (ADDiu CPURegs:$hi, tblockaddress:$lo)>; 1202def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)), 1203 (ADDiu CPURegs:$hi, tjumptable:$lo)>; 1204def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)), 1205 (ADDiu CPURegs:$hi, tconstpool:$lo)>; 1206def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)), 1207 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; 1208 1209// gp_rel relocs 1210def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)), 1211 (ADDiu CPURegs:$gp, tglobaladdr:$in)>; 1212def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), 1213 (ADDiu CPURegs:$gp, tconstpool:$in)>; 1214 1215// wrapper_pic 1216class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>: 1217 MipsPat<(MipsWrapper RC:$gp, node:$in), 1218 (ADDiuOp RC:$gp, node:$in)>; 1219 1220def : WrapperPat<tglobaladdr, ADDiu, CPURegs>; 1221def : WrapperPat<tconstpool, ADDiu, CPURegs>; 1222def : WrapperPat<texternalsym, ADDiu, CPURegs>; 1223def : WrapperPat<tblockaddress, ADDiu, CPURegs>; 1224def : WrapperPat<tjumptable, ADDiu, CPURegs>; 1225def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>; 1226 1227// Mips does not have "not", so we expand our way 1228def : MipsPat<(not CPURegs:$in), 1229 (NOR CPURegsOpnd:$in, ZERO)>; 1230 1231// extended loads 1232let Predicates = [NotN64, HasStdEnc] in { 1233 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; 1234 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; 1235 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; 1236} 1237let Predicates = [IsN64, HasStdEnc] in { 1238 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>; 1239 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>; 1240 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>; 1241} 1242 1243// peepholes 1244let Predicates = [NotN64, HasStdEnc] in { 1245 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; 1246} 1247let Predicates = [IsN64, HasStdEnc] in { 1248 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>; 1249} 1250 1251// brcond patterns 1252multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, 1253 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, 1254 Instruction SLTiuOp, Register ZEROReg> { 1255def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), 1256 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; 1257def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), 1258 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; 1259 1260def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), 1261 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1262def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), 1263 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; 1264def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1265 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1266def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), 1267 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; 1268 1269def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), 1270 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1271def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), 1272 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; 1273 1274def : MipsPat<(brcond RC:$cond, bb:$dst), 1275 (BNEOp RC:$cond, ZEROReg, bb:$dst)>; 1276} 1277 1278defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; 1279 1280// setcc patterns 1281multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, 1282 Instruction SLTuOp, Register ZEROReg> { 1283 def : MipsPat<(seteq RC:$lhs, 0), 1284 (SLTiuOp RC:$lhs, 1)>; 1285 def : MipsPat<(seteq RC:$lhs, RC:$rhs), 1286 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>; 1287 def : MipsPat<(setne RC:$lhs, RC:$rhs), 1288 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; 1289} 1290 1291multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1292 def : MipsPat<(setle RC:$lhs, RC:$rhs), 1293 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; 1294 def : MipsPat<(setule RC:$lhs, RC:$rhs), 1295 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; 1296} 1297 1298multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1299 def : MipsPat<(setgt RC:$lhs, RC:$rhs), 1300 (SLTOp RC:$rhs, RC:$lhs)>; 1301 def : MipsPat<(setugt RC:$lhs, RC:$rhs), 1302 (SLTuOp RC:$rhs, RC:$lhs)>; 1303} 1304 1305multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { 1306 def : MipsPat<(setge RC:$lhs, RC:$rhs), 1307 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; 1308 def : MipsPat<(setuge RC:$lhs, RC:$rhs), 1309 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; 1310} 1311 1312multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, 1313 Instruction SLTiuOp> { 1314 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), 1315 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; 1316 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), 1317 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; 1318} 1319 1320defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>; 1321defm : SetlePats<CPURegs, SLT, SLTu>; 1322defm : SetgtPats<CPURegs, SLT, SLTu>; 1323defm : SetgePats<CPURegs, SLT, SLTu>; 1324defm : SetgeImmPats<CPURegs, SLTi, SLTiu>; 1325 1326// bswap pattern 1327def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>; 1328 1329// mflo/hi patterns. 1330def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)), 1331 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>; 1332 1333// Load halfword/word patterns. 1334let AddedComplexity = 40 in { 1335 let Predicates = [NotN64, HasStdEnc] in { 1336 def : LoadRegImmPat<LBu, i32, zextloadi8>; 1337 def : LoadRegImmPat<LH, i32, sextloadi16>; 1338 def : LoadRegImmPat<LW, i32, load>; 1339 } 1340 let Predicates = [IsN64, HasStdEnc] in { 1341 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>; 1342 def : LoadRegImmPat<LH_P8, i32, sextloadi16>; 1343 def : LoadRegImmPat<LW_P8, i32, load>; 1344 } 1345} 1346 1347//===----------------------------------------------------------------------===// 1348// Floating Point Support 1349//===----------------------------------------------------------------------===// 1350 1351include "MipsInstrFPU.td" 1352include "Mips64InstrInfo.td" 1353include "MipsCondMov.td" 1354 1355// 1356// Mips16 1357 1358include "Mips16InstrFormats.td" 1359include "Mips16InstrInfo.td" 1360 1361// DSP 1362include "MipsDSPInstrFormats.td" 1363include "MipsDSPInstrInfo.td" 1364 1365// Micromips 1366include "MicroMipsInstrFormats.td" 1367include "MicroMipsInstrInfo.td" 1368