MipsRegisterInfo.td revision 3531db14c61957e7ad00ce972e9685864c3887da
1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MIPS register file 12//===----------------------------------------------------------------------===// 13let Namespace = "Mips" in { 14def sub_32 : SubRegIndex<32>; 15def sub_64 : SubRegIndex<64>; 16def sub_lo : SubRegIndex<32>; 17def sub_hi : SubRegIndex<32, 32>; 18def sub_dsp16_19 : SubRegIndex<4, 16>; 19def sub_dsp20 : SubRegIndex<1, 20>; 20def sub_dsp21 : SubRegIndex<1, 21>; 21def sub_dsp22 : SubRegIndex<1, 22>; 22def sub_dsp23 : SubRegIndex<1, 23>; 23} 24 25class Unallocatable { 26 bit isAllocatable = 0; 27} 28 29// We have banks of 32 registers each. 30class MipsReg<bits<16> Enc, string n> : Register<n> { 31 let HWEncoding = Enc; 32 let Namespace = "Mips"; 33} 34 35class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 36 : RegisterWithSubRegs<n, subregs> { 37 let HWEncoding = Enc; 38 let Namespace = "Mips"; 39} 40 41// Mips CPU Registers 42class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 43 44// Mips 64-bit CPU Registers 45class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 46 : MipsRegWithSubRegs<Enc, n, subregs> { 47 let SubRegIndices = [sub_32]; 48} 49 50// Mips 32-bit FPU Registers 51class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 52 53// Mips 64-bit (aliased) FPU Registers 54class AFPR<bits<16> Enc, string n, list<Register> subregs> 55 : MipsRegWithSubRegs<Enc, n, subregs> { 56 let SubRegIndices = [sub_lo, sub_hi]; 57 let CoveredBySubRegs = 1; 58} 59 60class AFPR64<bits<16> Enc, string n, list<Register> subregs> 61 : MipsRegWithSubRegs<Enc, n, subregs> { 62 let SubRegIndices = [sub_lo, sub_hi]; 63} 64 65// Mips 128-bit (aliased) MSA Registers 66class AFPR128<bits<16> Enc, string n, list<Register> subregs> 67 : MipsRegWithSubRegs<Enc, n, subregs> { 68 let SubRegIndices = [sub_64]; 69} 70 71// Accumulator Registers 72class ACCReg<bits<16> Enc, string n, list<Register> subregs> 73 : MipsRegWithSubRegs<Enc, n, subregs> { 74 let SubRegIndices = [sub_lo, sub_hi]; 75 let CoveredBySubRegs = 1; 76} 77 78// Mips Hardware Registers 79class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 80 81//===----------------------------------------------------------------------===// 82// Registers 83//===----------------------------------------------------------------------===// 84 85let Namespace = "Mips" in { 86 // General Purpose Registers 87 def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 88 def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 89 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 90 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 91 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 92 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 93 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 94 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 95 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 96 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 97 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 98 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 99 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 100 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 101 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 102 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 103 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 104 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 105 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 106 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 107 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 108 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 109 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 110 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 111 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 112 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 113 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 114 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 115 def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 116 def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 117 def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 118 def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 119 120 // General Purpose 64-bit Registers 121 def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 122 def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 123 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 124 def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 125 def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 126 def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 127 def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 128 def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 129 def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 130 def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 131 def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 132 def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 133 def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 134 def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 135 def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 136 def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 137 def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 138 def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 139 def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 140 def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 141 def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 142 def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 143 def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 144 def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 145 def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 146 def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 147 def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 148 def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 149 def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 150 def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 151 def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 152 def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 153 154 /// Mips Single point precision FPU Registers 155 foreach I = 0-31 in 156 def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 157 158 // Higher half of 64-bit FP registers. 159 foreach I = 0-31 in 160 def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 161 162 /// Mips Double point precision FPU Registers (aliased 163 /// with the single precision to hold 64 bit values) 164 foreach I = 0-15 in 165 def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1), 166 [!cast<FPR>("F"#!shl(I, 1)), 167 !cast<FPR>("F"#!add(!shl(I, 1), 1))]>; 168 169 /// Mips Double point precision FPU Registers in MFP64 mode. 170 foreach I = 0-31 in 171 def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>, 172 DwarfRegNum<[!add(I, 32)]>; 173 174 /// Mips MSA registers 175 /// MSA and FPU cannot both be present unless the FPU has 64-bit registers 176 def W0 : AFPR128<0, "w0", [D0_64]>, DwarfRegNum<[32]>; 177 def W1 : AFPR128<1, "w1", [D1_64]>, DwarfRegNum<[33]>; 178 def W2 : AFPR128<2, "w2", [D2_64]>, DwarfRegNum<[34]>; 179 def W3 : AFPR128<3, "w3", [D3_64]>, DwarfRegNum<[35]>; 180 def W4 : AFPR128<4, "w4", [D4_64]>, DwarfRegNum<[36]>; 181 def W5 : AFPR128<5, "w5", [D5_64]>, DwarfRegNum<[37]>; 182 def W6 : AFPR128<6, "w6", [D6_64]>, DwarfRegNum<[38]>; 183 def W7 : AFPR128<7, "w7", [D7_64]>, DwarfRegNum<[39]>; 184 def W8 : AFPR128<8, "w8", [D8_64]>, DwarfRegNum<[40]>; 185 def W9 : AFPR128<9, "w9", [D9_64]>, DwarfRegNum<[41]>; 186 def W10 : AFPR128<10, "w10", [D10_64]>, DwarfRegNum<[42]>; 187 def W11 : AFPR128<11, "w11", [D11_64]>, DwarfRegNum<[43]>; 188 def W12 : AFPR128<12, "w12", [D12_64]>, DwarfRegNum<[44]>; 189 def W13 : AFPR128<13, "w13", [D13_64]>, DwarfRegNum<[45]>; 190 def W14 : AFPR128<14, "w14", [D14_64]>, DwarfRegNum<[46]>; 191 def W15 : AFPR128<15, "w15", [D15_64]>, DwarfRegNum<[47]>; 192 def W16 : AFPR128<16, "w16", [D16_64]>, DwarfRegNum<[48]>; 193 def W17 : AFPR128<17, "w17", [D17_64]>, DwarfRegNum<[49]>; 194 def W18 : AFPR128<18, "w18", [D18_64]>, DwarfRegNum<[50]>; 195 def W19 : AFPR128<19, "w19", [D19_64]>, DwarfRegNum<[51]>; 196 def W20 : AFPR128<20, "w20", [D20_64]>, DwarfRegNum<[52]>; 197 def W21 : AFPR128<21, "w21", [D21_64]>, DwarfRegNum<[53]>; 198 def W22 : AFPR128<22, "w22", [D22_64]>, DwarfRegNum<[54]>; 199 def W23 : AFPR128<23, "w23", [D23_64]>, DwarfRegNum<[55]>; 200 def W24 : AFPR128<24, "w24", [D24_64]>, DwarfRegNum<[56]>; 201 def W25 : AFPR128<25, "w25", [D25_64]>, DwarfRegNum<[57]>; 202 def W26 : AFPR128<26, "w26", [D26_64]>, DwarfRegNum<[58]>; 203 def W27 : AFPR128<27, "w27", [D27_64]>, DwarfRegNum<[59]>; 204 def W28 : AFPR128<28, "w28", [D28_64]>, DwarfRegNum<[60]>; 205 def W29 : AFPR128<29, "w29", [D29_64]>, DwarfRegNum<[61]>; 206 def W30 : AFPR128<30, "w30", [D30_64]>, DwarfRegNum<[62]>; 207 def W31 : AFPR128<31, "w31", [D31_64]>, DwarfRegNum<[63]>; 208 209 // Hi/Lo registers 210 def HI0 : Register<"ac0">, DwarfRegNum<[64]>; 211 def HI1 : Register<"ac1">, DwarfRegNum<[176]>; 212 def HI2 : Register<"ac2">, DwarfRegNum<[178]>; 213 def HI3 : Register<"ac3">, DwarfRegNum<[180]>; 214 def LO0 : Register<"ac0">, DwarfRegNum<[65]>; 215 def LO1 : Register<"ac1">, DwarfRegNum<[177]>; 216 def LO2 : Register<"ac2">, DwarfRegNum<[179]>; 217 def LO3 : Register<"ac3">, DwarfRegNum<[181]>; 218 219 let SubRegIndices = [sub_32] in { 220 def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>; 221 def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>; 222 } 223 224 // FP control registers. 225 foreach I = 0-31 in 226 def FCR#I : MipsReg<#I, ""#I>; 227 228 // FP condition code registers. 229 foreach I = 0-7 in 230 def FCC#I : MipsReg<#I, "fcc"#I>; 231 232 // PC register 233 def PC : Register<"pc">; 234 235 // Hardware register $29 236 def HWR29 : MipsReg<29, "29">; 237 238 // Accum registers 239 foreach I = 0-3 in 240 def AC#I : ACCReg<#I, "ac"#I, 241 [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>; 242 243 def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; 244 245 // DSP-ASE control register fields. 246 def DSPPos : Register<"">; 247 def DSPSCount : Register<"">; 248 def DSPCarry : Register<"">; 249 def DSPEFI : Register<"">; 250 def DSPOutFlag16_19 : Register<"">; 251 def DSPOutFlag20 : Register<"">; 252 def DSPOutFlag21 : Register<"">; 253 def DSPOutFlag22 : Register<"">; 254 def DSPOutFlag23 : Register<"">; 255 def DSPCCond : Register<"">; 256 257 let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, 258 sub_dsp23] in 259 def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, 260 DSPOutFlag21, DSPOutFlag22, 261 DSPOutFlag23]>; 262} 263 264//===----------------------------------------------------------------------===// 265// Register Classes 266//===----------------------------------------------------------------------===// 267 268class GPR32Class<list<ValueType> regTypes> : 269 RegisterClass<"Mips", regTypes, 32, (add 270 // Reserved 271 ZERO, AT, 272 // Return Values and Arguments 273 V0, V1, A0, A1, A2, A3, 274 // Not preserved across procedure calls 275 T0, T1, T2, T3, T4, T5, T6, T7, 276 // Callee save 277 S0, S1, S2, S3, S4, S5, S6, S7, 278 // Not preserved across procedure calls 279 T8, T9, 280 // Reserved 281 K0, K1, GP, SP, FP, RA)>; 282 283def GPR32 : GPR32Class<[i32]>; 284def DSPR : GPR32Class<[v4i8, v2i16]>; 285 286def GPR64 : RegisterClass<"Mips", [i64], 64, (add 287// Reserved 288 ZERO_64, AT_64, 289 // Return Values and Arguments 290 V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 291 // Not preserved across procedure calls 292 T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 293 // Callee save 294 S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 295 // Not preserved across procedure calls 296 T8_64, T9_64, 297 // Reserved 298 K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 299 300def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 301 // Return Values and Arguments 302 V0, V1, A0, A1, A2, A3, 303 // Callee save 304 S0, S1)>; 305 306def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add 307 // Return Values and Arguments 308 V0, V1, A0, A1, A2, A3, 309 // Callee save 310 S0, S1, 311 SP)>; 312 313def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 314 315def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 316 317// 64bit fp: 318// * FGR64 - 32 64-bit registers 319// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 320// 321// 32bit fp: 322// * FGR32 - 16 32-bit even registers 323// * FGR32 - 32 32-bit registers (single float only mode) 324def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 325 326def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>; 327 328def AFGR64 : RegisterClass<"Mips", [f64], 64, (add 329 // Return Values and Arguments 330 D0, D1, 331 // Not preserved across procedure calls 332 D2, D3, D4, D5, 333 // Return Values and Arguments 334 D6, D7, 335 // Not preserved across procedure calls 336 D8, D9, 337 // Callee save 338 D10, D11, D12, D13, D14, D15)>; 339 340def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 341 342// FP control registers. 343def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, 344 Unallocatable; 345 346// FP condition code registers. 347def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, 348 Unallocatable; 349 350def MSA128: RegisterClass<"Mips", 351 [v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64], 352 128, (sequence "W%u", 0, 31)>; 353 354// Hi/Lo Registers 355def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; 356def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>; 357def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; 358def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; 359def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>; 360def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>; 361 362// Hardware registers 363def HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; 364 365// Accumulator Registers 366def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> { 367 let Size = 64; 368} 369 370def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { 371 let Size = 128; 372} 373 374def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { 375 let Size = 64; 376} 377 378def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; 379 380// Register Operands. 381 382class MipsAsmRegOperand : AsmOperandClass { 383 let RenderMethod = "addRegAsmOperands"; 384} 385def GPR32AsmOperand : MipsAsmRegOperand { 386 let Name = "GPR32Asm"; 387 let ParserMethod = "parseGPR32"; 388} 389 390def GPR64AsmOperand : MipsAsmRegOperand { 391 let Name = "GPR64Asm"; 392 let ParserMethod = "parseGPR64"; 393} 394 395def ACC64DSPAsmOperand : MipsAsmRegOperand { 396 let Name = "ACC64DSPAsm"; 397 let ParserMethod = "parseACC64DSP"; 398} 399 400def LO32DSPAsmOperand : MipsAsmRegOperand { 401 let Name = "LO32DSPAsm"; 402 let ParserMethod = "parseLO32DSP"; 403} 404 405def HI32DSPAsmOperand : MipsAsmRegOperand { 406 let Name = "HI32DSPAsm"; 407 let ParserMethod = "parseHI32DSP"; 408} 409 410def CCRAsmOperand : MipsAsmRegOperand { 411 let Name = "CCRAsm"; 412 let ParserMethod = "parseCCRRegs"; 413} 414 415def AFGR64AsmOperand : MipsAsmRegOperand { 416 let Name = "AFGR64Asm"; 417 let ParserMethod = "parseAFGR64Regs"; 418} 419 420def FGR64AsmOperand : MipsAsmRegOperand { 421 let Name = "FGR64Asm"; 422 let ParserMethod = "parseFGR64Regs"; 423} 424 425def FGR32AsmOperand : MipsAsmRegOperand { 426 let Name = "FGR32Asm"; 427 let ParserMethod = "parseFGR32Regs"; 428} 429 430def FGRH32AsmOperand : MipsAsmRegOperand { 431 let Name = "FGRH32Asm"; 432 let ParserMethod = "parseFGRH32Regs"; 433} 434 435def FCCRegsAsmOperand : MipsAsmRegOperand { 436 let Name = "FCCRegsAsm"; 437 let ParserMethod = "parseFCCRegs"; 438} 439 440def GPR32Opnd : RegisterOperand<GPR32> { 441 let ParserMatchClass = GPR32AsmOperand; 442} 443 444def GPR64Opnd : RegisterOperand<GPR64> { 445 let ParserMatchClass = GPR64AsmOperand; 446} 447 448def DSPROpnd : RegisterOperand<DSPR> { 449 let ParserMatchClass = GPR32AsmOperand; 450} 451 452def CCROpnd : RegisterOperand<CCR> { 453 let ParserMatchClass = CCRAsmOperand; 454} 455 456def HWRegsAsmOperand : MipsAsmRegOperand { 457 let Name = "HWRegsAsm"; 458 let ParserMethod = "parseHWRegs"; 459} 460 461def HWRegsOpnd : RegisterOperand<HWRegs> { 462 let ParserMatchClass = HWRegsAsmOperand; 463} 464 465def AFGR64Opnd : RegisterOperand<AFGR64> { 466 let ParserMatchClass = AFGR64AsmOperand; 467} 468 469def FGR64Opnd : RegisterOperand<FGR64> { 470 let ParserMatchClass = FGR64AsmOperand; 471} 472 473def FGR32Opnd : RegisterOperand<FGR32> { 474 let ParserMatchClass = FGR32AsmOperand; 475} 476 477def FGRH32Opnd : RegisterOperand<FGRH32> { 478 let ParserMatchClass = FGRH32AsmOperand; 479} 480 481def FCCRegsOpnd : RegisterOperand<FCC> { 482 let ParserMatchClass = FCCRegsAsmOperand; 483} 484 485def LO32DSPOpnd : RegisterOperand<LO32DSP> { 486 let ParserMatchClass = LO32DSPAsmOperand; 487} 488 489def HI32DSPOpnd : RegisterOperand<HI32DSP> { 490 let ParserMatchClass = HI32DSPAsmOperand; 491} 492 493def ACC64DSPOpnd : RegisterOperand<ACC64DSP> { 494 let ParserMatchClass = ACC64DSPAsmOperand; 495} 496