PPCISelDAGToDAG.cpp revision 2fe76e58eb734a09ec08ea006a32700572ffc0ca
1//===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines a pattern matching instruction selector for 32 bit PowerPC, 11// converting from a legalized dag to a PPC dag. 12// 13//===----------------------------------------------------------------------===// 14 15#include "PowerPC.h" 16#include "PPC32TargetMachine.h" 17#include "PPC32ISelLowering.h" 18#include "llvm/CodeGen/MachineConstantPool.h" 19#include "llvm/CodeGen/MachineInstrBuilder.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/SSARegMap.h" 22#include "llvm/CodeGen/SelectionDAG.h" 23#include "llvm/CodeGen/SelectionDAGISel.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/Statistic.h" 26#include "llvm/Constants.h" 27#include "llvm/GlobalValue.h" 28#include "llvm/Support/Debug.h" 29#include "llvm/Support/MathExtras.h" 30using namespace llvm; 31 32namespace { 33 Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations"); 34 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed"); 35 36 //===--------------------------------------------------------------------===// 37 /// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine 38 /// instructions for SelectionDAG operations. 39 /// 40 class PPC32DAGToDAGISel : public SelectionDAGISel { 41 PPC32TargetLowering PPC32Lowering; 42 unsigned GlobalBaseReg; 43 public: 44 PPC32DAGToDAGISel(TargetMachine &TM) 45 : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {} 46 47 virtual bool runOnFunction(Function &Fn) { 48 // Make sure we re-emit a set of the global base reg if necessary 49 GlobalBaseReg = 0; 50 return SelectionDAGISel::runOnFunction(Fn); 51 } 52 53 /// getI32Imm - Return a target constant with the specified value, of type 54 /// i32. 55 inline SDOperand getI32Imm(unsigned Imm) { 56 return CurDAG->getTargetConstant(Imm, MVT::i32); 57 } 58 59 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC 60 /// base register. Return the virtual register that holds this value. 61 SDOperand getGlobalBaseReg(); 62 63 // Select - Convert the specified operand from a target-independent to a 64 // target-specific node if it hasn't already been changed. 65 SDOperand Select(SDOperand Op); 66 67 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS, 68 unsigned OCHi, unsigned OCLo, 69 bool IsArithmetic = false, 70 bool Negate = false); 71 SDNode *SelectBitfieldInsert(SDNode *N); 72 73 /// SelectCC - Select a comparison of the specified values with the 74 /// specified condition code, returning the CR# of the expression. 75 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC); 76 77 /// SelectAddr - Given the specified address, return the two operands for a 78 /// load/store instruction, and return true if it should be an indexed [r+r] 79 /// operation. 80 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2); 81 82 /// InstructionSelectBasicBlock - This callback is invoked by 83 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 84 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) { 85 DEBUG(BB->dump()); 86 // Select target instructions for the DAG. 87 Select(DAG.getRoot()); 88 DAG.RemoveDeadNodes(); 89 90 // Emit machine code to BB. 91 ScheduleAndEmitDAG(DAG); 92 } 93 94 virtual const char *getPassName() const { 95 return "PowerPC DAG->DAG Pattern Instruction Selection"; 96 } 97 }; 98} 99 100/// getGlobalBaseReg - Output the instructions required to put the 101/// base address to use for accessing globals into a register. 102/// 103SDOperand PPC32DAGToDAGISel::getGlobalBaseReg() { 104 if (!GlobalBaseReg) { 105 // Insert the set of GlobalBaseReg into the first MBB of the function 106 MachineBasicBlock &FirstMBB = BB->getParent()->front(); 107 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 108 SSARegMap *RegMap = BB->getParent()->getSSARegMap(); 109 GlobalBaseReg = RegMap->createVirtualRegister(PPC32::GPRCRegisterClass); 110 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR); 111 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg); 112 } 113 return CurDAG->getRegister(GlobalBaseReg, MVT::i32); 114} 115 116 117// isIntImmediate - This method tests to see if a constant operand. 118// If so Imm will receive the 32 bit value. 119static bool isIntImmediate(SDNode *N, unsigned& Imm) { 120 if (N->getOpcode() == ISD::Constant) { 121 Imm = cast<ConstantSDNode>(N)->getValue(); 122 return true; 123 } 124 return false; 125} 126 127// isOprShiftImm - Returns true if the specified operand is a shift opcode with 128// a immediate shift count less than 32. 129static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) { 130 Opc = N->getOpcode(); 131 return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) && 132 isIntImmediate(N->getOperand(1).Val, SH) && SH < 32; 133} 134 135// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with 136// any number of 0s on either side. The 1s are allowed to wrap from LSB to 137// MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is 138// not, since all 1s are not contiguous. 139static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { 140 if (isShiftedMask_32(Val)) { 141 // look for the first non-zero bit 142 MB = CountLeadingZeros_32(Val); 143 // look for the first zero bit after the run of ones 144 ME = CountLeadingZeros_32((Val - 1) ^ Val); 145 return true; 146 } else { 147 Val = ~Val; // invert mask 148 if (isShiftedMask_32(Val)) { 149 // effectively look for the first zero bit 150 ME = CountLeadingZeros_32(Val) - 1; 151 // effectively look for the first one bit after the run of zeros 152 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1; 153 return true; 154 } 155 } 156 // no run present 157 return false; 158} 159 160// isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate 161// and mask opcode and mask operation. 162static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask, 163 unsigned &SH, unsigned &MB, unsigned &ME) { 164 unsigned Shift = 32; 165 unsigned Indeterminant = ~0; // bit mask marking indeterminant results 166 unsigned Opcode = N->getOpcode(); 167 if (!isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31)) 168 return false; 169 170 if (Opcode == ISD::SHL) { 171 // apply shift left to mask if it comes first 172 if (IsShiftMask) Mask = Mask << Shift; 173 // determine which bits are made indeterminant by shift 174 Indeterminant = ~(0xFFFFFFFFu << Shift); 175 } else if (Opcode == ISD::SRA || Opcode == ISD::SRL) { 176 // apply shift right to mask if it comes first 177 if (IsShiftMask) Mask = Mask >> Shift; 178 // determine which bits are made indeterminant by shift 179 Indeterminant = ~(0xFFFFFFFFu >> Shift); 180 // adjust for the left rotate 181 Shift = 32 - Shift; 182 } else { 183 return false; 184 } 185 186 // if the mask doesn't intersect any Indeterminant bits 187 if (Mask && !(Mask & Indeterminant)) { 188 SH = Shift; 189 // make sure the mask is still a mask (wrap arounds may not be) 190 return isRunOfOnes(Mask, MB, ME); 191 } 192 return false; 193} 194 195// isOpcWithIntImmediate - This method tests to see if the node is a specific 196// opcode and that it has a immediate integer right operand. 197// If so Imm will receive the 32 bit value. 198static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { 199 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm); 200} 201 202// isOprNot - Returns true if the specified operand is an xor with immediate -1. 203static bool isOprNot(SDNode *N) { 204 unsigned Imm; 205 return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1; 206} 207 208// Immediate constant composers. 209// Lo16 - grabs the lo 16 bits from a 32 bit constant. 210// Hi16 - grabs the hi 16 bits from a 32 bit constant. 211// HA16 - computes the hi bits required if the lo bits are add/subtracted in 212// arithmethically. 213static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; } 214static unsigned Hi16(unsigned x) { return Lo16(x >> 16); } 215static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); } 216 217// isIntImmediate - This method tests to see if a constant operand. 218// If so Imm will receive the 32 bit value. 219static bool isIntImmediate(SDOperand N, unsigned& Imm) { 220 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 221 Imm = (unsigned)CN->getSignExtended(); 222 return true; 223 } 224 return false; 225} 226 227/// SelectBitfieldInsert - turn an or of two masked values into 228/// the rotate left word immediate then mask insert (rlwimi) instruction. 229/// Returns true on success, false if the caller still needs to select OR. 230/// 231/// Patterns matched: 232/// 1. or shl, and 5. or and, and 233/// 2. or and, shl 6. or shl, shr 234/// 3. or shr, and 7. or shr, shl 235/// 4. or and, shr 236SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) { 237 bool IsRotate = false; 238 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0; 239 unsigned Value; 240 241 SDOperand Op0 = N->getOperand(0); 242 SDOperand Op1 = N->getOperand(1); 243 244 unsigned Op0Opc = Op0.getOpcode(); 245 unsigned Op1Opc = Op1.getOpcode(); 246 247 // Verify that we have the correct opcodes 248 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc) 249 return false; 250 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc) 251 return false; 252 253 // Generate Mask value for Target 254 if (isIntImmediate(Op0.getOperand(1), Value)) { 255 switch(Op0Opc) { 256 case ISD::SHL: TgtMask <<= Value; break; 257 case ISD::SRL: TgtMask >>= Value; break; 258 case ISD::AND: TgtMask &= Value; break; 259 } 260 } else { 261 return 0; 262 } 263 264 // Generate Mask value for Insert 265 if (isIntImmediate(Op1.getOperand(1), Value)) { 266 switch(Op1Opc) { 267 case ISD::SHL: 268 SH = Value; 269 InsMask <<= SH; 270 if (Op0Opc == ISD::SRL) IsRotate = true; 271 break; 272 case ISD::SRL: 273 SH = Value; 274 InsMask >>= SH; 275 SH = 32-SH; 276 if (Op0Opc == ISD::SHL) IsRotate = true; 277 break; 278 case ISD::AND: 279 InsMask &= Value; 280 break; 281 } 282 } else { 283 return 0; 284 } 285 286 // If both of the inputs are ANDs and one of them has a logical shift by 287 // constant as its input, make that AND the inserted value so that we can 288 // combine the shift into the rotate part of the rlwimi instruction 289 bool IsAndWithShiftOp = false; 290 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { 291 if (Op1.getOperand(0).getOpcode() == ISD::SHL || 292 Op1.getOperand(0).getOpcode() == ISD::SRL) { 293 if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) { 294 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value; 295 IsAndWithShiftOp = true; 296 } 297 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL || 298 Op0.getOperand(0).getOpcode() == ISD::SRL) { 299 if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) { 300 std::swap(Op0, Op1); 301 std::swap(TgtMask, InsMask); 302 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value; 303 IsAndWithShiftOp = true; 304 } 305 } 306 } 307 308 // Verify that the Target mask and Insert mask together form a full word mask 309 // and that the Insert mask is a run of set bits (which implies both are runs 310 // of set bits). Given that, Select the arguments and generate the rlwimi 311 // instruction. 312 unsigned MB, ME; 313 if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) { 314 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF; 315 bool Op0IsAND = Op0Opc == ISD::AND; 316 // Check for rotlwi / rotrwi here, a special case of bitfield insert 317 // where both bitfield halves are sourced from the same value. 318 if (IsRotate && fullMask && 319 N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) { 320 Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, 321 Select(N->getOperand(0).getOperand(0)), 322 getI32Imm(SH), getI32Imm(0), getI32Imm(31)); 323 return Op0.Val; 324 } 325 SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0)) 326 : Select(Op0); 327 SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0)) 328 : Select(Op1.getOperand(0)); 329 Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2, 330 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); 331 return Op0.Val; 332 } 333 return 0; 334} 335 336// SelectIntImmediateExpr - Choose code for integer operations with an immediate 337// operand. 338SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS, 339 unsigned OCHi, unsigned OCLo, 340 bool IsArithmetic, 341 bool Negate) { 342 // Check to make sure this is a constant. 343 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS); 344 // Exit if not a constant. 345 if (!CN) return 0; 346 // Extract immediate. 347 unsigned C = (unsigned)CN->getValue(); 348 // Negate if required (ISD::SUB). 349 if (Negate) C = -C; 350 // Get the hi and lo portions of constant. 351 unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C); 352 unsigned Lo = Lo16(C); 353 354 // If two instructions are needed and usage indicates it would be better to 355 // load immediate into a register, bail out. 356 if (Hi && Lo && CN->use_size() > 2) return false; 357 358 // Select the first operand. 359 SDOperand Opr0 = Select(LHS); 360 361 if (Lo) // Add in the lo-part. 362 Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo)); 363 if (Hi) // Add in the hi-part. 364 Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi)); 365 return Opr0.Val; 366} 367 368/// SelectAddr - Given the specified address, return the two operands for a 369/// load/store instruction, and return true if it should be an indexed [r+r] 370/// operation. 371bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1, 372 SDOperand &Op2) { 373 unsigned imm = 0; 374 if (Addr.getOpcode() == ISD::ADD) { 375 if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) { 376 Op1 = getI32Imm(Lo16(imm)); 377 if (FrameIndexSDNode *FI = 378 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 379 ++FrameOff; 380 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32); 381 } else { 382 Op2 = Select(Addr.getOperand(0)); 383 } 384 return false; 385 } else { 386 Op1 = Select(Addr.getOperand(0)); 387 Op2 = Select(Addr.getOperand(1)); 388 return true; // [r+r] 389 } 390 } 391 392 // Now check if we're dealing with a global, and whether or not we should emit 393 // an optimized load or store for statics. 394 if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) { 395 GlobalValue *GV = GN->getGlobal(); 396 if (!GV->hasWeakLinkage() && !GV->isExternal()) { 397 Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32); 398 if (PICEnabled) 399 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), 400 Op1); 401 else 402 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1); 403 return false; 404 } 405 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) { 406 Op1 = getI32Imm(0); 407 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32); 408 return false; 409 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) { 410 Op1 = Addr; 411 if (PICEnabled) 412 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1); 413 else 414 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1); 415 return false; 416 } 417 Op1 = getI32Imm(0); 418 Op2 = Select(Addr); 419 return false; 420} 421 422/// SelectCC - Select a comparison of the specified values with the specified 423/// condition code, returning the CR# of the expression. 424SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, 425 ISD::CondCode CC) { 426 // Always select the LHS. 427 LHS = Select(LHS); 428 429 // Use U to determine whether the SETCC immediate range is signed or not. 430 if (MVT::isInteger(LHS.getValueType())) { 431 bool U = ISD::isUnsignedIntSetCC(CC); 432 unsigned Imm; 433 if (isIntImmediate(RHS, Imm) && 434 ((U && isUInt16(Imm)) || (!U && isInt16(Imm)))) 435 return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32, 436 LHS, getI32Imm(Lo16(Imm))); 437 return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32, 438 LHS, Select(RHS)); 439 } else { 440 return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS)); 441 } 442} 443 444/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding 445/// to Condition. 446static unsigned getBCCForSetCC(ISD::CondCode CC) { 447 switch (CC) { 448 default: assert(0 && "Unknown condition!"); abort(); 449 case ISD::SETEQ: return PPC::BEQ; 450 case ISD::SETNE: return PPC::BNE; 451 case ISD::SETULT: 452 case ISD::SETLT: return PPC::BLT; 453 case ISD::SETULE: 454 case ISD::SETLE: return PPC::BLE; 455 case ISD::SETUGT: 456 case ISD::SETGT: return PPC::BGT; 457 case ISD::SETUGE: 458 case ISD::SETGE: return PPC::BGE; 459 } 460 return 0; 461} 462 463 464// Select - Convert the specified operand from a target-independent to a 465// target-specific node if it hasn't already been changed. 466SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) { 467 SDNode *N = Op.Val; 468 if (N->getOpcode() >= ISD::BUILTIN_OP_END) 469 return Op; // Already selected. 470 471 switch (N->getOpcode()) { 472 default: 473 std::cerr << "Cannot yet select: "; 474 N->dump(); 475 std::cerr << "\n"; 476 abort(); 477 case ISD::EntryToken: // These leaves remain the same. 478 return Op; 479 case ISD::TokenFactor: { 480 SDOperand New; 481 if (N->getNumOperands() == 2) { 482 SDOperand Op0 = Select(N->getOperand(0)); 483 SDOperand Op1 = Select(N->getOperand(1)); 484 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 485 } else { 486 std::vector<SDOperand> Ops; 487 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 488 Ops.push_back(Select(N->getOperand(i))); 489 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops); 490 } 491 492 if (New.Val != N) { 493 CurDAG->ReplaceAllUsesWith(N, New.Val); 494 N = New.Val; 495 } 496 break; 497 } 498 case ISD::CopyFromReg: { 499 SDOperand Chain = Select(N->getOperand(0)); 500 if (Chain == N->getOperand(0)) return Op; // No change 501 SDOperand New = CurDAG->getCopyFromReg(Chain, 502 cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0)); 503 return New.getValue(Op.ResNo); 504 } 505 case ISD::CopyToReg: { 506 SDOperand Chain = Select(N->getOperand(0)); 507 SDOperand Reg = N->getOperand(1); 508 SDOperand Val = Select(N->getOperand(2)); 509 if (Chain != N->getOperand(0) || Val != N->getOperand(2)) { 510 SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other, 511 Chain, Reg, Val); 512 CurDAG->ReplaceAllUsesWith(N, New.Val); 513 N = New.Val; 514 } 515 break; 516 } 517 case ISD::Constant: { 518 assert(N->getValueType(0) == MVT::i32); 519 unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue(); 520 unsigned Hi = HA16(v); 521 unsigned Lo = Lo16(v); 522 if (Hi && Lo) { 523 SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32, 524 getI32Imm(v >> 16)); 525 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF)); 526 } else if (Lo) { 527 CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v)); 528 } else { 529 CurDAG->SelectNodeTo(N, MVT::i32, PPC::LIS, getI32Imm(v >> 16)); 530 } 531 break; 532 } 533 case ISD::ConstantFP: { // FIXME: this should get sucked into the legalizer 534 MachineConstantPool *CP = CurDAG->getMachineFunction().getConstantPool(); 535 Constant *CFP = ConstantFP::get(Type::FloatTy, 536 cast<ConstantFPSDNode>(N)->getValue()); 537 SDOperand CPN = CurDAG->getConstantPool(CP->getConstantPoolIndex(CFP), 538 MVT::i32); 539 SDOperand Tmp; 540 if (PICEnabled) 541 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPN); 542 else 543 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPN); 544 CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::LFS, CPN, Tmp); 545 break; 546 } 547 case ISD::UNDEF: 548 if (N->getValueType(0) == MVT::i32) 549 CurDAG->SelectNodeTo(N, MVT::i32, PPC::IMPLICIT_DEF_GPR); 550 else 551 CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::IMPLICIT_DEF_FP); 552 break; 553 case ISD::FrameIndex: { 554 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 555 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ADDI, 556 CurDAG->getTargetFrameIndex(FI, MVT::i32), 557 getI32Imm(0)); 558 break; 559 } 560 case ISD::GlobalAddress: { 561 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal(); 562 SDOperand Tmp; 563 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32); 564 if (PICEnabled) 565 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA); 566 else 567 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA); 568 569 if (GV->hasWeakLinkage() || GV->isExternal()) 570 CurDAG->SelectNodeTo(N, MVT::i32, PPC::LWZ, GA, Tmp); 571 else 572 CurDAG->SelectNodeTo(N, MVT::i32, PPC::LA, Tmp, GA); 573 break; 574 } 575 case ISD::SIGN_EXTEND_INREG: 576 switch(cast<VTSDNode>(N->getOperand(1))->getVT()) { 577 default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break; 578 case MVT::i16: 579 CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSH, Select(N->getOperand(0))); 580 break; 581 case MVT::i8: 582 CurDAG->SelectNodeTo(N, MVT::i32, PPC::EXTSB, Select(N->getOperand(0))); 583 break; 584 } 585 break; 586 case ISD::CTLZ: 587 assert(N->getValueType(0) == MVT::i32); 588 CurDAG->SelectNodeTo(N, MVT::i32, PPC::CNTLZW, Select(N->getOperand(0))); 589 break; 590 case ISD::ADD: { 591 MVT::ValueType Ty = N->getValueType(0); 592 if (Ty == MVT::i32) { 593 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1), 594 PPC::ADDIS, PPC::ADDI, true)) { 595 CurDAG->ReplaceAllUsesWith(N, I); 596 N = I; 597 } else { 598 CurDAG->SelectNodeTo(N, Ty, PPC::ADD, Select(N->getOperand(0)), 599 Select(N->getOperand(1))); 600 } 601 break; 602 } 603 604 if (!NoExcessFPPrecision) { // Match FMA ops 605 if (N->getOperand(0).getOpcode() == ISD::MUL && 606 N->getOperand(0).Val->hasOneUse()) { 607 ++FusedFP; // Statistic 608 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, 609 Select(N->getOperand(0).getOperand(0)), 610 Select(N->getOperand(0).getOperand(1)), 611 Select(N->getOperand(1))); 612 break; 613 } else if (N->getOperand(1).getOpcode() == ISD::MUL && 614 N->getOperand(1).hasOneUse()) { 615 ++FusedFP; // Statistic 616 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, 617 Select(N->getOperand(1).getOperand(0)), 618 Select(N->getOperand(1).getOperand(1)), 619 Select(N->getOperand(0))); 620 break; 621 } 622 } 623 624 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS, 625 Select(N->getOperand(0)), Select(N->getOperand(1))); 626 break; 627 } 628 case ISD::SUB: { 629 MVT::ValueType Ty = N->getValueType(0); 630 if (Ty == MVT::i32) { 631 unsigned Imm; 632 if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) { 633 if (0 == Imm) 634 CurDAG->SelectNodeTo(N, Ty, PPC::NEG, Select(N->getOperand(1))); 635 else 636 CurDAG->SelectNodeTo(N, Ty, PPC::SUBFIC, Select(N->getOperand(1)), 637 getI32Imm(Lo16(Imm))); 638 break; 639 } 640 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1), 641 PPC::ADDIS, PPC::ADDI, true, true)) { 642 CurDAG->ReplaceAllUsesWith(N, I); 643 N = I; 644 } else { 645 CurDAG->SelectNodeTo(N, Ty, PPC::SUBF, Select(N->getOperand(1)), 646 Select(N->getOperand(0))); 647 } 648 break; 649 } 650 651 if (!NoExcessFPPrecision) { // Match FMA ops 652 if (N->getOperand(0).getOpcode() == ISD::MUL && 653 N->getOperand(0).Val->hasOneUse()) { 654 ++FusedFP; // Statistic 655 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS, 656 Select(N->getOperand(0).getOperand(0)), 657 Select(N->getOperand(0).getOperand(1)), 658 Select(N->getOperand(1))); 659 break; 660 } else if (N->getOperand(1).getOpcode() == ISD::MUL && 661 N->getOperand(1).Val->hasOneUse()) { 662 ++FusedFP; // Statistic 663 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS, 664 Select(N->getOperand(1).getOperand(0)), 665 Select(N->getOperand(1).getOperand(1)), 666 Select(N->getOperand(0))); 667 break; 668 } 669 } 670 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS, 671 Select(N->getOperand(0)), 672 Select(N->getOperand(1))); 673 break; 674 } 675 case ISD::MUL: { 676 unsigned Imm, Opc; 677 if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) { 678 CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::MULLI, 679 Select(N->getOperand(0)), getI32Imm(Lo16(Imm))); 680 break; 681 } 682 switch (N->getValueType(0)) { 683 default: assert(0 && "Unhandled multiply type!"); 684 case MVT::i32: Opc = PPC::MULLW; break; 685 case MVT::f32: Opc = PPC::FMULS; break; 686 case MVT::f64: Opc = PPC::FMUL; break; 687 } 688 CurDAG->SelectNodeTo(N, N->getValueType(0), Opc, Select(N->getOperand(0)), 689 Select(N->getOperand(1))); 690 break; 691 } 692 case ISD::MULHS: 693 assert(N->getValueType(0) == MVT::i32); 694 CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHW, Select(N->getOperand(0)), 695 Select(N->getOperand(1))); 696 break; 697 case ISD::MULHU: 698 assert(N->getValueType(0) == MVT::i32); 699 CurDAG->SelectNodeTo(N, MVT::i32, PPC::MULHWU, Select(N->getOperand(0)), 700 Select(N->getOperand(1))); 701 break; 702 case ISD::AND: { 703 unsigned Imm; 704 // If this is an and of a value rotated between 0 and 31 bits and then and'd 705 // with a mask, emit rlwinm 706 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) || 707 isShiftedMask_32(~Imm))) { 708 SDOperand Val; 709 unsigned SH, MB, ME; 710 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) { 711 Val = Select(N->getOperand(0).getOperand(0)); 712 } else { 713 Val = Select(N->getOperand(0)); 714 isRunOfOnes(Imm, MB, ME); 715 SH = 0; 716 } 717 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Val, getI32Imm(SH), 718 getI32Imm(MB), getI32Imm(ME)); 719 break; 720 } 721 // If this is an and with an immediate that isn't a mask, then codegen it as 722 // high and low 16 bit immediate ands. 723 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), 724 N->getOperand(1), 725 PPC::ANDISo, PPC::ANDIo)) { 726 CurDAG->ReplaceAllUsesWith(N, I); 727 N = I; 728 break; 729 } 730 // Finally, check for the case where we are being asked to select 731 // and (not(a), b) or and (a, not(b)) which can be selected as andc. 732 if (isOprNot(N->getOperand(0).Val)) 733 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(1)), 734 Select(N->getOperand(0).getOperand(0))); 735 else if (isOprNot(N->getOperand(1).Val)) 736 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ANDC, Select(N->getOperand(0)), 737 Select(N->getOperand(1).getOperand(0))); 738 else 739 CurDAG->SelectNodeTo(N, MVT::i32, PPC::AND, Select(N->getOperand(0)), 740 Select(N->getOperand(1))); 741 break; 742 } 743 case ISD::OR: 744 if (SDNode *I = SelectBitfieldInsert(N)) { 745 CurDAG->ReplaceAllUsesWith(N, I); 746 N = I; 747 break; 748 } 749 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), 750 N->getOperand(1), 751 PPC::ORIS, PPC::ORI)) { 752 CurDAG->ReplaceAllUsesWith(N, I); 753 N = I; 754 break; 755 } 756 // Finally, check for the case where we are being asked to select 757 // 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc. 758 if (isOprNot(N->getOperand(0).Val)) 759 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORC, Select(N->getOperand(1)), 760 Select(N->getOperand(0).getOperand(0))); 761 else if (isOprNot(N->getOperand(1).Val)) 762 CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORC, Select(N->getOperand(0)), 763 Select(N->getOperand(1).getOperand(0))); 764 else 765 CurDAG->SelectNodeTo(N, MVT::i32, PPC::OR, Select(N->getOperand(0)), 766 Select(N->getOperand(1))); 767 break; 768 case ISD::XOR: 769 // Check whether or not this node is a logical 'not'. This is represented 770 // by llvm as a xor with the constant value -1 (all bits set). If this is a 771 // 'not', then fold 'or' into 'nor', and so forth for the supported ops. 772 if (isOprNot(N)) { 773 unsigned Opc; 774 SDOperand Val = Select(N->getOperand(0)); 775 switch (Val.getTargetOpcode()) { 776 default: Opc = 0; break; 777 case PPC::OR: Opc = PPC::NOR; break; 778 case PPC::AND: Opc = PPC::NAND; break; 779 case PPC::XOR: Opc = PPC::EQV; break; 780 } 781 if (Opc) 782 CurDAG->SelectNodeTo(N, MVT::i32, Opc, Val.getOperand(0), 783 Val.getOperand(1)); 784 else 785 CurDAG->SelectNodeTo(N, MVT::i32, PPC::NOR, Val, Val); 786 break; 787 } 788 // If this is a xor with an immediate other than -1, then codegen it as high 789 // and low 16 bit immediate xors. 790 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), 791 N->getOperand(1), 792 PPC::XORIS, PPC::XORI)) { 793 CurDAG->ReplaceAllUsesWith(N, I); 794 N = I; 795 break; 796 } 797 // Finally, check for the case where we are being asked to select 798 // xor (not(a), b) which is equivalent to not(xor a, b), which is eqv 799 if (isOprNot(N->getOperand(0).Val)) 800 CurDAG->SelectNodeTo(N, MVT::i32, PPC::EQV, 801 Select(N->getOperand(0).getOperand(0)), 802 Select(N->getOperand(1))); 803 else 804 CurDAG->SelectNodeTo(N, MVT::i32, PPC::XOR, Select(N->getOperand(0)), 805 Select(N->getOperand(1))); 806 break; 807 case ISD::SHL: { 808 unsigned Imm, SH, MB, ME; 809 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && 810 isRotateAndMask(N, Imm, true, SH, MB, ME)) 811 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, 812 Select(N->getOperand(0).getOperand(0)), 813 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); 814 else if (isIntImmediate(N->getOperand(1), Imm)) 815 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Select(N->getOperand(0)), 816 getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm)); 817 else 818 CurDAG->SelectNodeTo(N, MVT::i32, PPC::SLW, Select(N->getOperand(0)), 819 Select(N->getOperand(1))); 820 break; 821 } 822 case ISD::SRL: { 823 unsigned Imm, SH, MB, ME; 824 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && 825 isRotateAndMask(N, Imm, true, SH, MB, ME)) 826 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, 827 Select(N->getOperand(0).getOperand(0)), 828 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); 829 else if (isIntImmediate(N->getOperand(1), Imm)) 830 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, Select(N->getOperand(0)), 831 getI32Imm(32-Imm), getI32Imm(Imm), getI32Imm(31)); 832 else 833 CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRW, Select(N->getOperand(0)), 834 Select(N->getOperand(1))); 835 break; 836 } 837 case ISD::SRA: { 838 unsigned Imm, SH, MB, ME; 839 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && 840 isRotateAndMask(N, Imm, true, SH, MB, ME)) 841 CurDAG->SelectNodeTo(N, MVT::i32, PPC::RLWINM, 842 Select(N->getOperand(0).getOperand(0)), 843 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); 844 else if (isIntImmediate(N->getOperand(1), Imm)) 845 CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRAWI, Select(N->getOperand(0)), 846 getI32Imm(Imm)); 847 else 848 CurDAG->SelectNodeTo(N, MVT::i32, PPC::SRAW, Select(N->getOperand(0)), 849 Select(N->getOperand(1))); 850 break; 851 } 852 case ISD::FABS: 853 CurDAG->SelectNodeTo(N, N->getValueType(0), PPC::FABS, 854 Select(N->getOperand(0))); 855 break; 856 case ISD::FP_EXTEND: 857 assert(MVT::f64 == N->getValueType(0) && 858 MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND"); 859 CurDAG->SelectNodeTo(N, MVT::f64, PPC::FMR, Select(N->getOperand(0))); 860 break; 861 case ISD::FP_ROUND: 862 assert(MVT::f32 == N->getValueType(0) && 863 MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND"); 864 CurDAG->SelectNodeTo(N, MVT::f32, PPC::FRSP, Select(N->getOperand(0))); 865 break; 866 case ISD::FNEG: { 867 SDOperand Val = Select(N->getOperand(0)); 868 MVT::ValueType Ty = N->getValueType(0); 869 if (Val.Val->hasOneUse()) { 870 unsigned Opc; 871 switch (Val.getTargetOpcode()) { 872 default: Opc = 0; break; 873 case PPC::FABS: Opc = PPC::FNABS; break; 874 case PPC::FMADD: Opc = PPC::FNMADD; break; 875 case PPC::FMADDS: Opc = PPC::FNMADDS; break; 876 case PPC::FMSUB: Opc = PPC::FNMSUB; break; 877 case PPC::FMSUBS: Opc = PPC::FNMSUBS; break; 878 } 879 // If we inverted the opcode, then emit the new instruction with the 880 // inverted opcode and the original instruction's operands. Otherwise, 881 // fall through and generate a fneg instruction. 882 if (Opc) { 883 if (PPC::FNABS == Opc) 884 CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0)); 885 else 886 CurDAG->SelectNodeTo(N, Ty, Opc, Val.getOperand(0), 887 Val.getOperand(1), Val.getOperand(2)); 888 break; 889 } 890 } 891 CurDAG->SelectNodeTo(N, Ty, PPC::FNEG, Val); 892 break; 893 } 894 case ISD::FSQRT: { 895 MVT::ValueType Ty = N->getValueType(0); 896 CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS, 897 Select(N->getOperand(0))); 898 break; 899 } 900 case ISD::LOAD: 901 case ISD::EXTLOAD: 902 case ISD::ZEXTLOAD: 903 case ISD::SEXTLOAD: { 904 SDOperand Op1, Op2; 905 bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2); 906 907 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ? 908 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT(); 909 unsigned Opc; 910 switch (TypeBeingLoaded) { 911 default: N->dump(); assert(0 && "Cannot load this type!"); 912 case MVT::i1: 913 case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break; 914 case MVT::i16: 915 if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load? 916 Opc = isIdx ? PPC::LHAX : PPC::LHA; 917 } else { 918 Opc = isIdx ? PPC::LHZX : PPC::LHZ; 919 } 920 break; 921 case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break; 922 case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break; 923 case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break; 924 } 925 926 CurDAG->SelectNodeTo(N, N->getValueType(0), MVT::Other, Opc, 927 Op1, Op2, Select(N->getOperand(0))); 928 break; 929 } 930 931 case ISD::TRUNCSTORE: 932 case ISD::STORE: { 933 SDOperand AddrOp1, AddrOp2; 934 bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2); 935 936 unsigned Opc; 937 if (N->getOpcode() == ISD::STORE) { 938 switch (N->getOperand(1).getValueType()) { 939 default: assert(0 && "unknown Type in store"); 940 case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break; 941 case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break; 942 case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break; 943 } 944 } else { //ISD::TRUNCSTORE 945 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) { 946 default: assert(0 && "unknown Type in store"); 947 case MVT::i1: 948 case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break; 949 case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break; 950 } 951 } 952 953 CurDAG->SelectNodeTo(N, MVT::Other, Opc, Select(N->getOperand(1)), 954 AddrOp1, AddrOp2, Select(N->getOperand(0))); 955 break; 956 } 957 958 case ISD::CALLSEQ_START: 959 case ISD::CALLSEQ_END: { 960 unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 961 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ? 962 PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP; 963 CurDAG->SelectNodeTo(N, MVT::Other, Opc, 964 getI32Imm(Amt), Select(N->getOperand(0))); 965 break; 966 } 967 case ISD::CALL: 968 case ISD::TAILCALL: { 969 SDOperand Chain = Select(N->getOperand(0)); 970 971 unsigned CallOpcode; 972 std::vector<SDOperand> CallOperands; 973 974 if (GlobalAddressSDNode *GASD = 975 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) { 976 CallOpcode = PPC::CALLpcrel; 977 CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(), 978 MVT::i32)); 979 } else if (ExternalSymbolSDNode *ESSDN = 980 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) { 981 CallOpcode = PPC::CALLpcrel; 982 CallOperands.push_back(N->getOperand(1)); 983 } else { 984 // Copy the callee address into the CTR register. 985 SDOperand Callee = Select(N->getOperand(1)); 986 Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain); 987 988 // Copy the callee address into R12 on darwin. 989 SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32); 990 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, R12, Callee, Chain); 991 992 CallOperands.push_back(getI32Imm(20)); // Information to encode indcall 993 CallOperands.push_back(getI32Imm(0)); // Information to encode indcall 994 CallOperands.push_back(R12); 995 CallOpcode = PPC::CALLindirect; 996 } 997 998 unsigned GPR_idx = 0, FPR_idx = 0; 999 static const unsigned GPR[] = { 1000 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1001 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1002 }; 1003 static const unsigned FPR[] = { 1004 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1005 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1006 }; 1007 1008 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) 1009 if (N->getOperand(i).getOpcode() != ISD::UNDEF) { 1010 unsigned DestReg = 0; 1011 MVT::ValueType RegTy; 1012 if (N->getOperand(i).getValueType() == MVT::i32) { 1013 assert(GPR_idx < 8 && "Too many int args"); 1014 DestReg = GPR[GPR_idx++]; 1015 RegTy = MVT::i32; 1016 } else { 1017 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) && 1018 "Unpromoted integer arg?"); 1019 assert(FPR_idx < 13 && "Too many fp args"); 1020 DestReg = FPR[FPR_idx++]; 1021 RegTy = MVT::f64; // Even if this is really f32! 1022 } 1023 1024 SDOperand Reg = CurDAG->getRegister(DestReg, RegTy); 1025 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, Reg, 1026 Select(N->getOperand(i))); 1027 CallOperands.push_back(Reg); 1028 } 1029 1030 // Finally, once everything is in registers to pass to the call, emit the 1031 // call itself. 1032 CallOperands.push_back(Chain); 1033 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, CallOperands); 1034 1035 std::vector<SDOperand> CallResults; 1036 1037 // If the call has results, copy the values out of the ret val registers. 1038 switch (N->getValueType(0)) { 1039 default: assert(0 && "Unexpected ret value!"); 1040 case MVT::Other: break; 1041 case MVT::i32: 1042 if (N->getValueType(1) == MVT::i32) { 1043 Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32).getValue(1); 1044 CallResults.push_back(Chain.getValue(0)); 1045 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32).getValue(1); 1046 CallResults.push_back(Chain.getValue(0)); 1047 } else { 1048 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32).getValue(1); 1049 CallResults.push_back(Chain.getValue(0)); 1050 } 1051 break; 1052 case MVT::f32: 1053 case MVT::f64: 1054 Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, MVT::f64).getValue(1); 1055 CallResults.push_back(Chain.getValue(0)); 1056 break; 1057 } 1058 1059 CallResults.push_back(Chain); 1060 CurDAG->ReplaceAllUsesWith(N, CallResults); 1061 return CallResults[Op.ResNo]; 1062 } 1063 case ISD::RET: { 1064 SDOperand Chain = Select(N->getOperand(0)); // Token chain. 1065 1066 if (N->getNumOperands() > 1) { 1067 SDOperand Val = Select(N->getOperand(1)); 1068 switch (N->getOperand(1).getValueType()) { 1069 default: assert(0 && "Unknown return type!"); 1070 case MVT::f64: 1071 case MVT::f32: 1072 Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val); 1073 break; 1074 case MVT::i32: 1075 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val); 1076 break; 1077 } 1078 1079 if (N->getNumOperands() > 2) { 1080 assert(N->getOperand(1).getValueType() == MVT::i32 && 1081 N->getOperand(2).getValueType() == MVT::i32 && 1082 N->getNumOperands() == 2 && "Unknown two-register ret value!"); 1083 Val = Select(N->getOperand(2)); 1084 Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val); 1085 } 1086 } 1087 1088 // Finally, select this to a blr (return) instruction. 1089 CurDAG->SelectNodeTo(N, MVT::Other, PPC::BLR, Chain); 1090 break; 1091 } 1092 case ISD::BR: 1093 CurDAG->SelectNodeTo(N, MVT::Other, PPC::B, N->getOperand(1), 1094 Select(N->getOperand(0))); 1095 break; 1096 case ISD::BR_CC: 1097 case ISD::BRTWOWAY_CC: { 1098 SDOperand Chain = Select(N->getOperand(0)); 1099 MachineBasicBlock *Dest = 1100 cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock(); 1101 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1102 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); 1103 unsigned Opc = getBCCForSetCC(CC); 1104 1105 // If this is a two way branch, then grab the fallthrough basic block 1106 // argument and build a PowerPC branch pseudo-op, suitable for long branch 1107 // conversion if necessary by the branch selection pass. Otherwise, emit a 1108 // standard conditional branch. 1109 if (N->getOpcode() == ISD::BRTWOWAY_CC) { 1110 MachineBasicBlock *Fallthrough = 1111 cast<BasicBlockSDNode>(N->getOperand(5))->getBasicBlock(); 1112 SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other, 1113 CondCode, getI32Imm(Opc), 1114 N->getOperand(4), N->getOperand(5), 1115 Chain); 1116 CurDAG->SelectNodeTo(N, MVT::Other, PPC::B, N->getOperand(5), CB); 1117 } else { 1118 // Iterate to the next basic block 1119 ilist<MachineBasicBlock>::iterator It = BB; 1120 ++It; 1121 1122 // If the fallthrough path is off the end of the function, which would be 1123 // undefined behavior, set it to be the same as the current block because 1124 // we have nothing better to set it to, and leaving it alone will cause 1125 // the PowerPC Branch Selection pass to crash. 1126 if (It == BB->getParent()->end()) It = Dest; 1127 CurDAG->SelectNodeTo(N, MVT::Other, PPC::COND_BRANCH, CondCode, 1128 getI32Imm(Opc), N->getOperand(4), 1129 CurDAG->getBasicBlock(It), Chain); 1130 } 1131 break; 1132 } 1133 } 1134 return SDOperand(N, Op.ResNo); 1135} 1136 1137 1138/// createPPC32ISelDag - This pass converts a legalized DAG into a 1139/// PowerPC-specific DAG, ready for instruction scheduling. 1140/// 1141FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) { 1142 return new PPC32DAGToDAGISel(TM); 1143} 1144 1145