| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 3e84ad28d4d3ceee25771b1e30315c20b7608c39 |
|
22-Sep-2013 |
Tim Northover <tnorthover@apple.com> |
ISelDAG: spot chain cycles involving MachineNodes
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.
Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.
This should fix PR15840.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 53c86db25b5b4e163c68dc91c8ce1bc8180e6ff3 |
|
11-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPCDAGToDAGISel::isRunOfOnes should return false on zero
This fixes a bug (found by csmith) at -O0 where we attempt to create a RLWIMI
with an out-of-range operand. Most uses of the isRunOfOnes function are guarded
by a condition that the value is not zero. This was not true in two places, and
in both places a zero input would result in an out-of-rage MB value (= 32).
To fix this, isRunOfOnes returns false on a zero input (and I've remove one
now-redundant guard).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 965b20e39c7fd73846e9b6ed55ba90e032ae3b1b |
|
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Always use mfocrf if available
When accessing just a single CR register, it is always preferable to
use mfocrf instead of mfcr, if the former is available on the CPU.
Current code makes that distinction in many, but not all places
where a single CR register value is retrieved. One missing
location is PPCRegisterInfo::lowerCRSpilling.
To fix this and make this simpler in the future, this patch changes
the bulk of the back-end to always assume mfocrf is available and
simply generate it when needed.
On machines that actually do not support mfocrf, the instruction
is replaced by mfcr at the very end, in EmitInstruction.
This has the additional benefit that we no longer need the
MFCRpseud hack, since before EmitInstruction we always have
a MFOCRF instruction pattern, which already models data flow
as required.
The patch also adds the MFOCRF8 version of the instruction,
which was missing so far.
Except for the PPCRegisterInfo::lowerCRSpilling case, no change
in generated code intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f6b67dc7f8ed87443dc03856e789f42ba72ecaa8 |
|
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Remove dead code from PPCDAGToDAGISel::SelectSETCC
The subroutine getCRIdxForSetCC has a parameter "Other" and comment:
If this returns with Other != -1, then the returned comparison
is an or of two simpler comparisons.
However for at least the last five years this routine has never
returned a value of Other != -1; these cases are now handled
differently to begin with.
This patch removes the parameter and the code in SelectSETCC that
attempted to handle the Other != -1 case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c38c1d135cb9d617254c396c22949baca024dd35 |
|
01-Jul-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Index: test/CodeGen/PowerPC/reloc-align.ll
===================================================================
--- test/CodeGen/PowerPC/reloc-align.ll (revision 0)
+++ test/CodeGen/PowerPC/reloc-align.ll (revision 0)
@@ -0,0 +1,34 @@
+; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s
+
+; This test verifies that the peephole optimization of address accesses
+; does not produce a load or store with a relocation that can't be
+; satisfied for a given instruction encoding. Reduced from a test supplied
+; by Hal Finkel.
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.S1 = type { [8 x i8] }
+
+@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1
+
+; Function Attrs: nounwind readonly
+define signext i32 @main() #0 {
+entry:
+ %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*))
+; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l
+ ret i32 %call
+}
+
+; Function Attrs: nounwind readonly
+define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 {
+entry:
+ %0 = bitcast %struct.S1* %p_91 to i64*
+ %bf.load = load i64* %0, align 1
+ %bf.shl = shl i64 %bf.load, 26
+ %bf.ashr = ashr i64 %bf.shl, 54
+ %bf.cast = trunc i64 %bf.ashr to i32
+ ret i32 %bf.cast
+}
+
+attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
Index: lib/Target/PowerPC/PPCAsmPrinter.cpp
===================================================================
--- lib/Target/PowerPC/PPCAsmPrinter.cpp (revision 185327)
+++ lib/Target/PowerPC/PPCAsmPrinter.cpp (working copy)
@@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI
OutStreamer.EmitRawText(StringRef("\tmsync"));
return;
}
+ break;
+ case PPC::LD:
+ case PPC::STD:
+ case PPC::LWA: {
+ // Verify alignment is legal, so we don't create relocations
+ // that can't be supported.
+ // FIXME: This test is currently disabled for Darwin. The test
+ // suite shows a handful of test cases that fail this check for
+ // Darwin. Those need to be investigated before this sanity test
+ // can be enabled for those subtargets.
+ if (!Subtarget.isDarwin()) {
+ unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
+ const MachineOperand &MO = MI->getOperand(OpNum);
+ if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4)
+ llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
+ }
+ // Now process the instruction normally.
+ break;
}
+ }
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
OutStreamer.EmitInstruction(TmpInst);
Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp (revision 185327)
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp (working copy)
@@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() {
if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
SDLoc dl(GA);
const GlobalValue *GV = GA->getGlobal();
+ // We can't perform this optimization for data whose alignment
+ // is insufficient for the instruction encoding.
+ if (GV->getAlignment() < 4 &&
+ (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
+ StorageOpcode == PPC::LWA)) {
+ DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
+ continue;
+ }
ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
} else if (ConstantPoolSDNode *CP =
dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2c77a625b79908f6e1238890caae630d28c48bee |
|
28-Jun-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix a PPC rlwimi instruction-selection bug
Under certain (evidently rare) circumstances, this code used to convert OR(a,
AND(x, y)) into OR(a, x). This was incorrect.
While there, I've added a comment to the code immediately above.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185201 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 92cfa61c50d01307d658753f8d47f4e8555a6fa9 |
|
21-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Rename some more VK_PPC_ enums
This renames more VK_PPC_ enums, to make them more closely reflect
the @modifier string they represent. This also prepares for adding
a bunch of new VK_PPC_ enums in upcoming patches.
For consistency, some MO_ flags related to VK_PPC_ enums are
likewise renamed.
No change in behaviour.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184547 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c6af2432c802d241c8fffbe0371c023e6c58844e |
|
25-May-2013 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Replace Count{Leading,Trailing}Zeros_{32,64} with count{Leading,Trailing}Zeros.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 347a5079e18278803bc05b197d325b8580e95610 |
|
16-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use true offset value in "memrix" machine operands
This is the second part of the change to always return "true"
offset values from getPreIndexedAddressParts, tackling the
case of "memrix" type operands.
This is about instructions like LD/STD that only have a 14-bit
field to encode immediate offsets, which are implicitly extended
by two zero bits by the machine, so that in effect we can access
16-bit offsets as long as they are a multiple of 4.
The PowerPC back end currently handles such instructions by
carrying the 14-bit value (as it will get encoded into the
actual machine instructions) in the machine operand fields
for such instructions. This means that those values are
in fact not the true offset, but rather the offset divided
by 4 (and then truncated to an unsigned 14-bit value).
Like in the case fixed in r182012, this makes common code
operations on such offset values not work as expected.
Furthermore, there doesn't really appear to be any strong
reason why we should encode machine operands this way.
This patch therefore changes the encoding of "memrix" type
machine operands to simply contain the "true" offset value
as a signed immediate value, while enforcing the rules that
it must fit in a 16-bit signed value and must also be a
multiple of 4.
This change must be made simultaneously in all places that
access machine operands of this type. However, just about
all those changes make the code simpler; in many cases we
can now just share the same code for memri and memrix
operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b1fd3cd78f8acd21dbf514b75fef991827c343b6 |
|
15-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement PPC counter loops as a late IR-level pass
The old PPCCTRLoops pass, like the Hexagon pass version from which it was
derived, could only handle some simple loops in canonical form. We cannot
directly adapt the new Hexagon hardware loops pass, however, because the
Hexagon pass contains a fundamental assumption that non-constant-trip-count
loops will contain a guard, and this is not always true (the result being that
incorrect negative counts can be generated). With this commit, we replace the
pass with a late IR-level pass which makes use of SE to calculate the
backedge-taken counts and safely generate the loop-count expressions (including
any necessary max() parts). This IR level pass inserts custom intrinsics that
are lowered into the desired decrement-and-branch instructions.
The most fragile part of this new implementation is that interfering uses of
the counter register must be detected on the IR level (and, on PPC, this also
includes any indirect branches in addition to function calls). Also, to make
all of this work, we need a variant of the mtctr instruction that is marked
as having side effects. Without this, machine-code level CSE, DCE, etc.
illegally transform the resulting code. Hopefully, this can be improved
in the future.
This new pass is smaller than the original (and much smaller than the new
Hexagon hardware loops pass), and can handle many additional cases correctly.
In addition, the preheader-creation code has been copied from LoopSimplify, and
after we decide on where it belongs, this code will be refactored so that it
can be explicitly shared (making this implementation even smaller).
The new test-case files ctrloop-{le,lt,ne}.ll have been adapted from tests for
the new Hexagon pass. There are a few classes of loops that this pass does not
transform (noted by FIXMEs in the files), but these deficiencies can be
addressed within the SE infrastructure (thus helping many other passes as well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2 |
|
20-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
ArrayRefize getMachineNode(). No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2b0850b8305380244ec98e1b1c89aaf57adf3b09 |
|
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Remove ADDIL patterns.
The ADDI/ADDI8 patterns are currently duplicated into ADDIL/ADDI8L,
which describe the same instruction, except that they accept a
symbolLo[64] operand instead of a s16imm[64] operand.
This duplication confuses the asm parser, and it actually not really
needed, since symbolLo[64] already accepts immediate operands anyway.
So this commit removes the duplicate patterns.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 881a7154b9f9b85f6a8515e282cacdfc9df156cf |
|
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix swapped BasePtr and Offset in pre-inc memory addresses.
PPCTargetLowering::getPreIndexedAddressParts currently provides
the base part of a memory address in the offset result, and the
offset part in the base result. That swap is then undone again
when an MI instruction is generated (in PPCDAGToDAGISel::Select
for loads, and using .md Pat patterns for stores).
This patch reverts this double swap, to make common code and
back-end be in sync as to which part of the address is base
and which is offset.
To avoid performance regressions in certain cases, target code
now checks whether the choice of base register would be rejected
for pre-inc accesses by common code, and attempts to swap base
and offset again in such cases. (Overall, this means that now
pre-ice accesses are generated *more* frequently than before.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0301e79a1af665422f205fd367cdbd8e6164f324 |
|
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Tighten iaddroff ComplexPattern.
The iaddroff ComplexPattern is supposed to recognize displacement
expressions that have been processed by a SelectAddressRegImm,
which means it needs to accept TargetConstant and TargetGlobalAddress
nodes. Currently, it erroneously also accepts some other nodes,
in particular Constant and PPCISD::Lo.
While this problem is currently latent, it would cause wrong-code
bugs with a follow-on patch I'm about to commit, so this patch
tightens the ComplexPattern. The equivalent change is made in
PPCDAGToDAGISel::Select, where pre-inc load patterns are handled
(as opposed to store patterns, the loads are handled in C++ code
without making use of the .td ComplexPattern).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177732 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| cff0faa16a7d03951fba0aa279a2c8441c5718f8 |
|
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Remove the xaddroff ComplexPattern.
The xaddroff pattern is currently (mistakenly) used to recognize
the *base* register in pre-inc store patterns. This patch replaces
those uses by ptr_rc_nor0 (as is elsewhere done to match the base
register of an address), and removes the now unused ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 7ee74a663a3b4d4ee6b55d23362f347ed1d390c2 |
|
21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement builtin_{setjmp/longjmp} on PPC
This implements SJLJ lowering on PPC, making the Clang functions
__builtin_{setjmp/longjmp} functional on PPC platforms. The implementation
strategy is similar to that on X86, with the exception that a branch-and-link
variant is used to get the right jump address. Credit goes to Bill Schmidt for
suggesting the use of the unconditional bcl form (instead of the regular bl
instruction) to limit return-address-cache pollution.
Benchmarking the speed at -O3 of:
static jmp_buf env_sigill;
void foo() {
__builtin_longjmp(env_sigill,1);
}
main() {
...
for (int i = 0; i < c; ++i) {
if (__builtin_setjmp(env_sigill)) {
goto done;
} else {
foo();
}
done:;
}
...
}
vs. the same code using the libc setjmp/longjmp functions on a P7 shows that
this builtin implementation is ~4x faster with Altivec enabled and ~7.25x
faster with Altivec disabled. This comparison is somewhat unfair because the
libc version must also save/restore the VSX registers which we don't yet
support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 399eafb580f824d6df2d7392e1bc3e25ecb39f32 |
|
21-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Trivial cleanup
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175771 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 53b0b0e75480121e4e01a7a76e17909e92b1762a |
|
21-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Large code model support for PowerPC.
Large code model is identical to medium code model except that the
addis/addi sequence for "local" accesses is never used. All accesses
use the addis/ld sequence.
The coding changes are straightforward; most of the patch is taken up
with creating variants of the medium model tests for large model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0514595b9b20c9d807a3e31ba6bc270fb6c3f9e7 |
|
21-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Code review cleanup for r175697
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 421021157eda12453b4fea7ea853d8c472bd8532 |
|
21-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
PPCDAGToDAGISel::PostprocessISelDAG()
This patch implements the PPCDAGToDAGISel::PostprocessISelDAG virtual
method to perform post-selection peephole optimizations on the DAG
representation.
One optimization is implemented here: folds to clean up complex
addressing expressions for thread-local storage and medium code
model. It will also be useful for large code model sequences when
those are added later. I originally thought about doing this on the
MI representation prior to register assignment, but it's difficult to
do effective global dead code elimination at that point. DCE is
trivial on the DAG representation.
A typical example of a candidate code sequence in assembly:
addis 3, 2, globalvar@toc@ha
addi 3, 3, globalvar@toc@l
lwz 5, 0(3)
When the final instruction is a load or store with an immediate offset
of zero, the offset from the add-immediate can replace the zero,
provided the relocation information is carried along:
addis 3, 2, globalvar@toc@ha
lwz 5, globalvar@toc@l(3)
Since the addi can in general have multiple uses, we need to only
delete the instruction when the last use is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175697 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| abc402886e407e21d845cccc15723cffd6e2dc20 |
|
20-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Additional fixes for bug 15155.
This handles the cases where the 6-bit splat element is odd, converting
to a three-instruction sequence to add or subtract two splats. With this
fix, the XFAIL in test/CodeGen/PowerPC/vec_constants.ll is removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b34c79e4bbe5accbb54d0291e8bef5d2bfef32e4 |
|
20-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR15155: lost vadd/vsplat optimization.
During lowering of a BUILD_VECTOR, we look for opportunities to use a
vector splat. When the splatted value fits in 5 signed bits, a single
splat does the job. When it doesn't fit in 5 bits but does fit in 6,
and is an even value, we can splat on half the value and add the result
to itself.
This last optimization hasn't been working recently because of improved
constant folding. To circumvent this, create a pseudo VADD_SPLAT that
can be expanded during instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 96848dfc465c8c7f156a562c246803ebefcf21cf |
|
13-Feb-2013 |
Krzysztof Parzyszek <kparzysz@codeaurora.org> |
Add registration for PPC-specific passes to allow the IR to be dumped
via -print-after-all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175058 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 90230c84668269fbd53d163e398cd16486d5d414 |
|
19-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Sort all of the includes. Several files got checked in with mis-sorted
includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172891 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 5b7f9216c357f1cdf507f300f396b44cb982eb3f |
|
07-Jan-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch addresses bug 14678 by fixing two problems in medium code model
code generation. Variables addressed through a GlobalAlias were not being
handled, and variables with available_externally linkage were treated
incorrectly. The patch contains two new tests to verify the correct code
generation for these cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 1e18b861920ad2fd1a63e006cac61a4e274e5fdf |
|
13-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This is another cleanup patch for 64-bit PowerPC TLS processing. I had
some hackery in place that hid my poor use of TblGen, which I've now sorted
out and cleaned up. No change in observable behavior, so no new test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 349c2787cf9e174c8aa955bf8e3b09a405b2aece |
|
12-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements local-dynamic TLS model support for the 64-bit
PowerPC target. This is the last of the four models, so we now have
full TLS support.
This is mostly a straightforward extension of the general dynamic model.
I had to use an additional Chain operand to tie ADDIS_DTPREL_HA to the
register copy following ADDI_TLSLD_L; otherwise everything above the
ADDIS_DTPREL_HA appeared dead and was removed.
As before, there are new test cases to test the assembly generation, and
the relocations output during integrated assembly. The expected code
gen sequence can be read in test/CodeGen/PowerPC/tls-ld.ll.
There are a couple of things I think can be done more efficiently in the
overall TLS code, so there will likely be a clean-up patch forthcoming;
but for now I want to be sure the functionality is in place.
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 57ac1f458a754f30cf500410b438fb260f9b8fe5 |
|
11-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| d7802bf0ddcac16ee910105922492aee86a53e1b |
|
04-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch introduces initial-exec model support for thread-local storage
on 64-bit PowerPC ELF.
The patch includes code to handle external assembly and MC output with the
integrated assembler. It intentionally does not support the "old" JIT.
For the initial-exec TLS model, the ABI requires the following to calculate
the address of external thread-local variable x:
Code sequence Relocation Symbol
ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x
add 9,9,x@tls R_PPC64_TLS x
The register 9 is arbitrary here. The linker will replace x@got@tprel
with the offset relative to the thread pointer to the generated GOT
entry for symbol x. It will replace x@tls with the thread-pointer
register (13).
The two test cases verify correct assembly output and relocation output
as just described.
PowerPC-specific selection node variants are added for the two
instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted
when an initial-exec global variable is encountered by
PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to
machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo
that uses the same LDrs support added for medium code model's LDtocL,
with a different relocation type.
The rest of the processing is straightforward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 34a9d4b3b9b7858b729a1af67afa721c048fe5e7 |
|
27-Nov-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer. Additionally,
only TOC entries are addressed via the TOC pointer.
With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset. Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed. Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.
Consider a load of an external 4-byte integer. With small code model, the
compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
With medium model, it instead generates:
addis 3, 2, .LC1@toc@ha
ld 3, .LC1@toc@l(3)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer. Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits. Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.
Consider next a load of a function-scope static integer. For small code
model, the compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc test_fn_static.si[TC],test_fn_static.si
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
For medium code model, the compiler generates:
addis 3, 2, test_fn_static.si@toc@ha
addi 3, 3, test_fn_static.si@toc@l
lwz 4, 0(3)
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.
Note that it would be more efficient for the compiler to generate:
addis 3, 2, test_fn_static.si@toc@ha
lwz 4, test_fn_static.si@toc@l(3)
The current patch does not perform this optimization yet. This will be
addressed as a peephole optimization in a later patch.
For the moment, the default code model for 64-bit PowerPC will remain the
small code model. We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior. Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.
I've tested the regression suite and the application/benchmark test suite in
two ways: Once with the patch as submitted here, and once with additional
logic to force medium code model as the default. The tests all compile
cleanly, with one exception. The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers. It just so happens
that small code model was incredibly lucky, in that temporary values in
floating-point registers held the expected values needed by the external
library routine that was called incorrectly. My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."
Here are a few comments on how the patch works, since the selection code
can be difficult to follow:
The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses. These are expanded by SelectCodeCommon(). The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL. These new node types correspond naturally to
the sequences described above.
The addis/ld sequence is generated for the following cases:
* Jump table addresses
* Function addresses
* External global variables
* Tentative definitions of global variables (common linkage)
The addis/addi sequence is generated for the following cases:
* Constant pool entries
* File-scope static global variables
* Function-scope static variables
Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.
The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to
a "real" PowerPC instruction. When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).
I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL. So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.
Note that for LDtocL, we generate a new form of LD called LDrs. This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.
The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.
The above assumes use of an external assembler. For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 5f41fd685b6e82c3194be782566bbc438d697cc9 |
|
30-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: More support for Altivec compare operations
This patch adds more support for vector type comparisons using altivec.
It adds correct support for v16i8, v8i16, v4i32, and v4f32 vector
types for comparison operators ==, !=, >, >=, <, and <=.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167015 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| a5d0ab555384baa293b06686bec5a01fb9638ca3 |
|
10-Oct-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
The PowerPC VRSAVE register has been somewhat of an odd beast since
the Altivec extensions were introduced. Its use is optional, and
allows the compiler to communicate to the operating system which
vector registers should be saved and restored during a context switch.
In practice, this information is ignored by the various operating
systems using the SVR4 ABI; the kernel saves and restores the entire
register state. Setting the VRSAVE register is no longer performed by
the AIX XL compilers, the IBM i compilers, or by GCC on Power Linux
systems. It seems best to avoid this logic within LLVM as well.
This patch avoids generating code to update and restore VRSAVE for the
PowerPC SVR4 ABIs (32- and 64-bit). The code remains in place for the
Darwin ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 1c7d69bbe2de22f386ffd9ef4480f8a77be28130 |
|
08-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PR12716: PPC crashes on vector compare
Vector compare using altivec 'vcmpxxx' instructions have as third argument
a vector register instead of CR one, different from integer and float-point
compares. This leads to a failure in code generation, where 'SelectSETCC'
expects a DAG with a CR register and gets vector register instead.
This patch changes the behavior by just returning a DAG with the
vector compare instruction based on the type. The patch also adds a testcase
for all vector types llvm defines.
It also included a fix on signed 5-bits predicates printing, where
signed values were not handled correctly as signed (char are unsigned by
default for PowerPC). This generates 'vspltisw' (vector splat)
instruction with SIM out of range.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165419 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 94c22716d60ff5edf6a98a3c67e0faa001be1142 |
|
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 7e2c793a2b5c746344652b6579e958ee42fafdcc |
|
27-Sep-2012 |
Sylvestre Ledru <sylvestre@debian.org> |
Fix a typo 'iff' => 'if'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 97d047dec71cb37f31aac102cdc87b3dec0b1c46 |
|
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Optimize zext on PPC64.
The zeroextend IR instruction is lowered to an 'and' node with an immediate
mask operand, which in turn gets legalised to a sequence of ori's & ands.
This can be done more efficiently using the rldicl instruction.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2bbc9193b4a9b4e53ec114fd98a587a2917c365b |
|
21-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Treat TargetGlobalAddress as a constant for the purpose of matching pre-inc stores on PPC.
Thanks to Tobias von Koch for pointing out this problem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158932 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0fcdd8b2cc2b1bcf0aa64870d5269f9ac6dc76c0 |
|
20-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for generating reg+reg (indexed) pre-inc loads on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ac81cc3282750d724f824547bc519caec0a01bce |
|
19-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for generating reg+reg preinc stores on PPC.
PPC will now generate STWUX and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| bd5cafd9bbba2180e7179436fb29071201d5ea9f |
|
11-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Rename the PPC target feature gpul to mfocrf.
The PPC target feature gpul (IsGigaProcessor) was only used for one thing:
To enable the generation of the MFOCRF instruction. Furthermore, this
instruction is available on other PPC cores outside of the G5 line. This
feature now corresponds to the HasMFOCRF flag.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158323 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c909950c384e8234a7b3c5a76b7f79e3f7012ceb |
|
20-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155186 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 26c8dcc692fb2addd475446cfff24d6a4e958bca |
|
04-Apr-2012 |
Rafael Espindola <rafael.espindola@gmail.com> |
Always compute all the bits in ComputeMaskedBits.
This allows us to keep passing reduced masks to SimplifyDemandedBits, but
know about all the bits if SimplifyDemandedBits fails. This allows instcombine
to simplify cases like the one in the included testcase.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154011 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4d6ccb5f68cd7c6418a209f1fa4dbade569e4493 |
|
20-Jan-2012 |
David Blaikie <dblaikie@gmail.com> |
More dead code removal (using -Wunreachable-code)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 67724526447efae608ef3c8cf333cd797efa8737 |
|
08-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
MTCTR needs to be glued to BCTR so that CTR is not marked dead in MTCTR (another find by -verify-machineinstrs)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd |
|
07-Dec-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.
For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b95fc31aa2e5a0a0b9ee1909d1cb949577c5aa16 |
|
16-Nov-2011 |
Evan Cheng <evan.cheng@apple.com> |
Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144788 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 94b9550a32d189704a8eae55505edf62662c0534 |
|
26-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetAsmParser to MCTargetAsmParser and TargetAsmLexer to MCTargetAsmLexer; rename createAsmLexer to createMCAsmLexer and createAsmParser to createMCAsmParser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8e9d6720c3b62ad45bb97d43b47867a3097b433a |
|
20-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Don't apply on PPC64 the 32bit ADDIC optimizations as there's no overflow
with 32bit values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0c9b559bfd0b476c2dde787285a1195f3142c423 |
|
03-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.
- Check for MTCTR8 in addition to MTCTR when looking up a hazard.
- When lowering an indirect call use CTR8 when targeting 64bit.
- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.
The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0113e4e3f242fef41e6c733d1945f9950276cc9c |
|
19-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointless
piclabel operand. The operand in the tablegen definition doesn't actually turn
into an MI operand, so it just confuses anything checking the TargetInstrDesc
for the number of operands. It suffices to just have an implicit def of LR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b2581353011673d1241af2d7d334be46088248d8 |
|
09-Jan-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Fix the last virtual register enumerations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2da8bc8a5f7705ac131184cd247f48500da0d74e |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
Various bits of framework needed for precise machine-level selection
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.
Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.
Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.
Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.
ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.
ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122541 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6e8f4c404825b79f9b9176483653f1aa927dfbde |
|
24-Dec-2010 |
Andrew Trick <atrick@apple.com> |
whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122539 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f1b4eafbfec976f939ec0ea3e8acf91cef5363e3 |
|
21-Dec-2010 |
Chris Lattner <sabre@nondot.org> |
rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for
something that just glues two nodes together, even if it is
sometimes used for flags.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122310 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 52a261b3c1391c5fec399ddeb3fc6ee9541e8790 |
|
21-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 17aa68055beed6faa48ca3a995c5b6fdf5092fd4 |
|
04-Sep-2010 |
Chris Lattner <sabre@nondot.org> |
zap dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 5f07d5224ddc32f405d7e19de8e58e91ab2816bc |
|
20-May-2010 |
Dale Johannesen <dalej@apple.com> |
The PPC MFCR instruction implicitly uses all 8 of the CR
registers. Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
vreg = MCRF CR0
MFCR <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment). That avoids all problems. 7739628.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| d858e90f039f5fcdc2fa93035e911a5a9505cc50 |
|
17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.
SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.
And PIC16's AsmPrinter no longer uses TargetLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101635 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c7f3ace20c325521c68335a1689645b43b06ddf0 |
|
02-Apr-2010 |
Chris Lattner <sabre@nondot.org> |
use DebugLoc default ctor instead of DebugLoc::getUnknownLoc()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100214 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 34247a0f356edf45ae3ad9ce04e1f90a77c6dba7 |
|
29-Mar-2010 |
Benjamin Kramer <benny.kra@googlemail.com> |
Make isInt?? and isUint?? template specializations of the generic versions. This
makes calls a little bit more consistent and allows easy removal of the
specializations in the future. Convert all callers to the templated functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 7c306da505e2d7f64e160890b274a47fa0740962 |
|
02-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection. Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.
Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.
17 files changed, 114 insertions(+), 430 deletions(-)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f451cb870efcf9e0302d25ed05f4cac6bb494e42 |
|
10-Feb-2010 |
Dan Gohman <gohman@apple.com> |
Fix "the the" and similar typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| eeb3a00b84b7767d236ec8cf0619b9217fc247b9 |
|
05-Jan-2010 |
Dan Gohman <gohman@apple.com> |
Change SelectCode's argument from SDValue to SDNode *, to make it more
clear what information these functions are actually using.
This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92564 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b60d5194f52349b74914593919764fe8f4396bdf |
|
24-Nov-2009 |
Dale Johannesen <dalej@apple.com> |
Make capitalization of names starting "is" more consistent.
No functional change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 5ca124691bc81ed013593151c500d8104f7068dd |
|
20-Nov-2009 |
Dale Johannesen <dalej@apple.com> |
Remove an incorrect overaggressive optimization
(PPC specific).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89496 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 73bb251cd7a535fb93bb3a52eda61555fb253f41 |
|
05-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Remove uninteresting and confusing debug output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f5a86f45e75ec744c203270ffa03659eb0a220c1 |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6726b6d75a8b679068a58cb954ba97cf9d1690ba |
|
25-Oct-2009 |
Nick Lewycky <nicholas@mxc.ca> |
Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 602b0c8c17f458d2c80f2deb3c8e554d516ee316 |
|
25-Sep-2009 |
Dan Gohman <gohman@apple.com> |
Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 24f20e083280d979e8fa1bc88959ae9e8339ee99 |
|
22-Aug-2009 |
Devang Patel <dpatel@apple.com> |
Record variable debug info at ISel time directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 5cfd4ddece1b73a719830ae84eb74d491f87b9d5 |
|
18-Aug-2009 |
Dale Johannesen <dalej@apple.com> |
PowerPC inline asm was emitting two output operands
for a single "m" constraint; this is wrong because the
opcode of a load or store would have to change in parallel.
This patch makes it always compute addresses into a register,
which is correct but not as efficient as possible. 7144566.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| bd51c677390d8e13560cbf3ea972b95a5fbc1f9a |
|
15-Aug-2009 |
Dan Gohman <gohman@apple.com> |
Simplify a few more things, eliminating a few more dependencies on
"the current basic block".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79069 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 825b72b0571821bf2d378749f69d6c4cfb52d2f9 |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78713 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| e50ed30282bb5b4a9ed952580523f2dda16215ac |
|
11-Aug-2009 |
Owen Anderson <resistor@mac.com> |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ad2afc2a421a0e41603d5eee412d4d8c77e9bc1c |
|
31-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsage
shouldn't do AU.setPreservesCFG(), because even though CodeGen passes
don't modify the LLVM IR CFG, they may modify the MachineFunction CFG,
and passes like MachineLoop are registered with isCFGOnly set to true.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77691 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c5b19b21d84814d19692a6bbea11fbd135f4b094 |
|
31-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Revert r77654, it appears to be causing llvm-gcc bootstrap failures, and many
failures when building assorted projects with clang.
--- Reverse-merging r77654 into '.':
U include/llvm/CodeGen/Passes.h
U include/llvm/CodeGen/MachineFunctionPass.h
U include/llvm/CodeGen/MachineFunction.h
U include/llvm/CodeGen/LazyLiveness.h
U include/llvm/CodeGen/SelectionDAGISel.h
D include/llvm/CodeGen/MachineFunctionAnalysis.h
U include/llvm/Function.h
U lib/Target/CellSPU/SPUISelDAGToDAG.cpp
U lib/Target/PowerPC/PPCISelDAGToDAG.cpp
U lib/CodeGen/LLVMTargetMachine.cpp
U lib/CodeGen/MachineVerifier.cpp
U lib/CodeGen/MachineFunction.cpp
U lib/CodeGen/PrologEpilogInserter.cpp
U lib/CodeGen/MachineLoopInfo.cpp
U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
D lib/CodeGen/MachineFunctionAnalysis.cpp
D lib/CodeGen/MachineFunctionPass.cpp
U lib/CodeGen/LiveVariables.cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 933c762371fe8cc6e2ef5d00d6866f4924852fed |
|
31-Jul-2009 |
Dan Gohman <gohman@apple.com> |
Manage MachineFunctions with an analysis Pass instead of the Annotable
mechanism. To support this, make MachineFunctionPass a little more
complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c23197a26f34f559ea9797de51e187087c039c42 |
|
14-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in
!NDEBUG builds.
In NDEBUG builds location info and the message is off (it only prints
"UREACHABLE executed").
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c25e7581b9b8088910da31702d4ca21c4734c6d7 |
|
11-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
assert(0) -> LLVM_UNREACHABLE.
Make llvm_unreachable take an optional string, thus moving the cerr<< out of
line.
LLVM_UNREACHABLE is now a simple wrapper that makes the message go away for
NDEBUG builds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75379 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| dac237e18209b697a8ba122d0ddd9cad4dfba1f8 |
|
08-Jul-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement changes from Chris's feedback.
Finish converting lib/Target.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 9062d9a55b0b8b473b927d8b020e36990e147a58 |
|
17-Apr-2009 |
Chris Lattner <sabre@nondot.org> |
Fix some failures in targets on available_externally functions,
this fixes a crash on CodeGen/Generic/externally_available.ll
on ppc hosts. Thanks to Nicholas L for pointing this out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 536a2f1f8467a17f6d145bd83f25faae1f689839 |
|
13-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove refs to non-DebugLoc version of BuildMI from PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f902d246b69c972fa3e8f652b44d10abbb1f9355 |
|
12-Feb-2009 |
Chris Lattner <sabre@nondot.org> |
fix PR3538 for PPC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@64383 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f5f5dce897269885754fc79adeb809194da52942 |
|
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Eliminate remaining non-DebugLoc version of getTargetNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ed2eee63a6858312ed17582d8cb85a6856d8eb34 |
|
06-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Get rid of one more non-DebugLoc getNode and
its corresponding getTargetNode. Lots of
caller changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| a05dca4f9e051fad19fe9b5f6cce2715c1e5d505 |
|
05-Feb-2009 |
Dale Johannesen <dalej@apple.com> |
Remove non-DebugLoc forms of CopyToReg and CopyFromReg.
Adjust callers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63789 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c1a168a0fcbc7483a879e617e91824c4a7e6eece |
|
19-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix 80 col violations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62518 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 5fc742d5b2b647b3dce2c9ba943a2499d980c347 |
|
19-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Handle ISD::DECLARE with PIC relocation model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ee5c2b8ba2bd9670931705ca04a46052d534ade9 |
|
16-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PPC ISD::Declare isel and eliminate the need for PPCTargetLowering::LowerGlobalAddress to check if isVerifiedDebugInfoDesc() is true. Given the recent changes, it would falsely return true for a lot of GlobalAddressSDNode's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| fc54c552963545a81e4ea38e60460590afb2d5ae |
|
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Generalize the HazardRecognizer interface so that it can be used
to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62284 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 79ce276083ced01256a0eb7d80731e4948ca6e87 |
|
15-Jan-2009 |
Dan Gohman <gohman@apple.com> |
Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.
To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 53e4e4478c69c2c2115db833b54385117c764d14 |
|
07-Nov-2008 |
Dale Johannesen <dalej@apple.com> |
Make FP tests requiring two compares work on PPC (PR 642).
This is Chris' patch from the PR, modified to realize that
SETUGT/SETULT occur legitimately with integers, plus
two fixes in LegalizeDAG to pass a valid result type into
LegalizeSetCC. The argument of TLI.getSetCCResultType is
ignored on PPC, but I think I'm following usage elsewhere.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| cbb7ab259d08ac5aa5a4764b48628c4bcb5110c7 |
|
05-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Reintroduce a comment that was removed with the AddToISelQueue
changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58760 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8be6bbe5bfd50945ac6c5542e0f54a0924a5db8d |
|
05-Nov-2008 |
Dan Gohman <gohman@apple.com> |
Eliminate the ISel priority queue, which used the topological order for a
priority function. Instead, just iterate over the AllNodes list, which is
already in topological order. This eliminates a fair amount of bookkeeping,
and speeds up the isel phase by about 15% on many testcases.
The impact on most targets is that AddToISelQueue calls can be simply removed.
In the x86 target, there are two additional notable changes.
The rule-bending AND+SHIFT optimization in MatchAddress that creates new
pre-isel nodes during isel is now a little more verbose, but more robust.
Instead of either creating an invalid DAG or creating an invalid topological
sort, as it has historically done, it can now just insert the new nodes into
the node list at a position where they will be consistent with the topological
ordering.
Also, the address-matching code has logic that checked to see if a node was
"already selected". However, when a node is selected, it has all its uses
taken away via ReplaceAllUsesWith or equivalent, so it won't recieve any
further visits from MatchAddress. This code is now removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58748 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8ad4c00c00233acb8a3395098e2b575cc34de46b |
|
27-Oct-2008 |
David Greene <greened@obbligato.org> |
Have TableGen emit setSubgraphColor calls under control of a -gen-debug
flag. Then in a debugger developers can set breakpoints at these calls
to see waht is about to be selected and what the resulting subgraph
looks like. This really helps when debugging instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58278 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f522068412218cd14b2c2df74a3437717d255381 |
|
16-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Trim #includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| da8ac5fd9130b70b61be61e4819faa8d842d708f |
|
03-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Avoid creating two TargetLowering objects for each target.
Instead, just create one, and make sure everything that needs
it can access it. Previously most of the SelectionDAGISel
subclasses all had their own TargetLowering object, which was
redundant with the TargetLowering object in the TargetMachine
subclasses, except on Sparc, where SparcTargetMachine
didn't have a TargetLowering object. Change Sparc to work
more like the other targets here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f5aeb1a8e4cf272c7348376d185ef8d8267653e0 |
|
12-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6448d91ad1e5497fe2f7015d61b57cb5f3040879 |
|
04-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Clean up uses of TargetLowering::getTargetMachine.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55769 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 93c53e5583427ee567293a9a21c6c76fccf218ca |
|
31-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
fix a bunch of 80-col violations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ba36cb5242eb02b12b277f82b9efe497f7da4d7f |
|
28-Aug-2008 |
Gabor Greif <ggreif@gmail.com> |
erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55504 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f350b277f32d7d47f86c0e54f4aec4d470500618 |
|
23-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Move the point at which FastISel taps into the SelectionDAGISel
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.
Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.
To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ad3460c3c968e33c5b9a07104b9fe5a5c27ff55b |
|
21-Aug-2008 |
Dan Gohman <gohman@apple.com> |
Simplify SelectRoot's interface, and factor out some common code
from all targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55124 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 475871a144eb604ddaf37503397ba0941442e5fb |
|
27-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Rename SDOperand to SDValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54128 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| e8be6c63915e0389f1eef6b53c64300d13b2ce99 |
|
17-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add a new function, ReplaceAllUsesOfValuesWith, which handles bulk
replacement of multiple values. This is slightly more efficient
than doing multiple ReplaceAllUsesOfValueWith calls, and theoretically
could be optimized even further. However, an important property of this
new function is that it handles the case where the source value set and
destination value set overlap. This makes it feasible for isel to use
SelectNodeTo in many very common cases, which is advantageous because
SelectNodeTo avoids a temporary node and it doesn't require CSEMap
updates for users of values that don't change position.
Revamp MorphNodeTo, which is what does all the work of SelectNodeTo, to
handle operand lists more efficiently, and to correctly handle a number
of corner cases to which its new wider use exposes it.
This commit also includes a change to the encoding of post-isel opcodes
in SDNodes; now instead of being sandwiched between the target-independent
pre-isel opcodes and the target-dependent pre-isel opcodes, post-isel
opcodes are now represented as negative values. This makes it possible
to test if an opcode is pre-isel or post-isel without having to know
the size of the current target's post-isel instruction set.
These changes speed up llc overall by 3% and reduce memory usage by 10%
on the InstructionCombining.cpp testcase with -fast and -regalloc=local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 1002c0203450620594a85454c6a095ca94b87cb2 |
|
07-Jul-2008 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| db8d56b825efeb576d67b9dbe39d736d93306222 |
|
30-Jun-2008 |
Evan Cheng <evan.cheng@apple.com> |
Split scheduling from instruction selection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 83ec4b6711980242ef3c55a4fa36b2d7a39c1bfb |
|
06-Jun-2008 |
Duncan Sands <baldrick@free.fr> |
Wrap MVT::ValueType in a struct to get type safety
and better control the abstraction. Rename the type
to MVT. To update out-of-tree patches, the main
thing to do is to rename MVT::ValueType to MVT, and
rewrite expressions like MVT::getSizeInBits(VT) in
the form VT.getSizeInBits(). Use VT.getSimpleVT()
to extract a MVT::SimpleValueType for use in switch
statements (you will get an assert failure if VT is
an extended value type - these shouldn't exist after
type legalization).
This results in a small speedup of codegen and no
new testsuite failures (x86-64 linux).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@52044 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b3564aa8367fc38efdab0a812868f6f93b9d883e |
|
27-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Convert the last remaining users of the non-APInt form of
ComputeMaskedBits to use the APInt form, and remove the
non-APInt form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 7c1c261272b43f2a9397c3052819b92c53918075 |
|
20-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove bunch of gcc 4.3-related warnings from Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6f0d024a534af18d9e60b3ea757376cd8a3a980e |
|
10-Feb-2008 |
Dan Gohman <gohman@apple.com> |
Rename MRegisterInfo to TargetRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4e3f5a4e9c13f216856515e6f000881f2c850736 |
|
05-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Dwarf requires variable entries to be in the source order. Right now, since we are recording variable information at isel time this means parameters would appear in the reverse order. The short term fix is to issue recordVariable() at asm printing time instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46724 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| a844bdeab31ef04221e7ef59a8467893584cc14d |
|
02-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
SDIsel processes llvm.dbg.declare by recording the variable debug information descriptor and its corresponding stack frame index in MachineModuleInfo. This only works if the local variable is "homed" in the stack frame. It does not work for byval parameter, etc.
Added ISD::DECLARE node type to represent llvm.dbg.declare intrinsic. Now the intrinsic calls are lowered into a SDNode and lives on through out the codegen passes.
For now, since all the debugging information recording is done at isel time, when a ISD::DECLARE node is selected, it has the side effect of also recording the variable. This is a short term solution that should be fixed in time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46659 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b625f2f8960de32bc973092aaee8ac62863006fe |
|
30-Jan-2008 |
Dan Gohman <gohman@apple.com> |
Factor the addressing mode and the load/store VT out of LoadSDNode
and StoreSDNode into their common base class LSBaseSDNode. Member
functions getLoadedVT and getStoredVT are replaced with the common
getMemoryVT to simplify code that will handle both loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46538 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| fe39edde27147d4645aff715d5a7630fa07fa885 |
|
08-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Finally implement correct ordered comparisons for PPC, even though
the code generated is not wonderful. This turns a miscompilation into
a code quality bug (noted in the ppc readme). This fixes PR642, which
is over 2 years old (!). Nate, please review this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 749c6f6b5ed301c84aac562e414486549d7b98eb |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename TargetInstrDescriptor -> TargetInstrDesc.
Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 349c4952009525b27383e2120a6b3c998f39bd09 |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Move a bunch more accessors from TargetInstrInfo to TargetInstrDescriptor
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 69244300b8a0112efb44b6273ecea4ca6264b8cf |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Rename MachineInstr::getInstrDescriptor -> getDesc(), which reflects
that it is cheap and efficient to get.
Move a variety of predicates from TargetInstrInfo into
TargetInstrDescriptor, which makes it much easier to query a predicate
when you don't have TII around. Now you can use MI->getDesc()->isBranch()
instead of going through TII, and this is much more efficient anyway. Not
all of the predicates have been moved over yet.
Update old code that used MI->getInstrDescriptor()->Flags to use the
new predicates in many places.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45674 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 84bc5427d6883f73cfeae3da640acd011d35c006 |
|
31-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Rename SSARegMap -> MachineRegisterInfo in keeping with the idea
that "machine" classes are used to represent the current state of
the code being compiled. Given this expanded name, we can start
moving other stuff into it. For now, move the UsedPhysRegs and
LiveIn/LoveOuts vectors from MachineFunction into it.
Update all the clients to match.
This also reduces some needless #includes, such as MachineModuleInfo
from MachineFunction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45467 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 152b7e18748f7e06a93260f22cc9dac8eb3abee2 |
|
23-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with right callee-saved defs set for ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43248 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2bda17c92229e7116adf2edd3eea98c0a12f43cb |
|
29-Jun-2007 |
Evan Cheng <evan.cheng@apple.com> |
Prevent PPC::BCC first operand, the PRED number, from being isel'd into a LI instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37790 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ea859be53ca13a1547c4675549946b74dc3c6f41 |
|
22-Jun-2007 |
Dan Gohman <gohman@apple.com> |
Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| aa43e9f73b4ccd700530803803e074eff9b3dca5 |
|
02-Apr-2007 |
Chris Lattner <sabre@nondot.org> |
Fix a bug which caused us to never be able to use signed comparisons for
equality comparisons of a constant. This allows us to codegen the 'sintzero'
loop in PR1288 as:
LBB1_1: ;cond_next
li r4, 0
addi r2, r2, 1
stw r4, 0(r3)
addi r3, r3, 4
cmpwi cr0, r2, -1
bne cr0, LBB1_1 ;cond_next
instead of:
LBB1_1: ;cond_next
addi r2, r2, 1
li r4, 0
xoris r5, r2, 65535
stw r4, 0(r3)
addi r3, r3, 4
cmplwi cr0, r5, 65535
bne cr0, LBB1_1 ;cond_next
This implements CodeGen/PowerPC/compare-simm.ll, and also cuts 74
instructions out of kc++.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 95b2c7da5e83670881270c1cd231a240be0556d9 |
|
19-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
eliminate static ctors for Statistic objects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 78f97f3118c0d7fbebf4084e24689c596d5e4fb7 |
|
12-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Reduce number of instructions to load 64-bit constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 |
|
07-Dec-2006 |
Bill Wendling <isanbard@gmail.com> |
What should be the last unnecessary <iostream>s in the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ac0b6ae358944ae8b2b5a11dc08f52c3ed89f2da |
|
06-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
Detemplatize the Statistic class. The only type it is instantiated with
is 'unsigned'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c0f64ffab93d11fb27a3b8a0707b77400918a20e |
|
28-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead
of opcode and number of operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 18258c640466274c26e89016e361ec411ff78520 |
|
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
convert PPC::BCC to use the 'pred' operand instead of separate predicate
value and CR reg #. This requires swapping the order of these everywhere
that touches BCC and requires us to write custom matching logic for
PPCcondbranch :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 289c2d5f4566d8d7722e3934f4763d3df92886f3 |
|
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
rename PPC::COND_BRANCH to PPC::BCC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| df4ed6350b2a51f71c0980e86c9078f4046ea706 |
|
17-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
start using PPC predicates more consistently.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 74531e49ef97cc2bef8fc9c35963368fc63153cf |
|
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add patterns for ppc32 preinc stores. ppc64 next.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31775 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0851b4f3eda110cc21c8d4b59f0d55bc84d9d088 |
|
15-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri
addrmodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31757 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| d10434215da983b58389d2a0880dfcd2cd3b7f35 |
|
14-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
remove a ton of custom selection logic no longer needed
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 5b3bbc7cd7bff4275b94003d4bf1fa296c6a10d0 |
|
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
allow the offset of a preinc'd load to be the low-part of a global. This
produces this clever code:
_millisecs:
lis r2, ha16(_Time.1182)
lwzu r3, lo16(_Time.1182)(r2)
lwz r2, 4(r2)
addic r4, r2, 1
addze r3, r3
blr
instead of this:
_millisecs:
lis r2, ha16(_Time.1182)
la r3, lo16(_Time.1182)(r2)
lwz r2, lo16(_Time.1182)(r2)
lwz r3, 4(r3)
addic r4, r3, 1
addze r3, r2
blr
for:
long %millisecs() {
%tmp = load long* %Time.1182 ; <long> [#uses=1]
%tmp1 = add long %tmp, 1 ; <long> [#uses=1]
ret long %tmp1
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31673 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 94e509caeab08edb27849ea9be5dc80e74d95f38 |
|
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
implement preinc support for r+i loads on ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4eab71497d10622bd209c53f8e56152877ac5638 |
|
10-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add an initial cut at preinc loads for ppc32. This is broken for ppc64
(because the 64-bit reg target versions aren't implemented yet), doesn't
support r+r addr modes, and doesn't handle stores, but it works otherwise. :)
This is disabled unless -enable-ppc-preinc is passed to llc for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0d53826f3653a789cf1491c3c40a1f4a993992b6 |
|
08-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tblegen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| fc5b1ab94959879a91c34aee8859e652a50270d0 |
|
08-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Refactor all the addressing mode selection stuff into the isel lowering
class, where it can be used for preinc formation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31536 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 3ed469ccd7b028a030b550d84b7336d146f5d8fa |
|
02-Nov-2006 |
Reid Spencer <rspencer@reidspencer.com> |
For PR786:
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 1d75400e2ed5704c4c156782a94ee139d638bb1b |
|
31-Oct-2006 |
Chris Lattner <sabre@nondot.org> |
fix miscompilation of llvm.isunordered, where we branched on the opposite
condition. This fixes miscompilation of Olden/bh and many others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31301 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f42f133938545d4f5c249bcfef63db772ce8e942 |
|
22-Sep-2006 |
Nate Begeman <natebegeman@mac.com> |
Fold AND and ROTL more often
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 711762497c27357adc1edf8d4237c2770fa303bb |
|
20-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Improve PPC64 equality comparisons like PPC32 comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 3836dbd3bde1100c1df847a582784cf83d18daf6 |
|
20-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Two improvements:
1. Codegen this comparison:
if (X == 0x8000)
as:
cmplwi cr0, r3, 32768
bne cr0, LBB1_2 ;cond_next
instead of:
lis r2, 0
ori r2, r2, 32768
cmpw cr0, r3, r2
bne cr0, LBB1_2 ;cond_next
2. Codegen this comparison:
if (X == 0x12345678)
as:
xoris r2, r3, 4660
cmplwi cr0, r2, 22136
bne cr0, LBB1_2 ;cond_next
instead of:
lis r2, 4660
ori r2, r2, 22136
cmpw cr0, r3, r2
bne cr0, LBB1_2 ;cond_next
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30509 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| a4f0b3a084d120cfc5b5bb06f64b222f5cb72740 |
|
27-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
s|llvm/Support/Visibility.h|llvm/Support/Compiler.h|
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29911 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0b828e08f94459ac0046b864871d92fed4aaef7c |
|
27-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Do not use getTargetNode() and SelectNodeTo() which takes more than 3
SDOperand arguments. Use the variants which take an array and number instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29907 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 95514bae7309ffacfc0a79b267159dcfde2b7720 |
|
26-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
SelectNodeTo now returns a SDNode*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 9ade218533429146731213eacb7e12060e65ff58 |
|
26-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Select() no longer require Result operand by reference.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6da2f3268d12a9e64f2635dbb94b63e1c4142f59 |
|
26-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tblgen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29895 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ccbe2ec890ca41b8fd8c4e8ef0f7bcb42c2f69ec |
|
16-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Fix PowerPC/2006-08-15-SelectionCrash.ll and simplify selection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29715 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 64a752f7c7cf160f2887d0a16d5922359832c9c2 |
|
11-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tablegen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| bd564bfc63163e31f320c3da9749db70992dc35e |
|
08-Aug-2006 |
Chris Lattner <sabre@nondot.org> |
Start eliminating temporary vectors used to create DAG nodes. Instead, pass
in the start of an array and a count of operands where applicable. In many
cases, the number of operands is known, so this static array can be allocated
on the stack, avoiding the heap. In many other cases, a SmallVector can be
used, which has the same benefit in the common cases.
I updated a lot of code calling getNode that takes a vector, but ran out of
time. The rest of the code should be updated, and these methods should be
removed.
We should also do the same thing to eliminate the methods that take a
vector of MVT::ValueTypes.
It would be extra nice to convert the dagiselemitter to avoid creating vectors
for operands when calling getTargetNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2ef88a09b71f458ad415b35a1fb431c3d15d7eb1 |
|
08-Aug-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match tablegen isel changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2641cad180e94c0d26630d4ed455352f19be3d3e |
|
28-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove InFlightSet hack. No longer needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29373 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 33e9ad96c8506313cc263893e9915d0a3457fc82 |
|
27-Jul-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove NodeDepth
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2a41a98fb70923e2d6780220eb225ac0e8b4ff36 |
|
29-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
shrink libllvmgcc.dylib another 25K
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28971 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| cccef1c6fffa292c227a289d447f6b848ab56c62 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6b76b96c69334f3b6a2a895ff810ed047b4b75e5 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix ppc64 jump tables
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 529c233498c59a544b26b277f8fe30e6a80cc6f8 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix variable shadowing issue
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c08f902bb7bfcc8a97a4c7c9eb9187882dc2d6d7 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Implement a bunch of 64-bit cleanliness work. With this, treeadd builds (but
doesn't work right).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| cf0063171995c97ee52dfdf5d6bbbe090d2f5f03 |
|
10-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Work around a nasty tblgen bug where it doesn't add operands for varargs
nodes correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8e2a04e21dc8299bdaba4321a6e690712dab9617 |
|
25-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix build failure of povray
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28473 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 5d634ce466173f6fde49470fad125eb09532caeb |
|
25-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix Benchmarks/MallocBench/cfrac
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28471 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6a3d5a62f09d4093468525a07a0143cae0e9df41 |
|
25-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Assert if InflightSet is not cleared after instruction selecting a BB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| afe358e7d46da9d29ba02fbbf81bdfb4ac4a4520 |
|
24-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
Clear HandleMap and ReplaceMap after instruction selection. Or it may cause
non-deterministic behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28454 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c703a8fbf8653ac8302ae368391a4954c307ca2c |
|
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
Make PPC call lowering more aggressive, making the isel matching code simple
enough to be autogenerated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 9a2a497284e2233345c4bb9cdc1044d8395fddde |
|
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
Switch PPC over to a call-selection model where the lowering code creates
the copyto/fromregs instead of making the PPCISD::CALL selection code create
them. This vastly simplifies the selection code, and moves the ABI handling
parts into one place.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c04ba7a97d5ad599d92a1817de2d7c5fbb145810 |
|
17-May-2006 |
Chris Lattner <sabre@nondot.org> |
implement passing/returning vector regs to calls, at least non-varargs calls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28341 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0949ed5412c0902113aaefe106fed5b383fcc696 |
|
12-May-2006 |
Chris Lattner <sabre@nondot.org> |
Fix PowerPC/2006-05-12-rlwimi-crash.ll
Nate, please verify that if InsertMask is 0, rlwimi shouldn't be used.
This fixes the crash and causes no PPC testsuite regressions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4667f2cbad246beccfca5411a26add24d1007035 |
|
08-May-2006 |
Nate Begeman <natebegeman@mac.com> |
Fold more shifts into inserts, and update the README
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28168 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 93376b083e11f6dfcc678fe68abbc801eaa0a348 |
|
08-May-2006 |
Nate Begeman <natebegeman@mac.com> |
Update some stuff now that the new rlwimi code has gone in
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 77f361f5b3ac6ed080d6b0f401b62cd6e08614e5 |
|
07-May-2006 |
Nate Begeman <natebegeman@mac.com> |
New rlwimi implementation, which is superior to the old one. There are
still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same bitfield. More regression tests
to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 37efe6764568a3829fee26aba532283131d1a104 |
|
22-Apr-2006 |
Nate Begeman <natebegeman@mac.com> |
JumpTable support! What this represents is working asm and jit support for
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27947 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 710ff32983ca919fa0da14e077450b6a7654274f |
|
09-Apr-2006 |
Chris Lattner <sabre@nondot.org> |
Add VRRC select support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27543 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6d92caddc4aa5fc946b294259e00cc35536e61e8 |
|
26-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Codegen vector predicate compares.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 420736dc85c01702bb7bc40495f8a4be5e5f8a6c |
|
25-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
#include Intrinsics.h into all dag isels
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 54e869e18cd3d7c6ea6e2bce668c961b6f46f0ea |
|
24-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Like the comment says, prefer to use the implicit add done by [r+r] addressing
modes than emitting an explicit add and using a base of r0. This implements
Regression/CodeGen/PowerPC/mem-rr-addr-mode.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| e5ba580ab05b18eaa9fd4d36e31466e41f693ad9 |
|
22-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for "ri" addressing modes where the immediate is a 14-bit field
which is shifted left two bits before use. Instructions like STD use this
addressing mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26942 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8151914321a67b16d7183248593171e670a28e4c |
|
21-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
With Evan's latest tblgen patch, this code is obsolete, thanks Evan!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26917 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| d97964457e972cc0c0ae0e293f975112c3d65c46 |
|
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Handle constant addresses more efficiently, folding the low bits into the
disp field of the load/store if possible. This compiles
CodeGen/PowerPC/load-constant-addr.ll to:
_test:
lis r2, 2838
lfs f1, 26848(r2)
blr
instead of:
_test:
lis r2, 2838
ori r2, r2, 26848
lfs f1, 0(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26908 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| e376e00247aa957ebc8e83191853599ea4065eed |
|
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
reenable this hack, the tblgen version isn't quite ready
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| e63d746ef6e75d5461c9e29bcaf04b2755455c7f |
|
20-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use tblgen'd VECTOR_SHUFFLE selection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26900 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| dd4d2d0e4086905d85bc3011c2de78822d873d83 |
|
20-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Add support for generating vspltw, instead of a vperm instruction with a
constant pool load. This generates significantly nicer code for splats.
When tblgen gets bugfixed, we can remove the custom selection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26898 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 81e8097377529dc3b666f33bb525c49cfbac3f51 |
|
17-Mar-2006 |
Nate Begeman <natebegeman@mac.com> |
Remove BRTWOWAY*
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26814 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4bb189507281af0da8aff91743b5198acbf2398b |
|
16-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Save/restore VRSAVE once per function, not once per block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26793 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| a08610c8a534501bc4301c5037e883f180b19a99 |
|
14-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Fix an off by one error that caused PPC LLC failures last night.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26758 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c4c6257c1a154279bf10e9498d46d6c1793dbaa7 |
|
14-Mar-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added getTargetLowering() to TargetMachine. Refactored targets to support this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 1877ec9b02511e111998596b9ba9c3a2275d6a92 |
|
13-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
For functions that use vector registers, save VRSAVE, mark used
registers, and update it on entry to each function, then restore it on exit.
This compiles:
void func(vfloat *a, vfloat *b, vfloat *c) {
*a = *b * *c + *c;
}
to this:
_func:
mfspr r2, 256
oris r6, r2, 49152
mtspr 256, r6
lvx v0, 0, r5
lvx v1, 0, r4
vmaddfp v0, v1, v0, v0
stvx v0, 0, r3
mtspr 256, r2
blr
GCC produces this (which has additional stack accesses):
_func:
mfspr r0,256
stw r0,-4(r1)
oris r0,r0,0xc000
mtspr 256,r0
lvx v0,0,r5
lvx v1,0,r4
lwz r12,-4(r1)
vmaddfp v0,v0,v1,v0
stvx v0,0,r3
mtspr 256,r12
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 88d211f82304e53694ece666d4a2507b170e4582 |
|
12-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Several big changes:
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
type instead of a table in the .cpp file. Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
accurately.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b0d21ef20c29f4ea46d21b488f17feaa6a8760e1 |
|
08-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Change the interface for getting a target HazardRecognizer to be more clean.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c6644188208d4aee9a9d6c428710ec1f69837944 |
|
07-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Implement a very very simple hazard recognizer for LSU rejects and ctr set/read
flushes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0f6ab6ff97decd0150a7cdeda600216cd050d18a |
|
01-Mar-2006 |
Chris Lattner <sabre@nondot.org> |
Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26450 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| e5d8861126959d01cf847b6ef280dd9ef38d33cf |
|
24-Feb-2006 |
Chris Lattner <sabre@nondot.org> |
Implement selection of inline asm memory operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 551bf3f80058a026b6a128dffd5530019e1df1b9 |
|
17-Feb-2006 |
Nate Begeman <natebegeman@mac.com> |
kill ADD_PARTS & SUB_PARTS and replace them with fancy new ADDC, ADDE, SUBC
and SUBE nodes that actually expose what's going on and allow for
significant simplifications in the targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26255 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 298ebf2bd80ca415e58bbcbd9866ee58f167b620 |
|
16-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
If the false case is the current basic block, then this is a self loop.
We do not want to emit "Loop: ... brcond Out; br Loop", as it adds an extra
instruction in the loop. Instead, invert the condition and emit
"Loop: ... br!cond Loop; br Out.
Generalize the fix by moving it from PPCDAGToDAGISel to SelectionDAGLowering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 7e9b26fc73425ae215fbc9c8010cb53059a93b3a |
|
09-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Match getTargetNode() changes (now return SDNode* instead of SDOperand).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26085 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 34167215a8da717b21e44f1b834dc34d15279bf1 |
|
09-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Change Select() from
SDOperand Select(SDOperand N);
to
void Select(SDOperand &Result, SDOperand N);
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 7564e0b46d68abbd43a9910882568f4f9875af50 |
|
05-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Complex pattern isel code shouldn't select nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26010 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ba2f0a9ee53512ce840aca34281e126802a125d1 |
|
05-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use SelectRoot() as entry of any tblgen based isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25997 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 281b55ebeccd3f0d723888c1bb9ec6e476f708f1 |
|
28-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Use PPCISD::CALL instead of ISD::CALL
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25717 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2c2c6c61f100bc7c3df873b11203fcea1b5e18fe |
|
23-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Add explicit #includes of <iostream>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b22c08b8082cdf0026a8d429f37e8c16a1ca8caf |
|
15-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Use the default impl of DYNAMIC_STACKALLOC, allowing us to delete some code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25334 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| e699ef56186ec4aec379a98c646f263bdaa61624 |
|
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
these cases are autogenerated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25238 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 17e82d2858f0c003b7fcfaf7c025ca3d0aaa7a88 |
|
12-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c9a5ef524a9f461717bbf647b2d3da061aed720d |
|
05-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a compile crash building MultiSource/Applications/d with the new front-end.
The PPC backend was generating random shift counts in this case, due to an
uninitialized variable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25114 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 50fb3c498601a84e0d82d7bab3e28c820dd64598 |
|
24-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix one of the things in the todo file, and get a bit closer to folding
constant offsets from statics into the address arithmetic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24999 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 9e4dd9dfc97f3930f58ca6e47bebbd8eb5cdd8a1 |
|
20-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Pattern-match return. Includes gross hack!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 88276b887c426cf5d998b705a14663bfa38f8efd |
|
20-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Fix a couple of the FIXMEs, thanks to suggestion from Chris. This allows
us to load and store vectors directly at a pointer (offset of zero) by
using r0 as the base register. This also requires some asm printer work
to satisfy the darwin assembler.
For
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float> *%a
ret void
}
We now produce:
_foo:
lvx v0, 0, r3
vaddfp v0, v0, v0
stvx v0, 0, r3
blr
Instead of:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24872 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 7fd1edd32e9a6782dbcd00818bbdaf82f14284a1 |
|
20-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Convert load/store over to being pattern matched
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24871 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| cf198eca97af9a939decdc4866398bcc7b370ac6 |
|
18-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
This is handled by the autogen'd code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24834 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b5f8e62d712c94aa5324d8816f6ca2c47c5ce86b |
|
14-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove a now unused statistic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| a07da92624219599e6569460b3b56b49d60a4b46 |
|
14-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Use the new predicate support that Evan Cheng added to remove some code
from the DAGToDAG cpp file. This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.
Allows us to match:
void %foo(<4 x float> * %a) {
entry:
%tmp1 = load <4 x float> * %a;
%tmp2 = mul <4 x float> %tmp1, %tmp1
%tmp3 = add <4 x float> %tmp2, %tmp1
store <4 x float> %tmp3, <4 x float> *%a
ret void
}
As:
_foo:
li r2, 0
lvx v0, r2, r3
vmaddfp v0, v0, v0, v0
stvx v0, r2, r3
blr
Or, with llc -disable-excess-fp-precision,
_foo:
li r2, 0
lvx v0, r2, r3
vxor v1, v1, v1
vmaddfp v1, v0, v0, v1
vaddfp v0, v1, v0
stvx v0, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24719 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 28a6b02626c29b1fe9bb16c14c193549fab4cab8 |
|
10-Dec-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support for TargetConstantPool nodes to the dag isel emitter, and use
them in the PPC backend, to simplify some logic out of Select and
SelectAddr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24657 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 85961d5ec126bbc0c111d52dd7361d5159265ca5 |
|
06-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Silence another annoying GCC warning
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24627 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| bead6612a5591003b84df52d8656a1fee54db82c |
|
04-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
The basic fneg cases are already autogen'd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24592 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 937a79dbe3d71320e2bda8050541080f04412f14 |
|
04-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Autogen matching code for ADJCALLSTACK[UP|DOWN], thanks to Evan's tblgen
improvements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 60a4ab2d5c5e0e2647590882d77fe5d21d0c4990 |
|
04-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Finish moving uncond br over to .td file, remove from .cpp file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24590 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 05f56a529c0c9ac37b41c7472ceb7d2e95feff1e |
|
01-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Make sure these get added into the codegenmap when appropriate
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| db1cb2b3a15301c000c2bc5a99d5807510b2a456 |
|
01-Dec-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a regression caused by a patch earlier today
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c121e33e35b2e7292e6d99d8db91f73b84269e36 |
|
01-Dec-2005 |
Evan Cheng <evan.cheng@apple.com> |
Use a getCopyToReg() variant to generate a flaggy CopyToReg node.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 71d3d50b4a2182ce34d383c00a6f0e6231685cbf |
|
30-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
SelectNodeTo now returns N. Use it instead of return N directly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24549 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f43a3ca26d7bf431be5cdfb5963350a158e840af |
|
30-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
First chunk of actually generating vector code for packed types. These
changes allow us to generate the following code:
_foo:
li r2, 0
lvx v0, r2, r3
vaddfp v0, v0, v0
stvx v0, r2, r3
blr
for this llvm:
void %foo(<4 x float>* %a) {
entry:
%tmp1 = load <4 x float>* %a
%tmp2 = add <4 x float> %tmp1, %tmp1
store <4 x float> %tmp2, <4 x float>* %a
ret void
}
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24534 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 3eef4e377cad01d5fbef2d67a12fe96171e0d860 |
|
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Enable global address legalization, fixing a todo and allowing the removal
of some code. This exposes the implicit load from the stubs to the DAG, allowing
them to be optimized by the dag combiner. It also moves darwin specific stuff
out of the isel into the legalizer, and allows more to be moved to the .td file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24397 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4f0f86de5f183b09d07b17d1f940bd3e298abfcd |
|
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Teach the selector to fold lo(g) into load instruction immediate fields
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24396 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 860e8862c1fbd3b261da4a64a8c0096f9f373681 |
|
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Add an initial hack at legalizing GlobalAddress into the appropriate nodes
on Darwin to remove smarts from the isel. This is currently disabled by
default (uncomment setOperationAction(ISD::GlobalAddress to enable it).
tblgen needs to become smarter about tglobaladdr nodes and bigger patterns
needed to be added to the .td file. However, we can currently emit stuff like
this: :)
li r2, lo16(L_x$non_lazy_ptr)
lis r3, ha16(L_x$non_lazy_ptr)
lwzx r2, r3, r2
The obvious improvements will follow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24390 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2823b3e70ee7a5ed7482c45c503659a16a879a61 |
|
17-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
When lowering direct calls, lower them to use a targetglobaladress directly
instead of a globaladdress. This has no effect on the generated code at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24386 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 422b0cee7a32636303398d8788f98a59bf15381c |
|
16-Nov-2005 |
Nate Begeman <natebegeman@mac.com> |
Patch to clean up function call pseudos and support the BLA instruction,
which branches to an absolute address. This is required to support objc
direct dispatch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 7d7b96746c1264bd617783860a4a5ab289208fb0 |
|
29-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Don't emit "32" for unordered comparison
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ed048c067dc7bf342b2947b4de39e915dcbd2bf0 |
|
28-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
add a hack to get code with ordered comparisons working. This hack is
tracked as PR642
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6df2507121507c24d7155605c343e467e0106c07 |
|
28-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
add support for branch on ordered/unordered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24067 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6e61ca6fa709edc76594602da9c78c22ba2106ea |
|
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
autogen undef
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 9c73f095bb984fc9ae295904a8bcbcec19313a48 |
|
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Autogen fsel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| e6115b370ad518fa5dfbd33b216f147ab3703db7 |
|
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Autogen a few new ppc-specific nodes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8ecedbe2c391dd399b8b0205484f9053256f90d2 |
|
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
The dag isel generator generates this now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23984 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 99ea9da87242fed79fd617d79c6efb630a2db37d |
|
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Be a bit more paranoid about calling SelectNodeTo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 3393e80a06bbbfd9988deafae20c614ebbd5b8e6 |
|
25-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a couple of minor bugs. The first fixes povray, the second fixes things
if the dag combiner isn't run
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23981 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| dabb8291e840053a3d1a2a550d157e9c5c3c38c9 |
|
21-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Instead of aborting if not a case we can handle specially, break out and
let the generic code handle it. This fixes CodeGen/Generic/2005-10-21-longlonggtu.ll on ppc.
also, reindent this code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 405e3ecb563f21e7b4ee30f0de57821f3eb91219 |
|
21-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Invert the TargetLowering flag that controls divide by consant expansion.
Add a new flag to TargetLowering indicating if the target has really cheap
signed division by powers of two, make ppc use it. This will probably go
away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23853 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6957523b9ddc6e85aede47a107502043fd1a3b2d |
|
20-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Move the target constant divide optimization up into the dag combiner, so
that the nodes can be folded with other nodes, and we can not duplicate
code in every backend. Alpha will probably want this too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23835 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2d5aff761d32b7f4fddc982e9444d20af48f080b |
|
19-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Write patterns for the various shl and srl patterns that don't involve
doing something clever.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23824 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8be1fa5dc5c66d74581a4ec4fb9920e4535ec600 |
|
19-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Convert these cases to patterns
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23811 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8d948323942cf031e9d1c55bda2bff9d4db4cf42 |
|
19-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Woo, it kinda works. We now generate this atrociously bad, but correct,
code for long long foo(long long a, long long b) { return a + b; }
_foo:
or r2, r3, r3
or r3, r4, r4
or r4, r5, r5
or r5, r6, r6
rldicr r2, r2, 32, 31
rldicl r3, r3, 0, 32
rldicr r4, r4, 32, 31
rldicl r5, r5, 0, 32
or r2, r3, r2
or r3, r5, r4
add r4, r3, r2
rldicl r2, r4, 32, 32
or r4, r4, r4
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23809 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| da32c9eed6743c29d219a5c3cb13788853f18016 |
|
19-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Make a new reg class for 64 bit regs that aliases the 32 bit regs. This
will have to tide us over until we get real subreg support, but it prevents
the PrologEpilogInserter from spilling 8 byte GPRs on a G4 processor.
Add some initial support for TRUNCATE and ANY_EXTEND, but they don't
currently work due to issues with ScheduleDAG. Something wll have to be
figured out.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23803 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4a95945fa5aa431110f50092f4a45d24772a553b |
|
19-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
Add the ability to lower return instructions to TargetLowering. This
allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23802 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 1d9d7427c4a4e3c7bdcfd1f725447f355e509c20 |
|
18-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
First bits of 64 bit PowerPC stuff, currently disabled. A lot of this is
purely mechanical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23778 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 21e463b2bf864671a87ebe386cb100ef9349a540 |
|
16-Oct-2005 |
Nate Begeman <natebegeman@mac.com> |
More PPC32 -> PPC changes, as well as merging some classes that were
redundant after the change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23759 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4cb5a1b8967828447e525fb9f593953f5f928bdc |
|
16-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Remove some dead code: the ORI/ORIS cases are autogen'd. This makes
SelectIntImmediateExpr dead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 75c9f6737080af3e0c4a772f9c314f1a6fa2c91d |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
These instructions are now autogenerated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 651dea74f6a362d30bc61fd0b549da7707af5bf8 |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 16e71f2f70811c69c56052dd146324fe20e31db5 |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PPC32*.h to PPC*.h
This completes the grand PPC file renaming
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2668959b8879097db368aec7d76c455260abc75b |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Rename PowerPC*.h to PPC*.h
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4c7b43b43fdf943c7298718e15ab5d6dfe345be7 |
|
15-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Eliminate PowerPC.td and PPC32.td, consolidating them into PPC.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23738 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 3f31d4304cab178da207cbb795d72274ff7ecdd9 |
|
14-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
These are now autogenerated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 65a419a1045972729f91f82a378b7f4b7f6a2be5 |
|
09-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Disable formation of rlwinm instructions from SRA bases. This fixes
the 177.mesa failure from last night, and fixes the
CodeGen/PowerPC/2005-10-08-ArithmeticRotate.ll regression test I added.
If this code cannot be fixed, it should be removed for good, but I'll leave
it to Nate to decide its fate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23670 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| cf01a70550a25af39f979eb36a9e95aadcb12e00 |
|
08-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
When preselecting, favor things that have low depth to select first. This
is faster and uses less stack space. This reduces our stack requirement
enough to compile sixtrack, and though it's a hack, should be enough until
we switch to iterative isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23664 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6a16f6a14f344eb49a218b3fe159858e95d73e94 |
|
06-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Pull out Call, reducing stack frame size from 6032 bytes to 5184 bytes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23650 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 222adac30a642b5ea4a916eb3e97d8d95eb32bea |
|
06-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Pull out setcc, this reduces stack frame size from 7520 to 6032 bytes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2b63e4c5e2281ebc5575be3339d311d34f850b3b |
|
06-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Pull two more methods out, reducing stack frame size from 8224 -> 7520 bytes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23648 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| bd937b98f48cac17bd3d5102b2182943b97f8c28 |
|
06-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Add a recursive-iterative hybrid stage to attempt to reduce stack space, this
helps but not enough.
Start pulling cases out of PPC32DAGToDAGISel::Select. With GCC 4, this function
required 8512 bytes of stack space for each invocation (GCC 3 required less
than 700 bytes). Pulling this first function out gets us down to 8224. More
to come :(
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23647 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 43f07a4bbcac695c51def1d0bcd9c9ddb9e6a94d |
|
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
another solution to the fsel issue. Instead of having 4 variants, just force
the comparison to be 64-bits. This is fine because extensions from float
to double are free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23589 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 867940d1b738504a3186276542e94f088821c7f3 |
|
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
fsel can take a different FP type for the comparison and for the result. As such
split the FSEL family into 4 things instead of just two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23588 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ca0a4778a8e3036df7e51ed375cc867e6bf024bd |
|
02-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Minor tweak to the branch selector. When emitting a two-way branch, and if
we're in a single-mbb loop, make sure to emit the backwards branch as the
conditional branch instead of the uncond branch. For example, emit this:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
ble cr0, LBBl29_z__44
b LBBl29_z__48 *** NOT PART OF LOOP
Instead of:
LBBl29_z__44:
stw r9, 0(r15)
stw r9, 4(r15)
stw r9, 8(r15)
stw r9, 12(r15)
addi r15, r15, 16
addi r8, r8, 1
cmpw cr0, r8, r28
bgt cr0, LBBl29_z__48 *** PART OF LOOP!
b LBBl29_z__44
The former sequence has one fewer dispatch group for the loop body.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2c1760f636df659df8fcbc91055c0afd970f16c8 |
|
01-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23578 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 919c032fa4511468aadc6f50d6ed9c50890710b3 |
|
01-Oct-2005 |
Chris Lattner <sabre@nondot.org> |
Modify the ppc backend to use two register classes for FP: F8RC and F4RC.
These are used to represent float and double values, and the two regclasses
contain the same physical registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23577 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 242f2557cc242b2d132e5a3e6c3a98961a7e4349 |
|
01-Oct-2005 |
Jim Laskey <jlaskey@mac.com> |
Should be using flag and not chain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 237733e9335f4d2bb16a818ab184929e12fae407 |
|
30-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Remove code for patterns that are autogenerated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| d3d2cf52bbb776941bf8cb03d8732ff3f407cdea |
|
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Never rely on ReplaceAllUsesWith when selecting, use CodeGenMap instead.
ReplaceAllUsesWith does not replace scalars SDOperand floating around on
the stack, permitting things to be selected multiple times.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23515 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| d8ead9e25021d5c07b222f8550b621b4f31c874f |
|
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Autogen MUL, move FP cases together
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 88add100b3db715df4275c8ab408e6b51f28ff8f |
|
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
disentangle FP from INT versions of div/mul
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23511 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4a7de219b4bd776e5ae89f3cf5f6638afac4e5d3 |
|
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Use the autogenerated matcher for ADD/SUB
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 615c2d0920862ae7d4d766ee3da660ecf2197308 |
|
29-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Add FP versions of the binary operators, keeping the int and fp worlds seperate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 393e138f603d50a37425d625126491e314f3a9d0 |
|
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
All (xor *) cases are autogenerated now
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23497 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 1bd8b7b06e8031f1140570eb3bb240075b334687 |
|
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Implement PowerPC/eqv-andc-orc-nor.ll:EQV3
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| d135fa4fd6f70944a7944d8de2a4e625a240351b |
|
28-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
These nodes are all autogenerated
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23489 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 333bd835bd0d01f0e49b2f3d590be685a4959e16 |
|
27-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Make sure to clear the CodeGenMap after each basic block is selected to avoid
cross MBB pollution.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 303b555164e82139e0f88c183f1fc176fbb2d16c |
|
14-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
we don't need this proto any longer
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23342 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| af165385112037cb942e94ea562a67990b7d6220 |
|
14-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
move the #include for the generated code into the isel class body so we
can use/define class methods
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| e6ec9f20c9df6387b68874e4c49035d3c9c5527f |
|
10-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
PowerPC cannot truncstore i1 natively
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23304 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 19c0907ba1c11c81dc231cf7b4143fdaf03466e4 |
|
08-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Remove some cases handled by the generated portion of the isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23262 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c09eeec0ebc378644bafd04916e5efafa7d98152 |
|
07-Sep-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement i64<->fp using the fctidz/fcfid instructions on PowerPC when we
are allowed to generate 64-bit-only PowerPC instructions for 32 bit hosts,
such as the PowerPC 970.
This speeds up 189.lucas from 81.99 to 32.64 seconds.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23250 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6cd40d5888f905a3820d5d6c71e57cc0e02abb4a |
|
03-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
include the dag isel fragment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23239 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 25dae727f3b0c3511c17d7b7a8d476b1eed04f20 |
|
03-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Change the isel to not break out of the big giant switch. Instead, the
switch should never be exited, so its bottom is now unreachable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 75592e4137c3ae7800e1fb8736db28a65bb3c94d |
|
01-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Implement dynamic allocas correctly. In particular, because we were copying
directly out of R1 (without using a CopyFromReg, which uses a chain), multiple
allocas were getting CSE'd together, producing bogus code. For this:
int %foo(bool %X, int %A, int %B) {
br bool %X, label %T, label %F
F:
%G = alloca int
%H = alloca int
store int %A, int* %G
store int %B, int* %H
%R = load int* %G
ret int %R
T:
ret int 0
}
We were generating:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
li r2, 16
subf r2, r2, r1 ;; One alloca
or r1, r2, r2
or r3, r1, r1
or r1, r2, r2
or r2, r1, r1
stw r4, 0(r3)
stw r5, 0(r2)
lwz r3, 0(r3)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
Now we generate:
_foo:
stwu r1, -16(r1)
stw r31, 4(r1)
or r31, r1, r1
stw r1, 12(r31)
cmpwi cr0, r3, 0
bne cr0, .LBB_foo_2 ; T
.LBB_foo_1: ; F
or r2, r1, r1
li r3, 16
subf r2, r3, r2 ;; Alloca 1
or r1, r2, r2
or r2, r1, r1
or r6, r1, r1
subf r3, r3, r6 ;; Alloca 2
or r1, r3, r3
or r3, r1, r1
stw r4, 0(r2)
stw r5, 0(r3)
lwz r3, 0(r2)
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
.LBB_foo_2: ; T
li r3, 0
lwz r1, 12(r31)
lwz r31, 4(r31)
lwz r1, 0(r1)
blr
This fixes Povray and SPASS with the dag isel, the last two failing cases.
Tommorow we will hopefully turn it on by default! :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23190 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 393ecd6d2dbc844ae9e34fea34f15d914ec7c43c |
|
01-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a bug where we were useing HA to get the high part, which seems like it
could cause a miscompile. Fixing this didn't fix the two programs that fail
though. :(
This also changes the implementation to follow the pattern selector more
closely, causing us to select 0 to li instead of lis.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 50ff55c2c7909818165e51bbdc103a05b143dcb1 |
|
01-Sep-2005 |
Chris Lattner <sabre@nondot.org> |
Do not select the operands being passed into SelectCC. IT does this itself
and selecting early prevents folding immediates into the cmpw* instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23188 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f76053269ecc6c7bd3d0b1e90ebdd0cef1bb2bdc |
|
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Move FCTIWZ handling out of the instruction selectors and into legalization,
getting them out of the business of making stack slots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8346bb6c29cb6268c99117f6c86d6696b373d03e |
|
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Remove dead code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 99296ffd36662f0a64a2b4922e2b133b46222113 |
|
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add assert zext/sext to the dag isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 7a49fdcd1136c26d9c60b19c087ca9d578cc9834 |
|
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix 'ret long' to return the high and lo parts in the right registers. This
fixes crafty and probably others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23167 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| eb80fe8ff684121c8130db716fe4a7cb5ca3ac0d |
|
31-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
now that physregs can exist in the same dag with multiple types, remove some
ugly hacks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2ea0c66ae56b3254698c960f7b89b4eaed6bd83f |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix type mismatches when passing f32 values to calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 1368721d532d0d291a03bb3fff7f94805e5919b6 |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix some indentation (first hunks).
Remove code (last hunk) that miscompiled immediate and's, such as
and uint %tmp.30, 4294958079
into
andi. r8, r8, 56319
andis. r8, r8, 65535
instead of:
li r9, -9217
and r8, r8, r9
The first always generates zero.
This fixes espresso.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23155 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b551ba7661d5f8263979a5905fd3d1b9e5387e45 |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a problem Nate found where we swapped the operands of SHL/SHR_PARTS. This
fixes fourinarow
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23153 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 14b86c72a28a064373ac1670ed8ee62dab41e2f4 |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
codegen ADD_PARTS correctly: put the results in the right registers! This
fixes fhourstones
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23152 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2501d5e29c13f41fc15c0be5fece011db27c8ab3 |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add operands in the right order, fixing McCat/18-imp with the dag isel
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 31ce12f4f57db4375392e9129772773bed1bd4cc |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Make sure the selector emits register register copies with flag operands
linking them to calls when appropriate, this prevents the scheduler from
pulling these copies away from the call.
This fixes Ptrdist/yacr2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23143 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 15055733f85da5dc9a29e64cc1a2eeda38898f68 |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
The first operand to AND does not always have more than two operands. This
fixes MediaBench/toast with the dag selector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8f838720ad578349e7929b32fa9117aa317bb3a5 |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
emit FMR instructions to convert f64<->f32 instructions, so things like
STOREs, know the right type to store.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23139 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8bbcc20a9dccd258d5977d1d99520367b9ca9e7e |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
fix a crash in cfrac
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 9c2dece8e2daed25eb2db0f034e004a8342462e6 |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement DYNAMIC_STACKALLOC, wrap some long lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 7107c10501e62d2e3ed34b349585e616b8f6da3e |
|
30-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a dumb bug of mine where we were mishandling the PPC ABI (undef handling).
This fixes voronoi and bh in Olden, allowing all of olden to pass!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23133 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| efa6abcb957b9002a7e6708eb6f7885a93957ea7 |
|
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a bug the last patch exposed in treeadd among others
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2fef809b5b6a38d38aadc3399b5f7a78b537d092 |
|
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
A hack to fix a problem folding immedaites. This fixes Olden/power.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2a06a5ef363382479e74cae2d39f139e11f40225 |
|
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix order of operands for copytoreg node when emitting calls. This fixes
Olden/msFix order of operands for copytoreg node when emitting calls. This fixes
Olden/mstt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b9efd14568531fc5d6150a4471c1bfb6cb98928f |
|
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add operands in the correct order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23123 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c8a89a1fcb900b8204c166fc4e9f5c3a1a3937de |
|
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a bug in FP_EXTEND, implement FP_TO_SINT
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 528f58e813ec4929a7997afbf121eb54e8bacf4c |
|
29-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
fix an assertion failure in treeadd
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23120 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8a2d3ca7dff8f37ee0f1fc0042f47c194045183d |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement SELECT_CC fully for the DAG->DAG isel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0bbea954331b8f08afa5b094dfb0841829c70eaa |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Make fsel emission work with both the pattern and dag-dag selectors, by
giving it a non-instruction opcode. The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 13794f5d01317d76ec698b43bdf1c35eea57eae5 |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement the fold for:
bool %test(int %X, int %Y) {
%C = setne int %X, 0
ret bool %C
}
to:
_test:
addic r2, r3, -1
subfe r3, r2, r3
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 52987f4f6531ffcfcc61b1319f5219f3704d426b |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Changes to adjust to new ReplaceAllUsesWith syntax. Change FP_EXTEND to
just return its input, instead of emitting an explicit copy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23088 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 28b9be300cab414da42f9da016a2e89b797b9ddc |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
now that fsel is formed during legalization, this code is dead
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 5839bf2b3bd22689d9dd0e9de66c2dce71d130ae |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Change ConstantPoolSDNode to actually hold the Constant itself instead of
putting it into the constant pool. This allows the isel machinery to
create constants that it will end up deciding are not needed, without them
ending up in the resultant function constant pool.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23081 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 95e0682a4276fb9f5978039dc4bae675bdf66ee3 |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix some warnings in an optimized build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23080 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2bb06cdf27905cf95bd39e4120f1ad57c68ac73e |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a huge annoyance: SelectNodeTo took types before the opcode unlike
every other SD API. Fix it to take the opcode before the types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23079 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| bb22df31d9cf329deca2cf770885869bd7c26c94 |
|
26-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
SUBFIC produces two results, not one.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23073 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6660cd65cf79f4be328f072526580471bde5fe22 |
|
26-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement SHL_PARTS and SRL_PARTS
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23072 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b20c318df02c19a5ba4ba89c76f2bf3daae64ad2 |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Emit the lo/hi parts in the right order :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23068 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| a9317ed361847c96989664b84ae8502a783a9956 |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement support for 64-bit add/sub, fix a broken assertion for 64-bit
return. Allow the udiv breaker-upper to work with any non-zero constant
operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23066 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 047b952e298352fe6feffedf02e359601133f465 |
|
26-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Finish implementing SDIV/UDIV by copying over the majik constant code from
ISelPattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23062 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 957fcfbd8935b2973376167861a53e4a9220aefc |
|
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement setcc correctly for G5 and non-G5 systems
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23060 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 64906a06b3d1cafec41c6b562f0f8130724decf6 |
|
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement setcc on the G5. We're still missing the non-g5 specific bits, but
they will come later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23059 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 8784a23075f8544f78f8b46cfd10457c1109d433 |
|
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add support for sdiv by 2^k and -2^k. Producing code like:
_test:
srawi r2, r3, 2
addze r3, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23052 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 34e17052a77e1a52cae58b2f6d203c663af97ece |
|
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement support for taking the address of constant pool indices, which
is used by the int -> FP code among other things. This gets
2005-05-12-Int64ToFP past that failure, to dying on lack of support for add_parts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2fe76e58eb734a09ec08ea006a32700572ffc0ca |
|
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add support for FP constants, fixing UnitTests/2004-02-02-NegativeZero
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23038 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| e28e40a2733c5d9a568d1569e2d1d8461716b22d |
|
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fully implement frame index, so that we can pass the address of alloca's
around to functions and stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23036 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 89532c7db03543402dd5376172b87233575beb44 |
|
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement unconditional branches, fixing UnitTests/2003-05-02-DependentPHI.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ed7956bfe4bbe9445cbf0a74299f714ffe4fd7a4 |
|
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a broken assertion
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23032 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2b54400f085391a247dd2c3fffc9f36f7b2dc867 |
|
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Split IMPLICIT_DEF into IMPLICIT_DEF_GPR and IMPLICIT_DEF_FP, so that the
instructions take a consistent reg class. Implement ISD::UNDEF in the dag->dag
selector to generate this, fixing UnitTests/2003-07-06-IntOverflow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23028 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| fb0c964364ba9f2c54ea28e0b7f404e18f7327b4 |
|
25-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
implement support for calls
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23026 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c6b0717a6caa32fc9029fd1337af4bf0d07b54e8 |
|
24-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Remove unused statistic
Prefer 'neg X' to 'subfic 0, X' since neg does not set XER[CA]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| a2590c5b3eaa24002e3f83f146f0e5b6c95a89c8 |
|
24-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Add callseq_begin/end support
Call stil not supported yet
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f7f22555053a8992b2f97db77a62458ff8a69d7f |
|
22-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22963 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| ddf3e7dfd791f7cdbcd1bb5feb168067b5b9c16d |
|
22-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix compilation of:
float %test2(float* %P) {
%Q = load float* %P
%R = add float %Q, %Q
ret float %R
}
By returning the right result.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22961 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 9944b76cfe74981d2c41c8237d25267ba0c467c7 |
|
22-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement most of load support. There is still a bug though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22959 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 2fbb4579d6d6bbde8387283b78307c2ea477a312 |
|
21-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Implement selection for branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22951 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 4416f1a0a5b17906b9e162209fd506656a2e07d8 |
|
20-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
add support for global address, including PIC support.
This REALLY should be lowered by the legalizer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22941 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 7e65997c43cc91a5e6eaa0f460b844ef1b5d2fb1 |
|
19-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Fix a typeo, no wonder all tokenfactor edges were the same!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 02b88a4586704f34bc65afca3348453eae69d1d3 |
|
19-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
ISD::OR, and it's accompanying SelectBitfieldInsert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| c15ed447f494c77a76c24661893e22192ebb2103 |
|
19-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0bc04231c0aa42fbb50cc4fd531340d35b60450d |
|
18-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
Move this to the emitter
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22877 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| d607c12e8e8533028a66c9f533007c6c32a64cef |
|
18-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
After selecting the instructions for a basic block, emit the instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| f5fac3b4a6c41a2ea344a24c5f9ecc51cfca0723 |
|
18-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
remove some unused stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22866 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| a69404781344c4aee05935ee921bbf2844911bc0 |
|
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Improve ISD::Constant codegen.
Now for int foo() { return -1; } we generate:
_foo:
li r3, -1
blr
instead of
_foo:
lis r2, -1
ori r3, r2, 65535
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22864 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| cffc32b6e2e1edc2ddd62a00159f7008ee765d3e |
|
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add support for ISD::AND, and its various optimized forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22857 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 131a8805205c383f67b3b6a11777401e27b90371 |
|
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Maintain consistency in negating things
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22855 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 0f3257a3302b60c128a667db6736e81335316c1e |
|
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement XOR, remove a broken sign_extend_inreg case
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22854 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 305a1c75cfcc1b2e97c2bccebd42a70d99e7d127 |
|
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add a bunch more simple nodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22851 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 6a7d61179c77c23dc22cd64e5e922bc40ed234e9 |
|
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add a couple more nodes that are easy to handle
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| b5a0668d43582297e19d03df34e0a0c09a1f6c45 |
|
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Be fruitful and multiply!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22849 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| 26653500bbbc21cd1c2d12ecc433fa439536b657 |
|
18-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Teach the DAG->DAG ISel about FNEG, and how it can be used to invert
several of the PowerPC opcodes that come in both negated and non-negated
forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|
| a5a91b10262f5bbcf1ec8abd1e66ee6585d3f00e |
|
17-Aug-2005 |
Chris Lattner <sabre@nondot.org> |
initial hack at a dag->dag instruction selector. This is obviously woefully
incomplete, but it is a start. It handles basic argument/retval stuff, immediates,
add and sub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22836 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
|