PPCISelDAGToDAG.cpp revision 7c1c261272b43f2a9397c3052819b92c53918075
1//===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines a pattern matching instruction selector for PowerPC, 11// converting from a legalized dag to a PPC dag. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "ppc-codegen" 16#include "PPC.h" 17#include "PPCPredicates.h" 18#include "PPCTargetMachine.h" 19#include "PPCISelLowering.h" 20#include "PPCHazardRecognizers.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/SelectionDAGISel.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Constants.h" 28#include "llvm/GlobalValue.h" 29#include "llvm/Intrinsics.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/Support/MathExtras.h" 32#include "llvm/Support/Compiler.h" 33#include <queue> 34#include <set> 35using namespace llvm; 36 37namespace { 38 //===--------------------------------------------------------------------===// 39 /// PPCDAGToDAGISel - PPC specific code to select PPC machine 40 /// instructions for SelectionDAG operations. 41 /// 42 class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel { 43 PPCTargetMachine &TM; 44 PPCTargetLowering PPCLowering; 45 const PPCSubtarget &PPCSubTarget; 46 unsigned GlobalBaseReg; 47 public: 48 PPCDAGToDAGISel(PPCTargetMachine &tm) 49 : SelectionDAGISel(PPCLowering), TM(tm), 50 PPCLowering(*TM.getTargetLowering()), 51 PPCSubTarget(*TM.getSubtargetImpl()) {} 52 53 virtual bool runOnFunction(Function &Fn) { 54 // Make sure we re-emit a set of the global base reg if necessary 55 GlobalBaseReg = 0; 56 SelectionDAGISel::runOnFunction(Fn); 57 58 InsertVRSaveCode(Fn); 59 return true; 60 } 61 62 /// getI32Imm - Return a target constant with the specified value, of type 63 /// i32. 64 inline SDOperand getI32Imm(unsigned Imm) { 65 return CurDAG->getTargetConstant(Imm, MVT::i32); 66 } 67 68 /// getI64Imm - Return a target constant with the specified value, of type 69 /// i64. 70 inline SDOperand getI64Imm(uint64_t Imm) { 71 return CurDAG->getTargetConstant(Imm, MVT::i64); 72 } 73 74 /// getSmallIPtrImm - Return a target constant of pointer type. 75 inline SDOperand getSmallIPtrImm(unsigned Imm) { 76 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); 77 } 78 79 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s 80 /// with any number of 0s on either side. The 1s are allowed to wrap from 81 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 82 /// 0x0F0F0000 is not, since all 1s are not contiguous. 83 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME); 84 85 86 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a 87 /// rotate and mask opcode and mask operation. 88 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask, 89 unsigned &SH, unsigned &MB, unsigned &ME); 90 91 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC 92 /// base register. Return the virtual register that holds this value. 93 SDNode *getGlobalBaseReg(); 94 95 // Select - Convert the specified operand from a target-independent to a 96 // target-specific node if it hasn't already been changed. 97 SDNode *Select(SDOperand Op); 98 99 SDNode *SelectBitfieldInsert(SDNode *N); 100 101 /// SelectCC - Select a comparison of the specified values with the 102 /// specified condition code, returning the CR# of the expression. 103 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC); 104 105 /// SelectAddrImm - Returns true if the address N can be represented by 106 /// a base register plus a signed 16-bit displacement [r+imm]. 107 bool SelectAddrImm(SDOperand Op, SDOperand N, SDOperand &Disp, 108 SDOperand &Base) { 109 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG); 110 } 111 112 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc 113 /// immediate field. Because preinc imms have already been validated, just 114 /// accept it. 115 bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand &Out) const { 116 Out = N; 117 return true; 118 } 119 120 /// SelectAddrIdx - Given the specified addressed, check to see if it can be 121 /// represented as an indexed [r+r] operation. Returns false if it can 122 /// be represented by [r+imm], which are preferred. 123 bool SelectAddrIdx(SDOperand Op, SDOperand N, SDOperand &Base, 124 SDOperand &Index) { 125 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG); 126 } 127 128 /// SelectAddrIdxOnly - Given the specified addressed, force it to be 129 /// represented as an indexed [r+r] operation. 130 bool SelectAddrIdxOnly(SDOperand Op, SDOperand N, SDOperand &Base, 131 SDOperand &Index) { 132 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG); 133 } 134 135 /// SelectAddrImmShift - Returns true if the address N can be represented by 136 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable 137 /// for use by STD and friends. 138 bool SelectAddrImmShift(SDOperand Op, SDOperand N, SDOperand &Disp, 139 SDOperand &Base) { 140 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG); 141 } 142 143 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 144 /// inline asm expressions. 145 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op, 146 char ConstraintCode, 147 std::vector<SDOperand> &OutOps, 148 SelectionDAG &DAG) { 149 SDOperand Op0, Op1; 150 switch (ConstraintCode) { 151 default: return true; 152 case 'm': // memory 153 if (!SelectAddrIdx(Op, Op, Op0, Op1)) 154 SelectAddrImm(Op, Op, Op0, Op1); 155 break; 156 case 'o': // offsetable 157 if (!SelectAddrImm(Op, Op, Op0, Op1)) { 158 Op0 = Op; 159 AddToISelQueue(Op0); // r+0. 160 Op1 = getSmallIPtrImm(0); 161 } 162 break; 163 case 'v': // not offsetable 164 SelectAddrIdxOnly(Op, Op, Op0, Op1); 165 break; 166 } 167 168 OutOps.push_back(Op0); 169 OutOps.push_back(Op1); 170 return false; 171 } 172 173 SDOperand BuildSDIVSequence(SDNode *N); 174 SDOperand BuildUDIVSequence(SDNode *N); 175 176 /// InstructionSelectBasicBlock - This callback is invoked by 177 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 178 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 179 180 void InsertVRSaveCode(Function &Fn); 181 182 virtual const char *getPassName() const { 183 return "PowerPC DAG->DAG Pattern Instruction Selection"; 184 } 185 186 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 187 /// this target when scheduling the DAG. 188 virtual HazardRecognizer *CreateTargetHazardRecognizer() { 189 // Should use subtarget info to pick the right hazard recognizer. For 190 // now, always return a PPC970 recognizer. 191 const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo(); 192 assert(II && "No InstrInfo?"); 193 return new PPCHazardRecognizer970(*II); 194 } 195 196// Include the pieces autogenerated from the target description. 197#include "PPCGenDAGISel.inc" 198 199private: 200 SDNode *SelectSETCC(SDOperand Op); 201 }; 202} 203 204/// InstructionSelectBasicBlock - This callback is invoked by 205/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 206void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 207 DEBUG(BB->dump()); 208 209 // Select target instructions for the DAG. 210 DAG.setRoot(SelectRoot(DAG.getRoot())); 211 DAG.RemoveDeadNodes(); 212 213 // Emit machine code to BB. 214 ScheduleAndEmitDAG(DAG); 215} 216 217/// InsertVRSaveCode - Once the entire function has been instruction selected, 218/// all virtual registers are created and all machine instructions are built, 219/// check to see if we need to save/restore VRSAVE. If so, do it. 220void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { 221 // Check to see if this function uses vector registers, which means we have to 222 // save and restore the VRSAVE register and update it with the regs we use. 223 // 224 // In this case, there will be virtual registers of vector type type created 225 // by the scheduler. Detect them now. 226 MachineFunction &Fn = MachineFunction::get(&F); 227 bool HasVectorVReg = false; 228 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 229 e = RegInfo->getLastVirtReg()+1; i != e; ++i) 230 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) { 231 HasVectorVReg = true; 232 break; 233 } 234 if (!HasVectorVReg) return; // nothing to do. 235 236 // If we have a vector register, we want to emit code into the entry and exit 237 // blocks to save and restore the VRSAVE register. We do this here (instead 238 // of marking all vector instructions as clobbering VRSAVE) for two reasons: 239 // 240 // 1. This (trivially) reduces the load on the register allocator, by not 241 // having to represent the live range of the VRSAVE register. 242 // 2. This (more significantly) allows us to create a temporary virtual 243 // register to hold the saved VRSAVE value, allowing this temporary to be 244 // register allocated, instead of forcing it to be spilled to the stack. 245 246 // Create two vregs - one to hold the VRSAVE register that is live-in to the 247 // function and one for the value after having bits or'd into it. 248 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 249 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 250 251 const TargetInstrInfo &TII = *TM.getInstrInfo(); 252 MachineBasicBlock &EntryBB = *Fn.begin(); 253 // Emit the following code into the entry block: 254 // InVRSAVE = MFVRSAVE 255 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE 256 // MTVRSAVE UpdatedVRSAVE 257 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point 258 BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE); 259 BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE), 260 UpdatedVRSAVE).addReg(InVRSAVE); 261 BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); 262 263 // Find all return blocks, outputting a restore in each epilog. 264 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 265 if (!BB->empty() && BB->back().getDesc().isReturn()) { 266 IP = BB->end(); --IP; 267 268 // Skip over all terminator instructions, which are part of the return 269 // sequence. 270 MachineBasicBlock::iterator I2 = IP; 271 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator()) 272 IP = I2; 273 274 // Emit: MTVRSAVE InVRSave 275 BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); 276 } 277 } 278} 279 280 281/// getGlobalBaseReg - Output the instructions required to put the 282/// base address to use for accessing globals into a register. 283/// 284SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { 285 if (!GlobalBaseReg) { 286 const TargetInstrInfo &TII = *TM.getInstrInfo(); 287 // Insert the set of GlobalBaseReg into the first MBB of the function 288 MachineBasicBlock &FirstMBB = BB->getParent()->front(); 289 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 290 291 if (PPCLowering.getPointerTy() == MVT::i32) { 292 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass); 293 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR); 294 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg); 295 } else { 296 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass); 297 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8); 298 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg); 299 } 300 } 301 return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val; 302} 303 304/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 305/// or 64-bit immediate, and if the value can be accurately represented as a 306/// sign extension from a 16-bit value. If so, this returns true and the 307/// immediate. 308static bool isIntS16Immediate(SDNode *N, short &Imm) { 309 if (N->getOpcode() != ISD::Constant) 310 return false; 311 312 Imm = (short)cast<ConstantSDNode>(N)->getValue(); 313 if (N->getValueType(0) == MVT::i32) 314 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue(); 315 else 316 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue(); 317} 318 319static bool isIntS16Immediate(SDOperand Op, short &Imm) { 320 return isIntS16Immediate(Op.Val, Imm); 321} 322 323 324/// isInt32Immediate - This method tests to see if the node is a 32-bit constant 325/// operand. If so Imm will receive the 32-bit value. 326static bool isInt32Immediate(SDNode *N, unsigned &Imm) { 327 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 328 Imm = cast<ConstantSDNode>(N)->getValue(); 329 return true; 330 } 331 return false; 332} 333 334/// isInt64Immediate - This method tests to see if the node is a 64-bit constant 335/// operand. If so Imm will receive the 64-bit value. 336static bool isInt64Immediate(SDNode *N, uint64_t &Imm) { 337 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 338 Imm = cast<ConstantSDNode>(N)->getValue(); 339 return true; 340 } 341 return false; 342} 343 344// isInt32Immediate - This method tests to see if a constant operand. 345// If so Imm will receive the 32 bit value. 346static bool isInt32Immediate(SDOperand N, unsigned &Imm) { 347 return isInt32Immediate(N.Val, Imm); 348} 349 350 351// isOpcWithIntImmediate - This method tests to see if the node is a specific 352// opcode and that it has a immediate integer right operand. 353// If so Imm will receive the 32 bit value. 354static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { 355 return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm); 356} 357 358bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { 359 if (isShiftedMask_32(Val)) { 360 // look for the first non-zero bit 361 MB = CountLeadingZeros_32(Val); 362 // look for the first zero bit after the run of ones 363 ME = CountLeadingZeros_32((Val - 1) ^ Val); 364 return true; 365 } else { 366 Val = ~Val; // invert mask 367 if (isShiftedMask_32(Val)) { 368 // effectively look for the first zero bit 369 ME = CountLeadingZeros_32(Val) - 1; 370 // effectively look for the first one bit after the run of zeros 371 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1; 372 return true; 373 } 374 } 375 // no run present 376 return false; 377} 378 379bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, 380 bool IsShiftMask, unsigned &SH, 381 unsigned &MB, unsigned &ME) { 382 // Don't even go down this path for i64, since different logic will be 383 // necessary for rldicl/rldicr/rldimi. 384 if (N->getValueType(0) != MVT::i32) 385 return false; 386 387 unsigned Shift = 32; 388 unsigned Indeterminant = ~0; // bit mask marking indeterminant results 389 unsigned Opcode = N->getOpcode(); 390 if (N->getNumOperands() != 2 || 391 !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31)) 392 return false; 393 394 if (Opcode == ISD::SHL) { 395 // apply shift left to mask if it comes first 396 if (IsShiftMask) Mask = Mask << Shift; 397 // determine which bits are made indeterminant by shift 398 Indeterminant = ~(0xFFFFFFFFu << Shift); 399 } else if (Opcode == ISD::SRL) { 400 // apply shift right to mask if it comes first 401 if (IsShiftMask) Mask = Mask >> Shift; 402 // determine which bits are made indeterminant by shift 403 Indeterminant = ~(0xFFFFFFFFu >> Shift); 404 // adjust for the left rotate 405 Shift = 32 - Shift; 406 } else if (Opcode == ISD::ROTL) { 407 Indeterminant = 0; 408 } else { 409 return false; 410 } 411 412 // if the mask doesn't intersect any Indeterminant bits 413 if (Mask && !(Mask & Indeterminant)) { 414 SH = Shift & 31; 415 // make sure the mask is still a mask (wrap arounds may not be) 416 return isRunOfOnes(Mask, MB, ME); 417 } 418 return false; 419} 420 421/// SelectBitfieldInsert - turn an or of two masked values into 422/// the rotate left word immediate then mask insert (rlwimi) instruction. 423SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { 424 SDOperand Op0 = N->getOperand(0); 425 SDOperand Op1 = N->getOperand(1); 426 427 uint64_t LKZ, LKO, RKZ, RKO; 428 CurDAG->ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO); 429 CurDAG->ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO); 430 431 unsigned TargetMask = LKZ; 432 unsigned InsertMask = RKZ; 433 434 if ((TargetMask | InsertMask) == 0xFFFFFFFF) { 435 unsigned Op0Opc = Op0.getOpcode(); 436 unsigned Op1Opc = Op1.getOpcode(); 437 unsigned Value, SH = 0; 438 TargetMask = ~TargetMask; 439 InsertMask = ~InsertMask; 440 441 // If the LHS has a foldable shift and the RHS does not, then swap it to the 442 // RHS so that we can fold the shift into the insert. 443 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { 444 if (Op0.getOperand(0).getOpcode() == ISD::SHL || 445 Op0.getOperand(0).getOpcode() == ISD::SRL) { 446 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 447 Op1.getOperand(0).getOpcode() != ISD::SRL) { 448 std::swap(Op0, Op1); 449 std::swap(Op0Opc, Op1Opc); 450 std::swap(TargetMask, InsertMask); 451 } 452 } 453 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { 454 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 455 Op1.getOperand(0).getOpcode() != ISD::SRL) { 456 std::swap(Op0, Op1); 457 std::swap(Op0Opc, Op1Opc); 458 std::swap(TargetMask, InsertMask); 459 } 460 } 461 462 unsigned MB, ME; 463 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) { 464 SDOperand Tmp1, Tmp2, Tmp3; 465 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF; 466 467 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && 468 isInt32Immediate(Op1.getOperand(1), Value)) { 469 Op1 = Op1.getOperand(0); 470 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; 471 } 472 if (Op1Opc == ISD::AND) { 473 unsigned SHOpc = Op1.getOperand(0).getOpcode(); 474 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && 475 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) { 476 Op1 = Op1.getOperand(0).getOperand(0); 477 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; 478 } else { 479 Op1 = Op1.getOperand(0); 480 } 481 } 482 483 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0; 484 AddToISelQueue(Tmp3); 485 AddToISelQueue(Op1); 486 SH &= 31; 487 SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB), 488 getI32Imm(ME) }; 489 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5); 490 } 491 } 492 return 0; 493} 494 495/// SelectCC - Select a comparison of the specified values with the specified 496/// condition code, returning the CR# of the expression. 497SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, 498 ISD::CondCode CC) { 499 // Always select the LHS. 500 AddToISelQueue(LHS); 501 unsigned Opc; 502 503 if (LHS.getValueType() == MVT::i32) { 504 unsigned Imm; 505 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 506 if (isInt32Immediate(RHS, Imm)) { 507 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 508 if (isUInt16(Imm)) 509 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, 510 getI32Imm(Imm & 0xFFFF)), 0); 511 // If this is a 16-bit signed immediate, fold it. 512 if (isInt16((int)Imm)) 513 return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, 514 getI32Imm(Imm & 0xFFFF)), 0); 515 516 // For non-equality comparisons, the default code would materialize the 517 // constant, then compare against it, like this: 518 // lis r2, 4660 519 // ori r2, r2, 22136 520 // cmpw cr0, r3, r2 521 // Since we are just comparing for equality, we can emit this instead: 522 // xoris r0,r3,0x1234 523 // cmplwi cr0,r0,0x5678 524 // beq cr0,L6 525 SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS, 526 getI32Imm(Imm >> 16)), 0); 527 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor, 528 getI32Imm(Imm & 0xFFFF)), 0); 529 } 530 Opc = PPC::CMPLW; 531 } else if (ISD::isUnsignedIntSetCC(CC)) { 532 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm)) 533 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS, 534 getI32Imm(Imm & 0xFFFF)), 0); 535 Opc = PPC::CMPLW; 536 } else { 537 short SImm; 538 if (isIntS16Immediate(RHS, SImm)) 539 return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS, 540 getI32Imm((int)SImm & 0xFFFF)), 541 0); 542 Opc = PPC::CMPW; 543 } 544 } else if (LHS.getValueType() == MVT::i64) { 545 uint64_t Imm; 546 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 547 if (isInt64Immediate(RHS.Val, Imm)) { 548 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 549 if (isUInt16(Imm)) 550 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, 551 getI32Imm(Imm & 0xFFFF)), 0); 552 // If this is a 16-bit signed immediate, fold it. 553 if (isInt16(Imm)) 554 return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, 555 getI32Imm(Imm & 0xFFFF)), 0); 556 557 // For non-equality comparisons, the default code would materialize the 558 // constant, then compare against it, like this: 559 // lis r2, 4660 560 // ori r2, r2, 22136 561 // cmpd cr0, r3, r2 562 // Since we are just comparing for equality, we can emit this instead: 563 // xoris r0,r3,0x1234 564 // cmpldi cr0,r0,0x5678 565 // beq cr0,L6 566 if (isUInt32(Imm)) { 567 SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS, 568 getI64Imm(Imm >> 16)), 0); 569 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor, 570 getI64Imm(Imm & 0xFFFF)), 0); 571 } 572 } 573 Opc = PPC::CMPLD; 574 } else if (ISD::isUnsignedIntSetCC(CC)) { 575 if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm)) 576 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS, 577 getI64Imm(Imm & 0xFFFF)), 0); 578 Opc = PPC::CMPLD; 579 } else { 580 short SImm; 581 if (isIntS16Immediate(RHS, SImm)) 582 return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS, 583 getI64Imm(SImm & 0xFFFF)), 584 0); 585 Opc = PPC::CMPD; 586 } 587 } else if (LHS.getValueType() == MVT::f32) { 588 Opc = PPC::FCMPUS; 589 } else { 590 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); 591 Opc = PPC::FCMPUD; 592 } 593 AddToISelQueue(RHS); 594 return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0); 595} 596 597static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { 598 switch (CC) { 599 default: assert(0 && "Unknown condition!"); abort(); 600 case ISD::SETOEQ: // FIXME: This is incorrect see PR642. 601 case ISD::SETUEQ: 602 case ISD::SETEQ: return PPC::PRED_EQ; 603 case ISD::SETONE: // FIXME: This is incorrect see PR642. 604 case ISD::SETUNE: 605 case ISD::SETNE: return PPC::PRED_NE; 606 case ISD::SETOLT: // FIXME: This is incorrect see PR642. 607 case ISD::SETULT: 608 case ISD::SETLT: return PPC::PRED_LT; 609 case ISD::SETOLE: // FIXME: This is incorrect see PR642. 610 case ISD::SETULE: 611 case ISD::SETLE: return PPC::PRED_LE; 612 case ISD::SETOGT: // FIXME: This is incorrect see PR642. 613 case ISD::SETUGT: 614 case ISD::SETGT: return PPC::PRED_GT; 615 case ISD::SETOGE: // FIXME: This is incorrect see PR642. 616 case ISD::SETUGE: 617 case ISD::SETGE: return PPC::PRED_GE; 618 619 case ISD::SETO: return PPC::PRED_NU; 620 case ISD::SETUO: return PPC::PRED_UN; 621 } 622} 623 624/// getCRIdxForSetCC - Return the index of the condition register field 625/// associated with the SetCC condition, and whether or not the field is 626/// treated as inverted. That is, lt = 0; ge = 0 inverted. 627/// 628/// If this returns with Other != -1, then the returned comparison is an or of 629/// two simpler comparisons. In this case, Invert is guaranteed to be false. 630static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { 631 Invert = false; 632 Other = -1; 633 switch (CC) { 634 default: assert(0 && "Unknown condition!"); abort(); 635 case ISD::SETOLT: 636 case ISD::SETLT: return 0; // Bit #0 = SETOLT 637 case ISD::SETOGT: 638 case ISD::SETGT: return 1; // Bit #1 = SETOGT 639 case ISD::SETOEQ: 640 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ 641 case ISD::SETUO: return 3; // Bit #3 = SETUO 642 case ISD::SETUGE: 643 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE 644 case ISD::SETULE: 645 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE 646 case ISD::SETUNE: 647 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE 648 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO 649 case ISD::SETULT: Other = 0; return 3; // SETOLT | SETUO 650 case ISD::SETUGT: Other = 1; return 3; // SETOGT | SETUO 651 case ISD::SETUEQ: Other = 2; return 3; // SETOEQ | SETUO 652 case ISD::SETOGE: Other = 1; return 2; // SETOGT | SETOEQ 653 case ISD::SETOLE: Other = 0; return 2; // SETOLT | SETOEQ 654 case ISD::SETONE: Other = 0; return 1; // SETOLT | SETOGT 655 } 656 return 0; 657} 658 659SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) { 660 SDNode *N = Op.Val; 661 unsigned Imm; 662 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 663 if (isInt32Immediate(N->getOperand(1), Imm)) { 664 // We can codegen setcc op, imm very efficiently compared to a brcond. 665 // Check for those cases here. 666 // setcc op, 0 667 if (Imm == 0) { 668 SDOperand Op = N->getOperand(0); 669 AddToISelQueue(Op); 670 switch (CC) { 671 default: break; 672 case ISD::SETEQ: { 673 Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0); 674 SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; 675 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 676 } 677 case ISD::SETNE: { 678 SDOperand AD = 679 SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, 680 Op, getI32Imm(~0U)), 0); 681 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, 682 AD.getValue(1)); 683 } 684 case ISD::SETLT: { 685 SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 686 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 687 } 688 case ISD::SETGT: { 689 SDOperand T = 690 SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0); 691 T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0); 692 SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 693 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 694 } 695 } 696 } else if (Imm == ~0U) { // setcc op, -1 697 SDOperand Op = N->getOperand(0); 698 AddToISelQueue(Op); 699 switch (CC) { 700 default: break; 701 case ISD::SETEQ: 702 Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, 703 Op, getI32Imm(1)), 0); 704 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 705 SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32, 706 getI32Imm(0)), 0), 707 Op.getValue(1)); 708 case ISD::SETNE: { 709 Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0); 710 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, 711 Op, getI32Imm(~0U)); 712 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0), 713 Op, SDOperand(AD, 1)); 714 } 715 case ISD::SETLT: { 716 SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, 717 getI32Imm(1)), 0); 718 SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, 719 Op), 0); 720 SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 721 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 722 } 723 case ISD::SETGT: { 724 SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 725 Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); 726 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, 727 getI32Imm(1)); 728 } 729 } 730 } 731 } 732 733 bool Inv; 734 int OtherCondIdx; 735 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx); 736 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); 737 SDOperand IntCR; 738 739 // Force the ccreg into CR7. 740 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); 741 742 SDOperand InFlag(0, 0); // Null incoming flag value. 743 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg, 744 InFlag).getValue(1); 745 746 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1) 747 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, 748 CCReg), 0); 749 else 750 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0); 751 752 SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), 753 getI32Imm(31), getI32Imm(31) }; 754 if (OtherCondIdx == -1 && !Inv) 755 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 756 757 // Get the specified bit. 758 SDOperand Tmp = 759 SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); 760 if (Inv) { 761 assert(OtherCondIdx == -1 && "Can't have split plus negation"); 762 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); 763 } 764 765 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT. 766 // We already got the bit for the first part of the comparison (e.g. SETULE). 767 768 // Get the other bit of the comparison. 769 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31); 770 SDOperand OtherCond = 771 SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0); 772 773 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond); 774} 775 776 777// Select - Convert the specified operand from a target-independent to a 778// target-specific node if it hasn't already been changed. 779SDNode *PPCDAGToDAGISel::Select(SDOperand Op) { 780 SDNode *N = Op.Val; 781 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 782 N->getOpcode() < PPCISD::FIRST_NUMBER) 783 return NULL; // Already selected. 784 785 switch (N->getOpcode()) { 786 default: break; 787 788 case ISD::Constant: { 789 if (N->getValueType(0) == MVT::i64) { 790 // Get 64 bit value. 791 int64_t Imm = cast<ConstantSDNode>(N)->getValue(); 792 // Assume no remaining bits. 793 unsigned Remainder = 0; 794 // Assume no shift required. 795 unsigned Shift = 0; 796 797 // If it can't be represented as a 32 bit value. 798 if (!isInt32(Imm)) { 799 Shift = CountTrailingZeros_64(Imm); 800 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift; 801 802 // If the shifted value fits 32 bits. 803 if (isInt32(ImmSh)) { 804 // Go with the shifted value. 805 Imm = ImmSh; 806 } else { 807 // Still stuck with a 64 bit value. 808 Remainder = Imm; 809 Shift = 32; 810 Imm >>= 32; 811 } 812 } 813 814 // Intermediate operand. 815 SDNode *Result; 816 817 // Handle first 32 bits. 818 unsigned Lo = Imm & 0xFFFF; 819 unsigned Hi = (Imm >> 16) & 0xFFFF; 820 821 // Simple value. 822 if (isInt16(Imm)) { 823 // Just the Lo bits. 824 Result = CurDAG->getTargetNode(PPC::LI8, MVT::i64, getI32Imm(Lo)); 825 } else if (Lo) { 826 // Handle the Hi bits. 827 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; 828 Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi)); 829 // And Lo bits. 830 Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64, 831 SDOperand(Result, 0), getI32Imm(Lo)); 832 } else { 833 // Just the Hi bits. 834 Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi)); 835 } 836 837 // If no shift, we're done. 838 if (!Shift) return Result; 839 840 // Shift for next step if the upper 32-bits were not zero. 841 if (Imm) { 842 Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64, 843 SDOperand(Result, 0), 844 getI32Imm(Shift), getI32Imm(63 - Shift)); 845 } 846 847 // Add in the last bits as required. 848 if ((Hi = (Remainder >> 16) & 0xFFFF)) { 849 Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64, 850 SDOperand(Result, 0), getI32Imm(Hi)); 851 } 852 if ((Lo = Remainder & 0xFFFF)) { 853 Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64, 854 SDOperand(Result, 0), getI32Imm(Lo)); 855 } 856 857 return Result; 858 } 859 break; 860 } 861 862 case ISD::SETCC: 863 return SelectSETCC(Op); 864 case PPCISD::GlobalBaseReg: 865 return getGlobalBaseReg(); 866 867 case ISD::FrameIndex: { 868 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 869 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType()); 870 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8; 871 if (N->hasOneUse()) 872 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI, 873 getSmallIPtrImm(0)); 874 return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI, 875 getSmallIPtrImm(0)); 876 } 877 878 case PPCISD::MFCR: { 879 SDOperand InFlag = N->getOperand(1); 880 AddToISelQueue(InFlag); 881 // Use MFOCRF if supported. 882 if (PPCSubTarget.isGigaProcessor()) 883 return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, 884 N->getOperand(0), InFlag); 885 else 886 return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag); 887 } 888 889 case ISD::SDIV: { 890 // FIXME: since this depends on the setting of the carry flag from the srawi 891 // we should really be making notes about that for the scheduler. 892 // FIXME: It sure would be nice if we could cheaply recognize the 893 // srl/add/sra pattern the dag combiner will generate for this as 894 // sra/addze rather than having to handle sdiv ourselves. oh well. 895 unsigned Imm; 896 if (isInt32Immediate(N->getOperand(1), Imm)) { 897 SDOperand N0 = N->getOperand(0); 898 AddToISelQueue(N0); 899 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { 900 SDNode *Op = 901 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, 902 N0, getI32Imm(Log2_32(Imm))); 903 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 904 SDOperand(Op, 0), SDOperand(Op, 1)); 905 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { 906 SDNode *Op = 907 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, 908 N0, getI32Imm(Log2_32(-Imm))); 909 SDOperand PT = 910 SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, 911 SDOperand(Op, 0), SDOperand(Op, 1)), 912 0); 913 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); 914 } 915 } 916 917 // Other cases are autogenerated. 918 break; 919 } 920 921 case ISD::LOAD: { 922 // Handle preincrement loads. 923 LoadSDNode *LD = cast<LoadSDNode>(Op); 924 MVT::ValueType LoadedVT = LD->getMemoryVT(); 925 926 // Normal loads are handled by code generated from the .td file. 927 if (LD->getAddressingMode() != ISD::PRE_INC) 928 break; 929 930 SDOperand Offset = LD->getOffset(); 931 if (isa<ConstantSDNode>(Offset) || 932 Offset.getOpcode() == ISD::TargetGlobalAddress) { 933 934 unsigned Opcode; 935 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 936 if (LD->getValueType(0) != MVT::i64) { 937 // Handle PPC32 integer and normal FP loads. 938 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 939 switch (LoadedVT) { 940 default: assert(0 && "Invalid PPC load type!"); 941 case MVT::f64: Opcode = PPC::LFDU; break; 942 case MVT::f32: Opcode = PPC::LFSU; break; 943 case MVT::i32: Opcode = PPC::LWZU; break; 944 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; 945 case MVT::i1: 946 case MVT::i8: Opcode = PPC::LBZU; break; 947 } 948 } else { 949 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 950 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 951 switch (LoadedVT) { 952 default: assert(0 && "Invalid PPC load type!"); 953 case MVT::i64: Opcode = PPC::LDU; break; 954 case MVT::i32: Opcode = PPC::LWZU8; break; 955 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; 956 case MVT::i1: 957 case MVT::i8: Opcode = PPC::LBZU8; break; 958 } 959 } 960 961 SDOperand Chain = LD->getChain(); 962 SDOperand Base = LD->getBasePtr(); 963 AddToISelQueue(Chain); 964 AddToISelQueue(Base); 965 AddToISelQueue(Offset); 966 SDOperand Ops[] = { Offset, Base, Chain }; 967 // FIXME: PPC64 968 return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32, 969 MVT::Other, Ops, 3); 970 } else { 971 assert(0 && "R+R preindex loads not supported yet!"); 972 } 973 } 974 975 case ISD::AND: { 976 unsigned Imm, Imm2, SH, MB, ME; 977 978 // If this is an and of a value rotated between 0 and 31 bits and then and'd 979 // with a mask, emit rlwinm 980 if (isInt32Immediate(N->getOperand(1), Imm) && 981 isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) { 982 SDOperand Val = N->getOperand(0).getOperand(0); 983 AddToISelQueue(Val); 984 SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 985 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 986 } 987 // If this is just a masked value where the input is not handled above, and 988 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm 989 if (isInt32Immediate(N->getOperand(1), Imm) && 990 isRunOfOnes(Imm, MB, ME) && 991 N->getOperand(0).getOpcode() != ISD::ROTL) { 992 SDOperand Val = N->getOperand(0); 993 AddToISelQueue(Val); 994 SDOperand Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; 995 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 996 } 997 // AND X, 0 -> 0, not "rlwinm 32". 998 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) { 999 AddToISelQueue(N->getOperand(1)); 1000 ReplaceUses(SDOperand(N, 0), N->getOperand(1)); 1001 return NULL; 1002 } 1003 // ISD::OR doesn't get all the bitfield insertion fun. 1004 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert 1005 if (isInt32Immediate(N->getOperand(1), Imm) && 1006 N->getOperand(0).getOpcode() == ISD::OR && 1007 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) { 1008 unsigned MB, ME; 1009 Imm = ~(Imm^Imm2); 1010 if (isRunOfOnes(Imm, MB, ME)) { 1011 AddToISelQueue(N->getOperand(0).getOperand(0)); 1012 AddToISelQueue(N->getOperand(0).getOperand(1)); 1013 SDOperand Ops[] = { N->getOperand(0).getOperand(0), 1014 N->getOperand(0).getOperand(1), 1015 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; 1016 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5); 1017 } 1018 } 1019 1020 // Other cases are autogenerated. 1021 break; 1022 } 1023 case ISD::OR: 1024 if (N->getValueType(0) == MVT::i32) 1025 if (SDNode *I = SelectBitfieldInsert(N)) 1026 return I; 1027 1028 // Other cases are autogenerated. 1029 break; 1030 case ISD::SHL: { 1031 unsigned Imm, SH, MB, ME; 1032 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && 1033 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1034 AddToISelQueue(N->getOperand(0).getOperand(0)); 1035 SDOperand Ops[] = { N->getOperand(0).getOperand(0), 1036 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1037 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1038 } 1039 1040 // Other cases are autogenerated. 1041 break; 1042 } 1043 case ISD::SRL: { 1044 unsigned Imm, SH, MB, ME; 1045 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && 1046 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1047 AddToISelQueue(N->getOperand(0).getOperand(0)); 1048 SDOperand Ops[] = { N->getOperand(0).getOperand(0), 1049 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1050 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1051 } 1052 1053 // Other cases are autogenerated. 1054 break; 1055 } 1056 case ISD::SELECT_CC: { 1057 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1058 1059 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc 1060 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1061 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2))) 1062 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3))) 1063 if (N1C->isNullValue() && N3C->isNullValue() && 1064 N2C->getValue() == 1ULL && CC == ISD::SETNE && 1065 // FIXME: Implement this optzn for PPC64. 1066 N->getValueType(0) == MVT::i32) { 1067 AddToISelQueue(N->getOperand(0)); 1068 SDNode *Tmp = 1069 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, 1070 N->getOperand(0), getI32Imm(~0U)); 1071 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, 1072 SDOperand(Tmp, 0), N->getOperand(0), 1073 SDOperand(Tmp, 1)); 1074 } 1075 1076 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); 1077 unsigned BROpc = getPredicateForSetCC(CC); 1078 1079 unsigned SelectCCOp; 1080 if (N->getValueType(0) == MVT::i32) 1081 SelectCCOp = PPC::SELECT_CC_I4; 1082 else if (N->getValueType(0) == MVT::i64) 1083 SelectCCOp = PPC::SELECT_CC_I8; 1084 else if (N->getValueType(0) == MVT::f32) 1085 SelectCCOp = PPC::SELECT_CC_F4; 1086 else if (N->getValueType(0) == MVT::f64) 1087 SelectCCOp = PPC::SELECT_CC_F8; 1088 else 1089 SelectCCOp = PPC::SELECT_CC_VRRC; 1090 1091 AddToISelQueue(N->getOperand(2)); 1092 AddToISelQueue(N->getOperand(3)); 1093 SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), 1094 getI32Imm(BROpc) }; 1095 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4); 1096 } 1097 case PPCISD::COND_BRANCH: { 1098 AddToISelQueue(N->getOperand(0)); // Op #0 is the Chain. 1099 // Op #1 is the PPC::PRED_* number. 1100 // Op #2 is the CR# 1101 // Op #3 is the Dest MBB 1102 AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag. 1103 // Prevent PPC::PRED_* from being selected into LI. 1104 SDOperand Pred = 1105 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getValue()); 1106 SDOperand Ops[] = { Pred, N->getOperand(2), N->getOperand(3), 1107 N->getOperand(0), N->getOperand(4) }; 1108 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5); 1109 } 1110 case ISD::BR_CC: { 1111 AddToISelQueue(N->getOperand(0)); 1112 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1113 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); 1114 SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, 1115 N->getOperand(4), N->getOperand(0) }; 1116 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); 1117 } 1118 case ISD::BRIND: { 1119 // FIXME: Should custom lower this. 1120 SDOperand Chain = N->getOperand(0); 1121 SDOperand Target = N->getOperand(1); 1122 AddToISelQueue(Chain); 1123 AddToISelQueue(Target); 1124 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; 1125 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target, 1126 Chain), 0); 1127 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain); 1128 } 1129 } 1130 1131 return SelectCode(Op); 1132} 1133 1134 1135 1136/// createPPCISelDag - This pass converts a legalized DAG into a 1137/// PowerPC-specific DAG, ready for instruction scheduling. 1138/// 1139FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) { 1140 return new PPCDAGToDAGISel(TM); 1141} 1142 1143