PPCISelDAGToDAG.cpp revision c23197a26f34f559ea9797de51e187087c039c42
1//===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines a pattern matching instruction selector for PowerPC, 11// converting from a legalized dag to a PPC dag. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "ppc-codegen" 16#include "PPC.h" 17#include "PPCPredicates.h" 18#include "PPCTargetMachine.h" 19#include "PPCISelLowering.h" 20#include "PPCHazardRecognizers.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineFunction.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/SelectionDAGISel.h" 26#include "llvm/Target/TargetOptions.h" 27#include "llvm/Constants.h" 28#include "llvm/Function.h" 29#include "llvm/GlobalValue.h" 30#include "llvm/Intrinsics.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Support/Compiler.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/raw_ostream.h" 36using namespace llvm; 37 38namespace { 39 //===--------------------------------------------------------------------===// 40 /// PPCDAGToDAGISel - PPC specific code to select PPC machine 41 /// instructions for SelectionDAG operations. 42 /// 43 class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel { 44 PPCTargetMachine &TM; 45 PPCTargetLowering &PPCLowering; 46 const PPCSubtarget &PPCSubTarget; 47 unsigned GlobalBaseReg; 48 public: 49 explicit PPCDAGToDAGISel(PPCTargetMachine &tm) 50 : SelectionDAGISel(tm), TM(tm), 51 PPCLowering(*TM.getTargetLowering()), 52 PPCSubTarget(*TM.getSubtargetImpl()) {} 53 54 virtual bool runOnFunction(Function &Fn) { 55 // Do not codegen any 'available_externally' functions at all, they have 56 // definitions outside the translation unit. 57 if (Fn.hasAvailableExternallyLinkage()) 58 return false; 59 60 // Make sure we re-emit a set of the global base reg if necessary 61 GlobalBaseReg = 0; 62 SelectionDAGISel::runOnFunction(Fn); 63 64 InsertVRSaveCode(Fn); 65 return true; 66 } 67 68 /// getI32Imm - Return a target constant with the specified value, of type 69 /// i32. 70 inline SDValue getI32Imm(unsigned Imm) { 71 return CurDAG->getTargetConstant(Imm, MVT::i32); 72 } 73 74 /// getI64Imm - Return a target constant with the specified value, of type 75 /// i64. 76 inline SDValue getI64Imm(uint64_t Imm) { 77 return CurDAG->getTargetConstant(Imm, MVT::i64); 78 } 79 80 /// getSmallIPtrImm - Return a target constant of pointer type. 81 inline SDValue getSmallIPtrImm(unsigned Imm) { 82 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy()); 83 } 84 85 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s 86 /// with any number of 0s on either side. The 1s are allowed to wrap from 87 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 88 /// 0x0F0F0000 is not, since all 1s are not contiguous. 89 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME); 90 91 92 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a 93 /// rotate and mask opcode and mask operation. 94 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask, 95 unsigned &SH, unsigned &MB, unsigned &ME); 96 97 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC 98 /// base register. Return the virtual register that holds this value. 99 SDNode *getGlobalBaseReg(); 100 101 // Select - Convert the specified operand from a target-independent to a 102 // target-specific node if it hasn't already been changed. 103 SDNode *Select(SDValue Op); 104 105 SDNode *SelectBitfieldInsert(SDNode *N); 106 107 /// SelectCC - Select a comparison of the specified values with the 108 /// specified condition code, returning the CR# of the expression. 109 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl); 110 111 /// SelectAddrImm - Returns true if the address N can be represented by 112 /// a base register plus a signed 16-bit displacement [r+imm]. 113 bool SelectAddrImm(SDValue Op, SDValue N, SDValue &Disp, 114 SDValue &Base) { 115 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG); 116 } 117 118 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc 119 /// immediate field. Because preinc imms have already been validated, just 120 /// accept it. 121 bool SelectAddrImmOffs(SDValue Op, SDValue N, SDValue &Out) const { 122 Out = N; 123 return true; 124 } 125 126 /// SelectAddrIdx - Given the specified addressed, check to see if it can be 127 /// represented as an indexed [r+r] operation. Returns false if it can 128 /// be represented by [r+imm], which are preferred. 129 bool SelectAddrIdx(SDValue Op, SDValue N, SDValue &Base, 130 SDValue &Index) { 131 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG); 132 } 133 134 /// SelectAddrIdxOnly - Given the specified addressed, force it to be 135 /// represented as an indexed [r+r] operation. 136 bool SelectAddrIdxOnly(SDValue Op, SDValue N, SDValue &Base, 137 SDValue &Index) { 138 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG); 139 } 140 141 /// SelectAddrImmShift - Returns true if the address N can be represented by 142 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable 143 /// for use by STD and friends. 144 bool SelectAddrImmShift(SDValue Op, SDValue N, SDValue &Disp, 145 SDValue &Base) { 146 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG); 147 } 148 149 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 150 /// inline asm expressions. 151 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 152 char ConstraintCode, 153 std::vector<SDValue> &OutOps) { 154 SDValue Op0, Op1; 155 switch (ConstraintCode) { 156 default: return true; 157 case 'm': // memory 158 if (!SelectAddrIdx(Op, Op, Op0, Op1)) 159 SelectAddrImm(Op, Op, Op0, Op1); 160 break; 161 case 'o': // offsetable 162 if (!SelectAddrImm(Op, Op, Op0, Op1)) { 163 Op0 = Op; 164 Op1 = getSmallIPtrImm(0); 165 } 166 break; 167 case 'v': // not offsetable 168 SelectAddrIdxOnly(Op, Op, Op0, Op1); 169 break; 170 } 171 172 OutOps.push_back(Op0); 173 OutOps.push_back(Op1); 174 return false; 175 } 176 177 SDValue BuildSDIVSequence(SDNode *N); 178 SDValue BuildUDIVSequence(SDNode *N); 179 180 /// InstructionSelect - This callback is invoked by 181 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 182 virtual void InstructionSelect(); 183 184 void InsertVRSaveCode(Function &Fn); 185 186 virtual const char *getPassName() const { 187 return "PowerPC DAG->DAG Pattern Instruction Selection"; 188 } 189 190 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for 191 /// this target when scheduling the DAG. 192 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() { 193 // Should use subtarget info to pick the right hazard recognizer. For 194 // now, always return a PPC970 recognizer. 195 const TargetInstrInfo *II = TM.getInstrInfo(); 196 assert(II && "No InstrInfo?"); 197 return new PPCHazardRecognizer970(*II); 198 } 199 200// Include the pieces autogenerated from the target description. 201#include "PPCGenDAGISel.inc" 202 203private: 204 SDNode *SelectSETCC(SDValue Op); 205 }; 206} 207 208/// InstructionSelect - This callback is invoked by 209/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 210void PPCDAGToDAGISel::InstructionSelect() { 211 DEBUG(BB->dump()); 212 213 // Select target instructions for the DAG. 214 SelectRoot(*CurDAG); 215 CurDAG->RemoveDeadNodes(); 216} 217 218/// InsertVRSaveCode - Once the entire function has been instruction selected, 219/// all virtual registers are created and all machine instructions are built, 220/// check to see if we need to save/restore VRSAVE. If so, do it. 221void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) { 222 // Check to see if this function uses vector registers, which means we have to 223 // save and restore the VRSAVE register and update it with the regs we use. 224 // 225 // In this case, there will be virtual registers of vector type type created 226 // by the scheduler. Detect them now. 227 MachineFunction &Fn = MachineFunction::get(&F); 228 bool HasVectorVReg = false; 229 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister, 230 e = RegInfo->getLastVirtReg()+1; i != e; ++i) 231 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) { 232 HasVectorVReg = true; 233 break; 234 } 235 if (!HasVectorVReg) return; // nothing to do. 236 237 // If we have a vector register, we want to emit code into the entry and exit 238 // blocks to save and restore the VRSAVE register. We do this here (instead 239 // of marking all vector instructions as clobbering VRSAVE) for two reasons: 240 // 241 // 1. This (trivially) reduces the load on the register allocator, by not 242 // having to represent the live range of the VRSAVE register. 243 // 2. This (more significantly) allows us to create a temporary virtual 244 // register to hold the saved VRSAVE value, allowing this temporary to be 245 // register allocated, instead of forcing it to be spilled to the stack. 246 247 // Create two vregs - one to hold the VRSAVE register that is live-in to the 248 // function and one for the value after having bits or'd into it. 249 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 250 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass); 251 252 const TargetInstrInfo &TII = *TM.getInstrInfo(); 253 MachineBasicBlock &EntryBB = *Fn.begin(); 254 DebugLoc dl = DebugLoc::getUnknownLoc(); 255 // Emit the following code into the entry block: 256 // InVRSAVE = MFVRSAVE 257 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE 258 // MTVRSAVE UpdatedVRSAVE 259 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point 260 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); 261 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), 262 UpdatedVRSAVE).addReg(InVRSAVE); 263 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); 264 265 // Find all return blocks, outputting a restore in each epilog. 266 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 267 if (!BB->empty() && BB->back().getDesc().isReturn()) { 268 IP = BB->end(); --IP; 269 270 // Skip over all terminator instructions, which are part of the return 271 // sequence. 272 MachineBasicBlock::iterator I2 = IP; 273 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator()) 274 IP = I2; 275 276 // Emit: MTVRSAVE InVRSave 277 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); 278 } 279 } 280} 281 282 283/// getGlobalBaseReg - Output the instructions required to put the 284/// base address to use for accessing globals into a register. 285/// 286SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { 287 if (!GlobalBaseReg) { 288 const TargetInstrInfo &TII = *TM.getInstrInfo(); 289 // Insert the set of GlobalBaseReg into the first MBB of the function 290 MachineBasicBlock &FirstMBB = BB->getParent()->front(); 291 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 292 DebugLoc dl = DebugLoc::getUnknownLoc(); 293 294 if (PPCLowering.getPointerTy() == MVT::i32) { 295 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass); 296 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR); 297 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); 298 } else { 299 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass); 300 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8); 301 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); 302 } 303 } 304 return CurDAG->getRegister(GlobalBaseReg, 305 PPCLowering.getPointerTy()).getNode(); 306} 307 308/// isIntS16Immediate - This method tests to see if the node is either a 32-bit 309/// or 64-bit immediate, and if the value can be accurately represented as a 310/// sign extension from a 16-bit value. If so, this returns true and the 311/// immediate. 312static bool isIntS16Immediate(SDNode *N, short &Imm) { 313 if (N->getOpcode() != ISD::Constant) 314 return false; 315 316 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); 317 if (N->getValueType(0) == MVT::i32) 318 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); 319 else 320 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); 321} 322 323static bool isIntS16Immediate(SDValue Op, short &Imm) { 324 return isIntS16Immediate(Op.getNode(), Imm); 325} 326 327 328/// isInt32Immediate - This method tests to see if the node is a 32-bit constant 329/// operand. If so Imm will receive the 32-bit value. 330static bool isInt32Immediate(SDNode *N, unsigned &Imm) { 331 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { 332 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 333 return true; 334 } 335 return false; 336} 337 338/// isInt64Immediate - This method tests to see if the node is a 64-bit constant 339/// operand. If so Imm will receive the 64-bit value. 340static bool isInt64Immediate(SDNode *N, uint64_t &Imm) { 341 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { 342 Imm = cast<ConstantSDNode>(N)->getZExtValue(); 343 return true; 344 } 345 return false; 346} 347 348// isInt32Immediate - This method tests to see if a constant operand. 349// If so Imm will receive the 32 bit value. 350static bool isInt32Immediate(SDValue N, unsigned &Imm) { 351 return isInt32Immediate(N.getNode(), Imm); 352} 353 354 355// isOpcWithIntImmediate - This method tests to see if the node is a specific 356// opcode and that it has a immediate integer right operand. 357// If so Imm will receive the 32 bit value. 358static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { 359 return N->getOpcode() == Opc 360 && isInt32Immediate(N->getOperand(1).getNode(), Imm); 361} 362 363bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { 364 if (isShiftedMask_32(Val)) { 365 // look for the first non-zero bit 366 MB = CountLeadingZeros_32(Val); 367 // look for the first zero bit after the run of ones 368 ME = CountLeadingZeros_32((Val - 1) ^ Val); 369 return true; 370 } else { 371 Val = ~Val; // invert mask 372 if (isShiftedMask_32(Val)) { 373 // effectively look for the first zero bit 374 ME = CountLeadingZeros_32(Val) - 1; 375 // effectively look for the first one bit after the run of zeros 376 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1; 377 return true; 378 } 379 } 380 // no run present 381 return false; 382} 383 384bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, 385 bool IsShiftMask, unsigned &SH, 386 unsigned &MB, unsigned &ME) { 387 // Don't even go down this path for i64, since different logic will be 388 // necessary for rldicl/rldicr/rldimi. 389 if (N->getValueType(0) != MVT::i32) 390 return false; 391 392 unsigned Shift = 32; 393 unsigned Indeterminant = ~0; // bit mask marking indeterminant results 394 unsigned Opcode = N->getOpcode(); 395 if (N->getNumOperands() != 2 || 396 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) 397 return false; 398 399 if (Opcode == ISD::SHL) { 400 // apply shift left to mask if it comes first 401 if (IsShiftMask) Mask = Mask << Shift; 402 // determine which bits are made indeterminant by shift 403 Indeterminant = ~(0xFFFFFFFFu << Shift); 404 } else if (Opcode == ISD::SRL) { 405 // apply shift right to mask if it comes first 406 if (IsShiftMask) Mask = Mask >> Shift; 407 // determine which bits are made indeterminant by shift 408 Indeterminant = ~(0xFFFFFFFFu >> Shift); 409 // adjust for the left rotate 410 Shift = 32 - Shift; 411 } else if (Opcode == ISD::ROTL) { 412 Indeterminant = 0; 413 } else { 414 return false; 415 } 416 417 // if the mask doesn't intersect any Indeterminant bits 418 if (Mask && !(Mask & Indeterminant)) { 419 SH = Shift & 31; 420 // make sure the mask is still a mask (wrap arounds may not be) 421 return isRunOfOnes(Mask, MB, ME); 422 } 423 return false; 424} 425 426/// SelectBitfieldInsert - turn an or of two masked values into 427/// the rotate left word immediate then mask insert (rlwimi) instruction. 428SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { 429 SDValue Op0 = N->getOperand(0); 430 SDValue Op1 = N->getOperand(1); 431 DebugLoc dl = N->getDebugLoc(); 432 433 APInt LKZ, LKO, RKZ, RKO; 434 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO); 435 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO); 436 437 unsigned TargetMask = LKZ.getZExtValue(); 438 unsigned InsertMask = RKZ.getZExtValue(); 439 440 if ((TargetMask | InsertMask) == 0xFFFFFFFF) { 441 unsigned Op0Opc = Op0.getOpcode(); 442 unsigned Op1Opc = Op1.getOpcode(); 443 unsigned Value, SH = 0; 444 TargetMask = ~TargetMask; 445 InsertMask = ~InsertMask; 446 447 // If the LHS has a foldable shift and the RHS does not, then swap it to the 448 // RHS so that we can fold the shift into the insert. 449 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { 450 if (Op0.getOperand(0).getOpcode() == ISD::SHL || 451 Op0.getOperand(0).getOpcode() == ISD::SRL) { 452 if (Op1.getOperand(0).getOpcode() != ISD::SHL && 453 Op1.getOperand(0).getOpcode() != ISD::SRL) { 454 std::swap(Op0, Op1); 455 std::swap(Op0Opc, Op1Opc); 456 std::swap(TargetMask, InsertMask); 457 } 458 } 459 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) { 460 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && 461 Op1.getOperand(0).getOpcode() != ISD::SRL) { 462 std::swap(Op0, Op1); 463 std::swap(Op0Opc, Op1Opc); 464 std::swap(TargetMask, InsertMask); 465 } 466 } 467 468 unsigned MB, ME; 469 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) { 470 SDValue Tmp1, Tmp2, Tmp3; 471 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF; 472 473 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) && 474 isInt32Immediate(Op1.getOperand(1), Value)) { 475 Op1 = Op1.getOperand(0); 476 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value; 477 } 478 if (Op1Opc == ISD::AND) { 479 unsigned SHOpc = Op1.getOperand(0).getOpcode(); 480 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && 481 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) { 482 Op1 = Op1.getOperand(0).getOperand(0); 483 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value; 484 } else { 485 Op1 = Op1.getOperand(0); 486 } 487 } 488 489 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0; 490 SH &= 31; 491 SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB), 492 getI32Imm(ME) }; 493 return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); 494 } 495 } 496 return 0; 497} 498 499/// SelectCC - Select a comparison of the specified values with the specified 500/// condition code, returning the CR# of the expression. 501SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, 502 ISD::CondCode CC, DebugLoc dl) { 503 // Always select the LHS. 504 unsigned Opc; 505 506 if (LHS.getValueType() == MVT::i32) { 507 unsigned Imm; 508 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 509 if (isInt32Immediate(RHS, Imm)) { 510 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 511 if (isUInt16(Imm)) 512 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS, 513 getI32Imm(Imm & 0xFFFF)), 0); 514 // If this is a 16-bit signed immediate, fold it. 515 if (isInt16((int)Imm)) 516 return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS, 517 getI32Imm(Imm & 0xFFFF)), 0); 518 519 // For non-equality comparisons, the default code would materialize the 520 // constant, then compare against it, like this: 521 // lis r2, 4660 522 // ori r2, r2, 22136 523 // cmpw cr0, r3, r2 524 // Since we are just comparing for equality, we can emit this instead: 525 // xoris r0,r3,0x1234 526 // cmplwi cr0,r0,0x5678 527 // beq cr0,L6 528 SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, MVT::i32, LHS, 529 getI32Imm(Imm >> 16)), 0); 530 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, Xor, 531 getI32Imm(Imm & 0xFFFF)), 0); 532 } 533 Opc = PPC::CMPLW; 534 } else if (ISD::isUnsignedIntSetCC(CC)) { 535 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm)) 536 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS, 537 getI32Imm(Imm & 0xFFFF)), 0); 538 Opc = PPC::CMPLW; 539 } else { 540 short SImm; 541 if (isIntS16Immediate(RHS, SImm)) 542 return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS, 543 getI32Imm((int)SImm & 0xFFFF)), 544 0); 545 Opc = PPC::CMPW; 546 } 547 } else if (LHS.getValueType() == MVT::i64) { 548 uint64_t Imm; 549 if (CC == ISD::SETEQ || CC == ISD::SETNE) { 550 if (isInt64Immediate(RHS.getNode(), Imm)) { 551 // SETEQ/SETNE comparison with 16-bit immediate, fold it. 552 if (isUInt16(Imm)) 553 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS, 554 getI32Imm(Imm & 0xFFFF)), 0); 555 // If this is a 16-bit signed immediate, fold it. 556 if (isInt16(Imm)) 557 return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS, 558 getI32Imm(Imm & 0xFFFF)), 0); 559 560 // For non-equality comparisons, the default code would materialize the 561 // constant, then compare against it, like this: 562 // lis r2, 4660 563 // ori r2, r2, 22136 564 // cmpd cr0, r3, r2 565 // Since we are just comparing for equality, we can emit this instead: 566 // xoris r0,r3,0x1234 567 // cmpldi cr0,r0,0x5678 568 // beq cr0,L6 569 if (isUInt32(Imm)) { 570 SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, MVT::i64, LHS, 571 getI64Imm(Imm >> 16)), 0); 572 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, Xor, 573 getI64Imm(Imm & 0xFFFF)), 0); 574 } 575 } 576 Opc = PPC::CMPLD; 577 } else if (ISD::isUnsignedIntSetCC(CC)) { 578 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm)) 579 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS, 580 getI64Imm(Imm & 0xFFFF)), 0); 581 Opc = PPC::CMPLD; 582 } else { 583 short SImm; 584 if (isIntS16Immediate(RHS, SImm)) 585 return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS, 586 getI64Imm(SImm & 0xFFFF)), 587 0); 588 Opc = PPC::CMPD; 589 } 590 } else if (LHS.getValueType() == MVT::f32) { 591 Opc = PPC::FCMPUS; 592 } else { 593 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); 594 Opc = PPC::FCMPUD; 595 } 596 return SDValue(CurDAG->getTargetNode(Opc, dl, MVT::i32, LHS, RHS), 0); 597} 598 599static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { 600 switch (CC) { 601 case ISD::SETUEQ: 602 case ISD::SETONE: 603 case ISD::SETOLE: 604 case ISD::SETOGE: 605 llvm_unreachable("Should be lowered by legalize!"); 606 default: llvm_unreachable("Unknown condition!"); 607 case ISD::SETOEQ: 608 case ISD::SETEQ: return PPC::PRED_EQ; 609 case ISD::SETUNE: 610 case ISD::SETNE: return PPC::PRED_NE; 611 case ISD::SETOLT: 612 case ISD::SETLT: return PPC::PRED_LT; 613 case ISD::SETULE: 614 case ISD::SETLE: return PPC::PRED_LE; 615 case ISD::SETOGT: 616 case ISD::SETGT: return PPC::PRED_GT; 617 case ISD::SETUGE: 618 case ISD::SETGE: return PPC::PRED_GE; 619 case ISD::SETO: return PPC::PRED_NU; 620 case ISD::SETUO: return PPC::PRED_UN; 621 // These two are invalid for floating point. Assume we have int. 622 case ISD::SETULT: return PPC::PRED_LT; 623 case ISD::SETUGT: return PPC::PRED_GT; 624 } 625} 626 627/// getCRIdxForSetCC - Return the index of the condition register field 628/// associated with the SetCC condition, and whether or not the field is 629/// treated as inverted. That is, lt = 0; ge = 0 inverted. 630/// 631/// If this returns with Other != -1, then the returned comparison is an or of 632/// two simpler comparisons. In this case, Invert is guaranteed to be false. 633static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { 634 Invert = false; 635 Other = -1; 636 switch (CC) { 637 default: llvm_unreachable("Unknown condition!"); 638 case ISD::SETOLT: 639 case ISD::SETLT: return 0; // Bit #0 = SETOLT 640 case ISD::SETOGT: 641 case ISD::SETGT: return 1; // Bit #1 = SETOGT 642 case ISD::SETOEQ: 643 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ 644 case ISD::SETUO: return 3; // Bit #3 = SETUO 645 case ISD::SETUGE: 646 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE 647 case ISD::SETULE: 648 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE 649 case ISD::SETUNE: 650 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE 651 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO 652 case ISD::SETUEQ: 653 case ISD::SETOGE: 654 case ISD::SETOLE: 655 case ISD::SETONE: 656 llvm_unreachable("Invalid branch code: should be expanded by legalize"); 657 // These are invalid for floating point. Assume integer. 658 case ISD::SETULT: return 0; 659 case ISD::SETUGT: return 1; 660 } 661 return 0; 662} 663 664SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { 665 SDNode *N = Op.getNode(); 666 DebugLoc dl = N->getDebugLoc(); 667 unsigned Imm; 668 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 669 if (isInt32Immediate(N->getOperand(1), Imm)) { 670 // We can codegen setcc op, imm very efficiently compared to a brcond. 671 // Check for those cases here. 672 // setcc op, 0 673 if (Imm == 0) { 674 SDValue Op = N->getOperand(0); 675 switch (CC) { 676 default: break; 677 case ISD::SETEQ: { 678 Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); 679 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; 680 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 681 } 682 case ISD::SETNE: { 683 SDValue AD = 684 SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, 685 Op, getI32Imm(~0U)), 0); 686 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, 687 AD.getValue(1)); 688 } 689 case ISD::SETLT: { 690 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 691 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 692 } 693 case ISD::SETGT: { 694 SDValue T = 695 SDValue(CurDAG->getTargetNode(PPC::NEG, dl, MVT::i32, Op), 0); 696 T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); 697 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 698 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 699 } 700 } 701 } else if (Imm == ~0U) { // setcc op, -1 702 SDValue Op = N->getOperand(0); 703 switch (CC) { 704 default: break; 705 case ISD::SETEQ: 706 Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, 707 Op, getI32Imm(1)), 0); 708 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 709 SDValue(CurDAG->getTargetNode(PPC::LI, dl, 710 MVT::i32, 711 getI32Imm(0)), 0), 712 Op.getValue(1)); 713 case ISD::SETNE: { 714 Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); 715 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, 716 Op, getI32Imm(~0U)); 717 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), 718 Op, SDValue(AD, 1)); 719 } 720 case ISD::SETLT: { 721 SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, MVT::i32, Op, 722 getI32Imm(1)), 0); 723 SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, MVT::i32, AD, 724 Op), 0); 725 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 726 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 727 } 728 case ISD::SETGT: { 729 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; 730 Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 731 0); 732 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, 733 getI32Imm(1)); 734 } 735 } 736 } 737 } 738 739 bool Inv; 740 int OtherCondIdx; 741 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx); 742 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); 743 SDValue IntCR; 744 745 // Force the ccreg into CR7. 746 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); 747 748 SDValue InFlag(0, 0); // Null incoming flag value. 749 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, 750 InFlag).getValue(1); 751 752 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1) 753 IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, 754 CCReg), 0); 755 else 756 IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, CCReg), 0); 757 758 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), 759 getI32Imm(31), getI32Imm(31) }; 760 if (OtherCondIdx == -1 && !Inv) 761 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 762 763 // Get the specified bit. 764 SDValue Tmp = 765 SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); 766 if (Inv) { 767 assert(OtherCondIdx == -1 && "Can't have split plus negation"); 768 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); 769 } 770 771 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT. 772 // We already got the bit for the first part of the comparison (e.g. SETULE). 773 774 // Get the other bit of the comparison. 775 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31); 776 SDValue OtherCond = 777 SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); 778 779 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond); 780} 781 782 783// Select - Convert the specified operand from a target-independent to a 784// target-specific node if it hasn't already been changed. 785SDNode *PPCDAGToDAGISel::Select(SDValue Op) { 786 SDNode *N = Op.getNode(); 787 DebugLoc dl = Op.getDebugLoc(); 788 if (N->isMachineOpcode()) 789 return NULL; // Already selected. 790 791 switch (N->getOpcode()) { 792 default: break; 793 794 case ISD::Constant: { 795 if (N->getValueType(0) == MVT::i64) { 796 // Get 64 bit value. 797 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue(); 798 // Assume no remaining bits. 799 unsigned Remainder = 0; 800 // Assume no shift required. 801 unsigned Shift = 0; 802 803 // If it can't be represented as a 32 bit value. 804 if (!isInt32(Imm)) { 805 Shift = CountTrailingZeros_64(Imm); 806 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift; 807 808 // If the shifted value fits 32 bits. 809 if (isInt32(ImmSh)) { 810 // Go with the shifted value. 811 Imm = ImmSh; 812 } else { 813 // Still stuck with a 64 bit value. 814 Remainder = Imm; 815 Shift = 32; 816 Imm >>= 32; 817 } 818 } 819 820 // Intermediate operand. 821 SDNode *Result; 822 823 // Handle first 32 bits. 824 unsigned Lo = Imm & 0xFFFF; 825 unsigned Hi = (Imm >> 16) & 0xFFFF; 826 827 // Simple value. 828 if (isInt16(Imm)) { 829 // Just the Lo bits. 830 Result = CurDAG->getTargetNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); 831 } else if (Lo) { 832 // Handle the Hi bits. 833 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; 834 Result = CurDAG->getTargetNode(OpC, dl, MVT::i64, getI32Imm(Hi)); 835 // And Lo bits. 836 Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64, 837 SDValue(Result, 0), getI32Imm(Lo)); 838 } else { 839 // Just the Hi bits. 840 Result = CurDAG->getTargetNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); 841 } 842 843 // If no shift, we're done. 844 if (!Shift) return Result; 845 846 // Shift for next step if the upper 32-bits were not zero. 847 if (Imm) { 848 Result = CurDAG->getTargetNode(PPC::RLDICR, dl, MVT::i64, 849 SDValue(Result, 0), 850 getI32Imm(Shift), getI32Imm(63 - Shift)); 851 } 852 853 // Add in the last bits as required. 854 if ((Hi = (Remainder >> 16) & 0xFFFF)) { 855 Result = CurDAG->getTargetNode(PPC::ORIS8, dl, MVT::i64, 856 SDValue(Result, 0), getI32Imm(Hi)); 857 } 858 if ((Lo = Remainder & 0xFFFF)) { 859 Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64, 860 SDValue(Result, 0), getI32Imm(Lo)); 861 } 862 863 return Result; 864 } 865 break; 866 } 867 868 case ISD::SETCC: 869 return SelectSETCC(Op); 870 case PPCISD::GlobalBaseReg: 871 return getGlobalBaseReg(); 872 873 case ISD::FrameIndex: { 874 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 875 SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType()); 876 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8; 877 if (N->hasOneUse()) 878 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI, 879 getSmallIPtrImm(0)); 880 return CurDAG->getTargetNode(Opc, dl, Op.getValueType(), TFI, 881 getSmallIPtrImm(0)); 882 } 883 884 case PPCISD::MFCR: { 885 SDValue InFlag = N->getOperand(1); 886 // Use MFOCRF if supported. 887 if (PPCSubTarget.isGigaProcessor()) 888 return CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, 889 N->getOperand(0), InFlag); 890 else 891 return CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, InFlag); 892 } 893 894 case ISD::SDIV: { 895 // FIXME: since this depends on the setting of the carry flag from the srawi 896 // we should really be making notes about that for the scheduler. 897 // FIXME: It sure would be nice if we could cheaply recognize the 898 // srl/add/sra pattern the dag combiner will generate for this as 899 // sra/addze rather than having to handle sdiv ourselves. oh well. 900 unsigned Imm; 901 if (isInt32Immediate(N->getOperand(1), Imm)) { 902 SDValue N0 = N->getOperand(0); 903 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { 904 SDNode *Op = 905 CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag, 906 N0, getI32Imm(Log2_32(Imm))); 907 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 908 SDValue(Op, 0), SDValue(Op, 1)); 909 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { 910 SDNode *Op = 911 CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag, 912 N0, getI32Imm(Log2_32(-Imm))); 913 SDValue PT = 914 SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, MVT::i32, 915 SDValue(Op, 0), SDValue(Op, 1)), 916 0); 917 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); 918 } 919 } 920 921 // Other cases are autogenerated. 922 break; 923 } 924 925 case ISD::LOAD: { 926 // Handle preincrement loads. 927 LoadSDNode *LD = cast<LoadSDNode>(Op); 928 MVT LoadedVT = LD->getMemoryVT(); 929 930 // Normal loads are handled by code generated from the .td file. 931 if (LD->getAddressingMode() != ISD::PRE_INC) 932 break; 933 934 SDValue Offset = LD->getOffset(); 935 if (isa<ConstantSDNode>(Offset) || 936 Offset.getOpcode() == ISD::TargetGlobalAddress) { 937 938 unsigned Opcode; 939 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; 940 if (LD->getValueType(0) != MVT::i64) { 941 // Handle PPC32 integer and normal FP loads. 942 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 943 switch (LoadedVT.getSimpleVT()) { 944 default: llvm_unreachable("Invalid PPC load type!"); 945 case MVT::f64: Opcode = PPC::LFDU; break; 946 case MVT::f32: Opcode = PPC::LFSU; break; 947 case MVT::i32: Opcode = PPC::LWZU; break; 948 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; 949 case MVT::i1: 950 case MVT::i8: Opcode = PPC::LBZU; break; 951 } 952 } else { 953 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); 954 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); 955 switch (LoadedVT.getSimpleVT()) { 956 default: llvm_unreachable("Invalid PPC load type!"); 957 case MVT::i64: Opcode = PPC::LDU; break; 958 case MVT::i32: Opcode = PPC::LWZU8; break; 959 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; 960 case MVT::i1: 961 case MVT::i8: Opcode = PPC::LBZU8; break; 962 } 963 } 964 965 SDValue Chain = LD->getChain(); 966 SDValue Base = LD->getBasePtr(); 967 SDValue Ops[] = { Offset, Base, Chain }; 968 // FIXME: PPC64 969 return CurDAG->getTargetNode(Opcode, dl, LD->getValueType(0), 970 PPCLowering.getPointerTy(), 971 MVT::Other, Ops, 3); 972 } else { 973 llvm_unreachable("R+R preindex loads not supported yet!"); 974 } 975 } 976 977 case ISD::AND: { 978 unsigned Imm, Imm2, SH, MB, ME; 979 980 // If this is an and of a value rotated between 0 and 31 bits and then and'd 981 // with a mask, emit rlwinm 982 if (isInt32Immediate(N->getOperand(1), Imm) && 983 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) { 984 SDValue Val = N->getOperand(0).getOperand(0); 985 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 986 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 987 } 988 // If this is just a masked value where the input is not handled above, and 989 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm 990 if (isInt32Immediate(N->getOperand(1), Imm) && 991 isRunOfOnes(Imm, MB, ME) && 992 N->getOperand(0).getOpcode() != ISD::ROTL) { 993 SDValue Val = N->getOperand(0); 994 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; 995 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 996 } 997 // AND X, 0 -> 0, not "rlwinm 32". 998 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) { 999 ReplaceUses(SDValue(N, 0), N->getOperand(1)); 1000 return NULL; 1001 } 1002 // ISD::OR doesn't get all the bitfield insertion fun. 1003 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert 1004 if (isInt32Immediate(N->getOperand(1), Imm) && 1005 N->getOperand(0).getOpcode() == ISD::OR && 1006 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) { 1007 unsigned MB, ME; 1008 Imm = ~(Imm^Imm2); 1009 if (isRunOfOnes(Imm, MB, ME)) { 1010 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1011 N->getOperand(0).getOperand(1), 1012 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; 1013 return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); 1014 } 1015 } 1016 1017 // Other cases are autogenerated. 1018 break; 1019 } 1020 case ISD::OR: 1021 if (N->getValueType(0) == MVT::i32) 1022 if (SDNode *I = SelectBitfieldInsert(N)) 1023 return I; 1024 1025 // Other cases are autogenerated. 1026 break; 1027 case ISD::SHL: { 1028 unsigned Imm, SH, MB, ME; 1029 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1030 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1031 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1032 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1033 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1034 } 1035 1036 // Other cases are autogenerated. 1037 break; 1038 } 1039 case ISD::SRL: { 1040 unsigned Imm, SH, MB, ME; 1041 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) && 1042 isRotateAndMask(N, Imm, true, SH, MB, ME)) { 1043 SDValue Ops[] = { N->getOperand(0).getOperand(0), 1044 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; 1045 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); 1046 } 1047 1048 // Other cases are autogenerated. 1049 break; 1050 } 1051 case ISD::SELECT_CC: { 1052 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1053 1054 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc 1055 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1056 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2))) 1057 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3))) 1058 if (N1C->isNullValue() && N3C->isNullValue() && 1059 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && 1060 // FIXME: Implement this optzn for PPC64. 1061 N->getValueType(0) == MVT::i32) { 1062 SDNode *Tmp = 1063 CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, 1064 N->getOperand(0), getI32Imm(~0U)); 1065 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, 1066 SDValue(Tmp, 0), N->getOperand(0), 1067 SDValue(Tmp, 1)); 1068 } 1069 1070 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl); 1071 unsigned BROpc = getPredicateForSetCC(CC); 1072 1073 unsigned SelectCCOp; 1074 if (N->getValueType(0) == MVT::i32) 1075 SelectCCOp = PPC::SELECT_CC_I4; 1076 else if (N->getValueType(0) == MVT::i64) 1077 SelectCCOp = PPC::SELECT_CC_I8; 1078 else if (N->getValueType(0) == MVT::f32) 1079 SelectCCOp = PPC::SELECT_CC_F4; 1080 else if (N->getValueType(0) == MVT::f64) 1081 SelectCCOp = PPC::SELECT_CC_F8; 1082 else 1083 SelectCCOp = PPC::SELECT_CC_VRRC; 1084 1085 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3), 1086 getI32Imm(BROpc) }; 1087 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4); 1088 } 1089 case PPCISD::COND_BRANCH: { 1090 // Op #0 is the Chain. 1091 // Op #1 is the PPC::PRED_* number. 1092 // Op #2 is the CR# 1093 // Op #3 is the Dest MBB 1094 // Op #4 is the Flag. 1095 // Prevent PPC::PRED_* from being selected into LI. 1096 SDValue Pred = 1097 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()); 1098 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3), 1099 N->getOperand(0), N->getOperand(4) }; 1100 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5); 1101 } 1102 case ISD::BR_CC: { 1103 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1104 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); 1105 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, 1106 N->getOperand(4), N->getOperand(0) }; 1107 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); 1108 } 1109 case ISD::BRIND: { 1110 // FIXME: Should custom lower this. 1111 SDValue Chain = N->getOperand(0); 1112 SDValue Target = N->getOperand(1); 1113 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; 1114 Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Target, 1115 Chain), 0); 1116 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain); 1117 } 1118 case ISD::DECLARE: { 1119 SDValue Chain = N->getOperand(0); 1120 SDValue N1 = N->getOperand(1); 1121 SDValue N2 = N->getOperand(2); 1122 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1); 1123 1124 // FIXME: We need to handle this for VLAs. 1125 if (!FINode) { 1126 ReplaceUses(Op.getValue(0), Chain); 1127 return NULL; 1128 } 1129 1130 if (N2.getOpcode() == ISD::ADD) { 1131 if (N2.getOperand(0).getOpcode() == ISD::ADD && 1132 N2.getOperand(0).getOperand(0).getOpcode() == PPCISD::GlobalBaseReg && 1133 N2.getOperand(0).getOperand(1).getOpcode() == PPCISD::Hi && 1134 N2.getOperand(1).getOpcode() == PPCISD::Lo) 1135 N2 = N2.getOperand(0).getOperand(1).getOperand(0); 1136 else if (N2.getOperand(0).getOpcode() == ISD::ADD && 1137 N2.getOperand(0).getOperand(0).getOpcode() == PPCISD::GlobalBaseReg && 1138 N2.getOperand(0).getOperand(1).getOpcode() == PPCISD::Lo && 1139 N2.getOperand(1).getOpcode() == PPCISD::Hi) 1140 N2 = N2.getOperand(0).getOperand(1).getOperand(0); 1141 else if (N2.getOperand(0).getOpcode() == PPCISD::Hi && 1142 N2.getOperand(1).getOpcode() == PPCISD::Lo) 1143 N2 = N2.getOperand(0).getOperand(0); 1144 } 1145 1146 // If we don't have a global address here, the debug info is mangled, just 1147 // drop it. 1148 if (!isa<GlobalAddressSDNode>(N2)) { 1149 ReplaceUses(Op.getValue(0), Chain); 1150 return NULL; 1151 } 1152 int FI = cast<FrameIndexSDNode>(N1)->getIndex(); 1153 GlobalValue *GV = cast<GlobalAddressSDNode>(N2)->getGlobal(); 1154 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); 1155 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy()); 1156 return CurDAG->SelectNodeTo(N, TargetInstrInfo::DECLARE, 1157 MVT::Other, Tmp1, Tmp2, Chain); 1158 } 1159 } 1160 1161 return SelectCode(Op); 1162} 1163 1164 1165 1166/// createPPCISelDag - This pass converts a legalized DAG into a 1167/// PowerPC-specific DAG, ready for instruction scheduling. 1168/// 1169FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) { 1170 return new PPCDAGToDAGISel(TM); 1171} 1172 1173