PPCISelDAGToDAG.cpp revision 333bd835bd0d01f0e49b2f3d590be685a4959e16
1//===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines a pattern matching instruction selector for 32 bit PowerPC, 11// converting from a legalized dag to a PPC dag. 12// 13//===----------------------------------------------------------------------===// 14 15#include "PowerPC.h" 16#include "PPC32TargetMachine.h" 17#include "PPC32ISelLowering.h" 18#include "llvm/CodeGen/MachineInstrBuilder.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/SSARegMap.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/Target/TargetOptions.h" 24#include "llvm/ADT/Statistic.h" 25#include "llvm/Constants.h" 26#include "llvm/GlobalValue.h" 27#include "llvm/Support/Debug.h" 28#include "llvm/Support/MathExtras.h" 29using namespace llvm; 30 31namespace { 32 Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations"); 33 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed"); 34 35 //===--------------------------------------------------------------------===// 36 /// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine 37 /// instructions for SelectionDAG operations. 38 /// 39 class PPC32DAGToDAGISel : public SelectionDAGISel { 40 PPC32TargetLowering PPC32Lowering; 41 unsigned GlobalBaseReg; 42 public: 43 PPC32DAGToDAGISel(TargetMachine &TM) 44 : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {} 45 46 virtual bool runOnFunction(Function &Fn) { 47 // Make sure we re-emit a set of the global base reg if necessary 48 GlobalBaseReg = 0; 49 return SelectionDAGISel::runOnFunction(Fn); 50 } 51 52 /// getI32Imm - Return a target constant with the specified value, of type 53 /// i32. 54 inline SDOperand getI32Imm(unsigned Imm) { 55 return CurDAG->getTargetConstant(Imm, MVT::i32); 56 } 57 58 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC 59 /// base register. Return the virtual register that holds this value. 60 SDOperand getGlobalBaseReg(); 61 62 // Select - Convert the specified operand from a target-independent to a 63 // target-specific node if it hasn't already been changed. 64 SDOperand Select(SDOperand Op); 65 66 SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS, 67 unsigned OCHi, unsigned OCLo, 68 bool IsArithmetic = false, 69 bool Negate = false); 70 SDNode *SelectBitfieldInsert(SDNode *N); 71 72 /// SelectCC - Select a comparison of the specified values with the 73 /// specified condition code, returning the CR# of the expression. 74 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC); 75 76 /// SelectAddr - Given the specified address, return the two operands for a 77 /// load/store instruction, and return true if it should be an indexed [r+r] 78 /// operation. 79 bool SelectAddr(SDOperand Addr, SDOperand &Op1, SDOperand &Op2); 80 81 SDOperand BuildSDIVSequence(SDNode *N); 82 SDOperand BuildUDIVSequence(SDNode *N); 83 84 /// InstructionSelectBasicBlock - This callback is invoked by 85 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 86 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) { 87 DEBUG(BB->dump()); 88 // Select target instructions for the DAG. 89 DAG.setRoot(Select(DAG.getRoot())); 90 CodeGenMap.clear(); 91 DAG.RemoveDeadNodes(); 92 93 // Emit machine code to BB. 94 ScheduleAndEmitDAG(DAG); 95 } 96 97 virtual const char *getPassName() const { 98 return "PowerPC DAG->DAG Pattern Instruction Selection"; 99 } 100 101// Include the pieces autogenerated from the target description. 102#include "PPC32GenDAGISel.inc" 103 }; 104} 105 106 107/// getGlobalBaseReg - Output the instructions required to put the 108/// base address to use for accessing globals into a register. 109/// 110SDOperand PPC32DAGToDAGISel::getGlobalBaseReg() { 111 if (!GlobalBaseReg) { 112 // Insert the set of GlobalBaseReg into the first MBB of the function 113 MachineBasicBlock &FirstMBB = BB->getParent()->front(); 114 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 115 SSARegMap *RegMap = BB->getParent()->getSSARegMap(); 116 GlobalBaseReg = RegMap->createVirtualRegister(PPC32::GPRCRegisterClass); 117 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR); 118 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg); 119 } 120 return CurDAG->getRegister(GlobalBaseReg, MVT::i32); 121} 122 123 124// isIntImmediate - This method tests to see if a constant operand. 125// If so Imm will receive the 32 bit value. 126static bool isIntImmediate(SDNode *N, unsigned& Imm) { 127 if (N->getOpcode() == ISD::Constant) { 128 Imm = cast<ConstantSDNode>(N)->getValue(); 129 return true; 130 } 131 return false; 132} 133 134// isOprShiftImm - Returns true if the specified operand is a shift opcode with 135// a immediate shift count less than 32. 136static bool isOprShiftImm(SDNode *N, unsigned& Opc, unsigned& SH) { 137 Opc = N->getOpcode(); 138 return (Opc == ISD::SHL || Opc == ISD::SRL || Opc == ISD::SRA) && 139 isIntImmediate(N->getOperand(1).Val, SH) && SH < 32; 140} 141 142// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s with 143// any number of 0s on either side. The 1s are allowed to wrap from LSB to 144// MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is 145// not, since all 1s are not contiguous. 146static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) { 147 if (isShiftedMask_32(Val)) { 148 // look for the first non-zero bit 149 MB = CountLeadingZeros_32(Val); 150 // look for the first zero bit after the run of ones 151 ME = CountLeadingZeros_32((Val - 1) ^ Val); 152 return true; 153 } else { 154 Val = ~Val; // invert mask 155 if (isShiftedMask_32(Val)) { 156 // effectively look for the first zero bit 157 ME = CountLeadingZeros_32(Val) - 1; 158 // effectively look for the first one bit after the run of zeros 159 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1; 160 return true; 161 } 162 } 163 // no run present 164 return false; 165} 166 167// isRotateAndMask - Returns true if Mask and Shift can be folded in to a rotate 168// and mask opcode and mask operation. 169static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask, 170 unsigned &SH, unsigned &MB, unsigned &ME) { 171 unsigned Shift = 32; 172 unsigned Indeterminant = ~0; // bit mask marking indeterminant results 173 unsigned Opcode = N->getOpcode(); 174 if (N->getNumOperands() != 2 || 175 !isIntImmediate(N->getOperand(1).Val, Shift) || (Shift > 31)) 176 return false; 177 178 if (Opcode == ISD::SHL) { 179 // apply shift left to mask if it comes first 180 if (IsShiftMask) Mask = Mask << Shift; 181 // determine which bits are made indeterminant by shift 182 Indeterminant = ~(0xFFFFFFFFu << Shift); 183 } else if (Opcode == ISD::SRA || Opcode == ISD::SRL) { 184 // apply shift right to mask if it comes first 185 if (IsShiftMask) Mask = Mask >> Shift; 186 // determine which bits are made indeterminant by shift 187 Indeterminant = ~(0xFFFFFFFFu >> Shift); 188 // adjust for the left rotate 189 Shift = 32 - Shift; 190 } else { 191 return false; 192 } 193 194 // if the mask doesn't intersect any Indeterminant bits 195 if (Mask && !(Mask & Indeterminant)) { 196 SH = Shift; 197 // make sure the mask is still a mask (wrap arounds may not be) 198 return isRunOfOnes(Mask, MB, ME); 199 } 200 return false; 201} 202 203// isOpcWithIntImmediate - This method tests to see if the node is a specific 204// opcode and that it has a immediate integer right operand. 205// If so Imm will receive the 32 bit value. 206static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { 207 return N->getOpcode() == Opc && isIntImmediate(N->getOperand(1).Val, Imm); 208} 209 210// isOprNot - Returns true if the specified operand is an xor with immediate -1. 211static bool isOprNot(SDNode *N) { 212 unsigned Imm; 213 return isOpcWithIntImmediate(N, ISD::XOR, Imm) && (signed)Imm == -1; 214} 215 216// Immediate constant composers. 217// Lo16 - grabs the lo 16 bits from a 32 bit constant. 218// Hi16 - grabs the hi 16 bits from a 32 bit constant. 219// HA16 - computes the hi bits required if the lo bits are add/subtracted in 220// arithmethically. 221static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; } 222static unsigned Hi16(unsigned x) { return Lo16(x >> 16); } 223static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); } 224 225// isIntImmediate - This method tests to see if a constant operand. 226// If so Imm will receive the 32 bit value. 227static bool isIntImmediate(SDOperand N, unsigned& Imm) { 228 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) { 229 Imm = (unsigned)CN->getSignExtended(); 230 return true; 231 } 232 return false; 233} 234 235/// SelectBitfieldInsert - turn an or of two masked values into 236/// the rotate left word immediate then mask insert (rlwimi) instruction. 237/// Returns true on success, false if the caller still needs to select OR. 238/// 239/// Patterns matched: 240/// 1. or shl, and 5. or and, and 241/// 2. or and, shl 6. or shl, shr 242/// 3. or shr, and 7. or shr, shl 243/// 4. or and, shr 244SDNode *PPC32DAGToDAGISel::SelectBitfieldInsert(SDNode *N) { 245 bool IsRotate = false; 246 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, SH = 0; 247 unsigned Value; 248 249 SDOperand Op0 = N->getOperand(0); 250 SDOperand Op1 = N->getOperand(1); 251 252 unsigned Op0Opc = Op0.getOpcode(); 253 unsigned Op1Opc = Op1.getOpcode(); 254 255 // Verify that we have the correct opcodes 256 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc) 257 return false; 258 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc) 259 return false; 260 261 // Generate Mask value for Target 262 if (isIntImmediate(Op0.getOperand(1), Value)) { 263 switch(Op0Opc) { 264 case ISD::SHL: TgtMask <<= Value; break; 265 case ISD::SRL: TgtMask >>= Value; break; 266 case ISD::AND: TgtMask &= Value; break; 267 } 268 } else { 269 return 0; 270 } 271 272 // Generate Mask value for Insert 273 if (!isIntImmediate(Op1.getOperand(1), Value)) 274 return 0; 275 276 switch(Op1Opc) { 277 case ISD::SHL: 278 SH = Value; 279 InsMask <<= SH; 280 if (Op0Opc == ISD::SRL) IsRotate = true; 281 break; 282 case ISD::SRL: 283 SH = Value; 284 InsMask >>= SH; 285 SH = 32-SH; 286 if (Op0Opc == ISD::SHL) IsRotate = true; 287 break; 288 case ISD::AND: 289 InsMask &= Value; 290 break; 291 } 292 293 // If both of the inputs are ANDs and one of them has a logical shift by 294 // constant as its input, make that AND the inserted value so that we can 295 // combine the shift into the rotate part of the rlwimi instruction 296 bool IsAndWithShiftOp = false; 297 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { 298 if (Op1.getOperand(0).getOpcode() == ISD::SHL || 299 Op1.getOperand(0).getOpcode() == ISD::SRL) { 300 if (isIntImmediate(Op1.getOperand(0).getOperand(1), Value)) { 301 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value; 302 IsAndWithShiftOp = true; 303 } 304 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL || 305 Op0.getOperand(0).getOpcode() == ISD::SRL) { 306 if (isIntImmediate(Op0.getOperand(0).getOperand(1), Value)) { 307 std::swap(Op0, Op1); 308 std::swap(TgtMask, InsMask); 309 SH = Op1.getOperand(0).getOpcode() == ISD::SHL ? Value : 32 - Value; 310 IsAndWithShiftOp = true; 311 } 312 } 313 } 314 315 // Verify that the Target mask and Insert mask together form a full word mask 316 // and that the Insert mask is a run of set bits (which implies both are runs 317 // of set bits). Given that, Select the arguments and generate the rlwimi 318 // instruction. 319 unsigned MB, ME; 320 if (((TgtMask & InsMask) == 0) && isRunOfOnes(InsMask, MB, ME)) { 321 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF; 322 bool Op0IsAND = Op0Opc == ISD::AND; 323 // Check for rotlwi / rotrwi here, a special case of bitfield insert 324 // where both bitfield halves are sourced from the same value. 325 if (IsRotate && fullMask && 326 N->getOperand(0).getOperand(0) == N->getOperand(1).getOperand(0)) { 327 Op0 = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, 328 Select(N->getOperand(0).getOperand(0)), 329 getI32Imm(SH), getI32Imm(0), getI32Imm(31)); 330 return Op0.Val; 331 } 332 SDOperand Tmp1 = (Op0IsAND && fullMask) ? Select(Op0.getOperand(0)) 333 : Select(Op0); 334 SDOperand Tmp2 = IsAndWithShiftOp ? Select(Op1.getOperand(0).getOperand(0)) 335 : Select(Op1.getOperand(0)); 336 Op0 = CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Tmp1, Tmp2, 337 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); 338 return Op0.Val; 339 } 340 return 0; 341} 342 343// SelectIntImmediateExpr - Choose code for integer operations with an immediate 344// operand. 345SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS, 346 unsigned OCHi, unsigned OCLo, 347 bool IsArithmetic, 348 bool Negate) { 349 // Check to make sure this is a constant. 350 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS); 351 // Exit if not a constant. 352 if (!CN) return 0; 353 // Extract immediate. 354 unsigned C = (unsigned)CN->getValue(); 355 // Negate if required (ISD::SUB). 356 if (Negate) C = -C; 357 // Get the hi and lo portions of constant. 358 unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C); 359 unsigned Lo = Lo16(C); 360 361 // If two instructions are needed and usage indicates it would be better to 362 // load immediate into a register, bail out. 363 if (Hi && Lo && CN->use_size() > 2) return false; 364 365 // Select the first operand. 366 SDOperand Opr0 = Select(LHS); 367 368 if (Lo) // Add in the lo-part. 369 Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo)); 370 if (Hi) // Add in the hi-part. 371 Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi)); 372 return Opr0.Val; 373} 374 375/// SelectAddr - Given the specified address, return the two operands for a 376/// load/store instruction, and return true if it should be an indexed [r+r] 377/// operation. 378bool PPC32DAGToDAGISel::SelectAddr(SDOperand Addr, SDOperand &Op1, 379 SDOperand &Op2) { 380 unsigned imm = 0; 381 if (Addr.getOpcode() == ISD::ADD) { 382 if (isIntImmediate(Addr.getOperand(1), imm) && isInt16(imm)) { 383 Op1 = getI32Imm(Lo16(imm)); 384 if (FrameIndexSDNode *FI = 385 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 386 ++FrameOff; 387 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32); 388 } else { 389 Op2 = Select(Addr.getOperand(0)); 390 } 391 return false; 392 } else { 393 Op1 = Select(Addr.getOperand(0)); 394 Op2 = Select(Addr.getOperand(1)); 395 return true; // [r+r] 396 } 397 } 398 399 // Now check if we're dealing with a global, and whether or not we should emit 400 // an optimized load or store for statics. 401 if (GlobalAddressSDNode *GN = dyn_cast<GlobalAddressSDNode>(Addr)) { 402 GlobalValue *GV = GN->getGlobal(); 403 if (!GV->hasWeakLinkage() && !GV->isExternal()) { 404 Op1 = CurDAG->getTargetGlobalAddress(GV, MVT::i32); 405 if (PICEnabled) 406 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), 407 Op1); 408 else 409 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1); 410 return false; 411 } 412 } else if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr)) { 413 Op1 = getI32Imm(0); 414 Op2 = CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32); 415 return false; 416 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Addr)) { 417 Op1 = Addr; 418 if (PICEnabled) 419 Op2 = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),Op1); 420 else 421 Op2 = CurDAG->getTargetNode(PPC::LIS, MVT::i32, Op1); 422 return false; 423 } 424 Op1 = getI32Imm(0); 425 Op2 = Select(Addr); 426 return false; 427} 428 429/// SelectCC - Select a comparison of the specified values with the specified 430/// condition code, returning the CR# of the expression. 431SDOperand PPC32DAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS, 432 ISD::CondCode CC) { 433 // Always select the LHS. 434 LHS = Select(LHS); 435 436 // Use U to determine whether the SETCC immediate range is signed or not. 437 if (MVT::isInteger(LHS.getValueType())) { 438 bool U = ISD::isUnsignedIntSetCC(CC); 439 unsigned Imm; 440 if (isIntImmediate(RHS, Imm) && 441 ((U && isUInt16(Imm)) || (!U && isInt16(Imm)))) 442 return CurDAG->getTargetNode(U ? PPC::CMPLWI : PPC::CMPWI, MVT::i32, 443 LHS, getI32Imm(Lo16(Imm))); 444 return CurDAG->getTargetNode(U ? PPC::CMPLW : PPC::CMPW, MVT::i32, 445 LHS, Select(RHS)); 446 } else { 447 return CurDAG->getTargetNode(PPC::FCMPU, MVT::i32, LHS, Select(RHS)); 448 } 449} 450 451/// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding 452/// to Condition. 453static unsigned getBCCForSetCC(ISD::CondCode CC) { 454 switch (CC) { 455 default: assert(0 && "Unknown condition!"); abort(); 456 case ISD::SETEQ: return PPC::BEQ; 457 case ISD::SETNE: return PPC::BNE; 458 case ISD::SETULT: 459 case ISD::SETLT: return PPC::BLT; 460 case ISD::SETULE: 461 case ISD::SETLE: return PPC::BLE; 462 case ISD::SETUGT: 463 case ISD::SETGT: return PPC::BGT; 464 case ISD::SETUGE: 465 case ISD::SETGE: return PPC::BGE; 466 } 467 return 0; 468} 469 470/// getCRIdxForSetCC - Return the index of the condition register field 471/// associated with the SetCC condition, and whether or not the field is 472/// treated as inverted. That is, lt = 0; ge = 0 inverted. 473static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) { 474 switch (CC) { 475 default: assert(0 && "Unknown condition!"); abort(); 476 case ISD::SETULT: 477 case ISD::SETLT: Inv = false; return 0; 478 case ISD::SETUGE: 479 case ISD::SETGE: Inv = true; return 0; 480 case ISD::SETUGT: 481 case ISD::SETGT: Inv = false; return 1; 482 case ISD::SETULE: 483 case ISD::SETLE: Inv = true; return 1; 484 case ISD::SETEQ: Inv = false; return 2; 485 case ISD::SETNE: Inv = true; return 2; 486 } 487 return 0; 488} 489 490// Structure used to return the necessary information to codegen an SDIV as 491// a multiply. 492struct ms { 493 int m; // magic number 494 int s; // shift amount 495}; 496 497struct mu { 498 unsigned int m; // magic number 499 int a; // add indicator 500 int s; // shift amount 501}; 502 503/// magic - calculate the magic numbers required to codegen an integer sdiv as 504/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 505/// or -1. 506static struct ms magic(int d) { 507 int p; 508 unsigned int ad, anc, delta, q1, r1, q2, r2, t; 509 const unsigned int two31 = 0x80000000U; 510 struct ms mag; 511 512 ad = abs(d); 513 t = two31 + ((unsigned int)d >> 31); 514 anc = t - 1 - t%ad; // absolute value of nc 515 p = 31; // initialize p 516 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 517 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 518 q2 = two31/ad; // initialize q2 = 2p/abs(d) 519 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 520 do { 521 p = p + 1; 522 q1 = 2*q1; // update q1 = 2p/abs(nc) 523 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 524 if (r1 >= anc) { // must be unsigned comparison 525 q1 = q1 + 1; 526 r1 = r1 - anc; 527 } 528 q2 = 2*q2; // update q2 = 2p/abs(d) 529 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 530 if (r2 >= ad) { // must be unsigned comparison 531 q2 = q2 + 1; 532 r2 = r2 - ad; 533 } 534 delta = ad - r2; 535 } while (q1 < delta || (q1 == delta && r1 == 0)); 536 537 mag.m = q2 + 1; 538 if (d < 0) mag.m = -mag.m; // resulting magic number 539 mag.s = p - 32; // resulting shift 540 return mag; 541} 542 543/// magicu - calculate the magic numbers required to codegen an integer udiv as 544/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 545static struct mu magicu(unsigned d) 546{ 547 int p; 548 unsigned int nc, delta, q1, r1, q2, r2; 549 struct mu magu; 550 magu.a = 0; // initialize "add" indicator 551 nc = - 1 - (-d)%d; 552 p = 31; // initialize p 553 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 554 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 555 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 556 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 557 do { 558 p = p + 1; 559 if (r1 >= nc - r1 ) { 560 q1 = 2*q1 + 1; // update q1 561 r1 = 2*r1 - nc; // update r1 562 } 563 else { 564 q1 = 2*q1; // update q1 565 r1 = 2*r1; // update r1 566 } 567 if (r2 + 1 >= d - r2) { 568 if (q2 >= 0x7FFFFFFF) magu.a = 1; 569 q2 = 2*q2 + 1; // update q2 570 r2 = 2*r2 + 1 - d; // update r2 571 } 572 else { 573 if (q2 >= 0x80000000) magu.a = 1; 574 q2 = 2*q2; // update q2 575 r2 = 2*r2 + 1; // update r2 576 } 577 delta = d - 1 - r2; 578 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 579 magu.m = q2 + 1; // resulting magic number 580 magu.s = p - 32; // resulting shift 581 return magu; 582} 583 584/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 585/// return a DAG expression to select that will generate the same value by 586/// multiplying by a magic number. See: 587/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 588SDOperand PPC32DAGToDAGISel::BuildSDIVSequence(SDNode *N) { 589 int d = (int)cast<ConstantSDNode>(N->getOperand(1))->getValue(); 590 ms magics = magic(d); 591 // Multiply the numerator (operand 0) by the magic value 592 SDOperand Q = CurDAG->getNode(ISD::MULHS, MVT::i32, N->getOperand(0), 593 CurDAG->getConstant(magics.m, MVT::i32)); 594 // If d > 0 and m < 0, add the numerator 595 if (d > 0 && magics.m < 0) 596 Q = CurDAG->getNode(ISD::ADD, MVT::i32, Q, N->getOperand(0)); 597 // If d < 0 and m > 0, subtract the numerator. 598 if (d < 0 && magics.m > 0) 599 Q = CurDAG->getNode(ISD::SUB, MVT::i32, Q, N->getOperand(0)); 600 // Shift right algebraic if shift value is nonzero 601 if (magics.s > 0) 602 Q = CurDAG->getNode(ISD::SRA, MVT::i32, Q, 603 CurDAG->getConstant(magics.s, MVT::i32)); 604 // Extract the sign bit and add it to the quotient 605 SDOperand T = 606 CurDAG->getNode(ISD::SRL, MVT::i32, Q, CurDAG->getConstant(31, MVT::i32)); 607 return CurDAG->getNode(ISD::ADD, MVT::i32, Q, T); 608} 609 610/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 611/// return a DAG expression to select that will generate the same value by 612/// multiplying by a magic number. See: 613/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 614SDOperand PPC32DAGToDAGISel::BuildUDIVSequence(SDNode *N) { 615 unsigned d = (unsigned)cast<ConstantSDNode>(N->getOperand(1))->getValue(); 616 mu magics = magicu(d); 617 // Multiply the numerator (operand 0) by the magic value 618 SDOperand Q = CurDAG->getNode(ISD::MULHU, MVT::i32, N->getOperand(0), 619 CurDAG->getConstant(magics.m, MVT::i32)); 620 if (magics.a == 0) { 621 return CurDAG->getNode(ISD::SRL, MVT::i32, Q, 622 CurDAG->getConstant(magics.s, MVT::i32)); 623 } else { 624 SDOperand NPQ = CurDAG->getNode(ISD::SUB, MVT::i32, N->getOperand(0), Q); 625 NPQ = CurDAG->getNode(ISD::SRL, MVT::i32, NPQ, 626 CurDAG->getConstant(1, MVT::i32)); 627 NPQ = CurDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q); 628 return CurDAG->getNode(ISD::SRL, MVT::i32, NPQ, 629 CurDAG->getConstant(magics.s-1, MVT::i32)); 630 } 631} 632 633// Select - Convert the specified operand from a target-independent to a 634// target-specific node if it hasn't already been changed. 635SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) { 636 SDNode *N = Op.Val; 637 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 638 N->getOpcode() < PPCISD::FIRST_NUMBER) 639 return Op; // Already selected. 640 641 switch (N->getOpcode()) { 642 default: break; 643 case ISD::TokenFactor: { 644 SDOperand New; 645 if (N->getNumOperands() == 2) { 646 SDOperand Op0 = Select(N->getOperand(0)); 647 SDOperand Op1 = Select(N->getOperand(1)); 648 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1); 649 } else { 650 std::vector<SDOperand> Ops; 651 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 652 Ops.push_back(Select(N->getOperand(i))); 653 New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops); 654 } 655 656 if (New.Val != N) { 657 CurDAG->ReplaceAllUsesWith(Op, New); 658 N = New.Val; 659 } 660 return SDOperand(N, 0); 661 } 662 case ISD::CopyFromReg: { 663 SDOperand Chain = Select(N->getOperand(0)); 664 if (Chain == N->getOperand(0)) return Op; // No change 665 SDOperand New = CurDAG->getCopyFromReg(Chain, 666 cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0)); 667 return New.getValue(Op.ResNo); 668 } 669 case ISD::CopyToReg: { 670 SDOperand Chain = Select(N->getOperand(0)); 671 SDOperand Reg = N->getOperand(1); 672 SDOperand Val = Select(N->getOperand(2)); 673 if (Chain != N->getOperand(0) || Val != N->getOperand(2)) { 674 SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other, 675 Chain, Reg, Val); 676 CurDAG->ReplaceAllUsesWith(Op, New); 677 N = New.Val; 678 } 679 return SDOperand(N, 0); 680 } 681 case ISD::Constant: { 682 assert(N->getValueType(0) == MVT::i32); 683 unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue(); 684 685 // NOTE: This doesn't use SelectNodeTo, because doing that will prevent 686 // folding shared immediates into other the second instruction that 687 // uses it. 688 if (isInt16(v)) 689 return CurDAG->getTargetNode(PPC::LI, MVT::i32, getI32Imm(v)); 690 691 unsigned Hi = Hi16(v); 692 unsigned Lo = Lo16(v); 693 694 if (!Lo) 695 return CurDAG->getTargetNode(PPC::LIS, MVT::i32, getI32Imm(Hi)); 696 697 SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32, getI32Imm(Hi)); 698 return CurDAG->getTargetNode(PPC::ORI, MVT::i32, Top, getI32Imm(Lo)); 699 } 700 case ISD::UNDEF: 701 if (N->getValueType(0) == MVT::i32) 702 CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_GPR, MVT::i32); 703 else 704 CurDAG->SelectNodeTo(N, PPC::IMPLICIT_DEF_FP, N->getValueType(0)); 705 return SDOperand(N, 0); 706 case ISD::FrameIndex: { 707 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 708 CurDAG->SelectNodeTo(N, PPC::ADDI, MVT::i32, 709 CurDAG->getTargetFrameIndex(FI, MVT::i32), 710 getI32Imm(0)); 711 return SDOperand(N, 0); 712 } 713 case ISD::ConstantPool: { 714 Constant *C = cast<ConstantPoolSDNode>(N)->get(); 715 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i32); 716 if (PICEnabled) 717 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(),CPI); 718 else 719 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, CPI); 720 CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, CPI); 721 return SDOperand(N, 0); 722 } 723 case ISD::GlobalAddress: { 724 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal(); 725 SDOperand Tmp; 726 SDOperand GA = CurDAG->getTargetGlobalAddress(GV, MVT::i32); 727 if (PICEnabled) 728 Tmp = CurDAG->getTargetNode(PPC::ADDIS, MVT::i32, getGlobalBaseReg(), GA); 729 else 730 Tmp = CurDAG->getTargetNode(PPC::LIS, MVT::i32, GA); 731 732 if (GV->hasWeakLinkage() || GV->isExternal()) 733 CurDAG->SelectNodeTo(N, PPC::LWZ, MVT::i32, GA, Tmp); 734 else 735 CurDAG->SelectNodeTo(N, PPC::LA, MVT::i32, Tmp, GA); 736 return SDOperand(N, 0); 737 } 738 case ISD::DYNAMIC_STACKALLOC: { 739 // FIXME: We are currently ignoring the requested alignment for handling 740 // greater than the stack alignment. This will need to be revisited at some 741 // point. Align = N.getOperand(2); 742 if (!isa<ConstantSDNode>(N->getOperand(2)) || 743 cast<ConstantSDNode>(N->getOperand(2))->getValue() != 0) { 744 std::cerr << "Cannot allocate stack object with greater alignment than" 745 << " the stack alignment yet!"; 746 abort(); 747 } 748 SDOperand Chain = Select(N->getOperand(0)); 749 SDOperand Amt = Select(N->getOperand(1)); 750 751 SDOperand R1Reg = CurDAG->getRegister(PPC::R1, MVT::i32); 752 753 SDOperand R1Val = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32); 754 Chain = R1Val.getValue(1); 755 756 // Subtract the amount (guaranteed to be a multiple of the stack alignment) 757 // from the stack pointer, giving us the result pointer. 758 SDOperand Result = CurDAG->getTargetNode(PPC::SUBF, MVT::i32, Amt, R1Val); 759 760 // Copy this result back into R1. 761 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R1Reg, Result); 762 763 // Copy this result back out of R1 to make sure we're not using the stack 764 // space without decrementing the stack pointer. 765 Result = CurDAG->getCopyFromReg(Chain, PPC::R1, MVT::i32); 766 767 // Finally, replace the DYNAMIC_STACKALLOC with the copyfromreg. 768 CurDAG->ReplaceAllUsesWith(N, Result.Val); 769 return SDOperand(Result.Val, Op.ResNo); 770 } 771 case ISD::SIGN_EXTEND_INREG: 772 switch(cast<VTSDNode>(N->getOperand(1))->getVT()) { 773 default: assert(0 && "Illegal type in SIGN_EXTEND_INREG"); break; 774 case MVT::i16: 775 CurDAG->SelectNodeTo(N, PPC::EXTSH, MVT::i32, Select(N->getOperand(0))); 776 break; 777 case MVT::i8: 778 CurDAG->SelectNodeTo(N, PPC::EXTSB, MVT::i32, Select(N->getOperand(0))); 779 break; 780 } 781 return SDOperand(N, 0); 782 case ISD::CTLZ: 783 assert(N->getValueType(0) == MVT::i32); 784 CurDAG->SelectNodeTo(N, PPC::CNTLZW, MVT::i32, Select(N->getOperand(0))); 785 return SDOperand(N, 0); 786 case PPCISD::FSEL: 787 CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0), 788 Select(N->getOperand(0)), 789 Select(N->getOperand(1)), 790 Select(N->getOperand(2))); 791 return SDOperand(N, 0); 792 case PPCISD::FCFID: 793 CurDAG->SelectNodeTo(N, PPC::FCFID, N->getValueType(0), 794 Select(N->getOperand(0))); 795 return SDOperand(N, 0); 796 case PPCISD::FCTIDZ: 797 CurDAG->SelectNodeTo(N, PPC::FCTIDZ, N->getValueType(0), 798 Select(N->getOperand(0))); 799 return SDOperand(N, 0); 800 case PPCISD::FCTIWZ: 801 CurDAG->SelectNodeTo(N, PPC::FCTIWZ, N->getValueType(0), 802 Select(N->getOperand(0))); 803 return SDOperand(N, 0); 804 case ISD::ADD: { 805 MVT::ValueType Ty = N->getValueType(0); 806 if (Ty == MVT::i32) { 807 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1), 808 PPC::ADDIS, PPC::ADDI, true)) { 809 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0)); 810 N = I; 811 } else { 812 CurDAG->SelectNodeTo(N, PPC::ADD, MVT::i32, Select(N->getOperand(0)), 813 Select(N->getOperand(1))); 814 } 815 return SDOperand(N, 0); 816 } 817 818 if (!NoExcessFPPrecision) { // Match FMA ops 819 if (N->getOperand(0).getOpcode() == ISD::MUL && 820 N->getOperand(0).Val->hasOneUse()) { 821 ++FusedFP; // Statistic 822 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty, 823 Select(N->getOperand(0).getOperand(0)), 824 Select(N->getOperand(0).getOperand(1)), 825 Select(N->getOperand(1))); 826 return SDOperand(N, 0); 827 } else if (N->getOperand(1).getOpcode() == ISD::MUL && 828 N->getOperand(1).hasOneUse()) { 829 ++FusedFP; // Statistic 830 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS, Ty, 831 Select(N->getOperand(1).getOperand(0)), 832 Select(N->getOperand(1).getOperand(1)), 833 Select(N->getOperand(0))); 834 return SDOperand(N, 0); 835 } 836 } 837 838 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS, Ty, 839 Select(N->getOperand(0)), Select(N->getOperand(1))); 840 return SDOperand(N, 0); 841 } 842 case ISD::SUB: { 843 MVT::ValueType Ty = N->getValueType(0); 844 if (Ty == MVT::i32) { 845 unsigned Imm; 846 if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) { 847 if (0 == Imm) 848 CurDAG->SelectNodeTo(N, PPC::NEG, Ty, Select(N->getOperand(1))); 849 else 850 CurDAG->SelectNodeTo(N, PPC::SUBFIC, Ty, Select(N->getOperand(1)), 851 getI32Imm(Lo16(Imm))); 852 return SDOperand(N, 0); 853 } 854 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1), 855 PPC::ADDIS, PPC::ADDI, true, true)) { 856 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0)); 857 N = I; 858 } else { 859 CurDAG->SelectNodeTo(N, PPC::SUBF, Ty, Select(N->getOperand(1)), 860 Select(N->getOperand(0))); 861 } 862 return SDOperand(N, 0); 863 } 864 865 if (!NoExcessFPPrecision) { // Match FMA ops 866 if (N->getOperand(0).getOpcode() == ISD::MUL && 867 N->getOperand(0).Val->hasOneUse()) { 868 ++FusedFP; // Statistic 869 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS, Ty, 870 Select(N->getOperand(0).getOperand(0)), 871 Select(N->getOperand(0).getOperand(1)), 872 Select(N->getOperand(1))); 873 return SDOperand(N, 0); 874 } else if (N->getOperand(1).getOpcode() == ISD::MUL && 875 N->getOperand(1).Val->hasOneUse()) { 876 ++FusedFP; // Statistic 877 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS, Ty, 878 Select(N->getOperand(1).getOperand(0)), 879 Select(N->getOperand(1).getOperand(1)), 880 Select(N->getOperand(0))); 881 return SDOperand(N, 0); 882 } 883 } 884 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS, Ty, 885 Select(N->getOperand(0)), 886 Select(N->getOperand(1))); 887 return SDOperand(N, 0); 888 } 889 case ISD::MUL: { 890 unsigned Imm, Opc; 891 if (isIntImmediate(N->getOperand(1), Imm) && isInt16(Imm)) { 892 CurDAG->SelectNodeTo(N, PPC::MULLI, MVT::i32, 893 Select(N->getOperand(0)), getI32Imm(Lo16(Imm))); 894 return SDOperand(N, 0); 895 } 896 switch (N->getValueType(0)) { 897 default: assert(0 && "Unhandled multiply type!"); 898 case MVT::i32: Opc = PPC::MULLW; break; 899 case MVT::f32: Opc = PPC::FMULS; break; 900 case MVT::f64: Opc = PPC::FMUL; break; 901 } 902 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)), 903 Select(N->getOperand(1))); 904 return SDOperand(N, 0); 905 } 906 case ISD::SDIV: { 907 unsigned Imm; 908 if (isIntImmediate(N->getOperand(1), Imm)) { 909 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { 910 SDOperand Op = 911 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, 912 Select(N->getOperand(0)), 913 getI32Imm(Log2_32(Imm))); 914 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 915 Op.getValue(0), Op.getValue(1)); 916 return SDOperand(N, 0); 917 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { 918 SDOperand Op = 919 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag, 920 Select(N->getOperand(0)), 921 getI32Imm(Log2_32(-Imm))); 922 SDOperand PT = 923 CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, Op.getValue(0), 924 Op.getValue(1)); 925 CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); 926 return SDOperand(N, 0); 927 } else if (Imm) { 928 SDOperand Result = Select(BuildSDIVSequence(N)); 929 assert(Result.ResNo == 0); 930 CurDAG->ReplaceAllUsesWith(Op, Result); 931 N = Result.Val; 932 return SDOperand(N, 0); 933 } 934 } 935 936 unsigned Opc; 937 switch (N->getValueType(0)) { 938 default: assert(0 && "Unknown type to ISD::SDIV"); 939 case MVT::i32: Opc = PPC::DIVW; break; 940 case MVT::f32: Opc = PPC::FDIVS; break; 941 case MVT::f64: Opc = PPC::FDIV; break; 942 } 943 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Select(N->getOperand(0)), 944 Select(N->getOperand(1))); 945 return SDOperand(N, 0); 946 } 947 case ISD::UDIV: { 948 // If this is a divide by constant, we can emit code using some magic 949 // constants to implement it as a multiply instead. 950 unsigned Imm; 951 if (isIntImmediate(N->getOperand(1), Imm) && Imm) { 952 SDOperand Result = Select(BuildUDIVSequence(N)); 953 assert(Result.ResNo == 0); 954 CurDAG->ReplaceAllUsesWith(Op, Result); 955 N = Result.Val; 956 return SDOperand(N, 0); 957 } 958 959 CurDAG->SelectNodeTo(N, PPC::DIVWU, MVT::i32, Select(N->getOperand(0)), 960 Select(N->getOperand(1))); 961 return SDOperand(N, 0); 962 } 963 case ISD::MULHS: 964 assert(N->getValueType(0) == MVT::i32); 965 CurDAG->SelectNodeTo(N, PPC::MULHW, MVT::i32, Select(N->getOperand(0)), 966 Select(N->getOperand(1))); 967 return SDOperand(N, 0); 968 case ISD::MULHU: 969 assert(N->getValueType(0) == MVT::i32); 970 CurDAG->SelectNodeTo(N, PPC::MULHWU, MVT::i32, Select(N->getOperand(0)), 971 Select(N->getOperand(1))); 972 return SDOperand(N, 0); 973 case ISD::AND: { 974 unsigned Imm; 975 // If this is an and of a value rotated between 0 and 31 bits and then and'd 976 // with a mask, emit rlwinm 977 if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) || 978 isShiftedMask_32(~Imm))) { 979 SDOperand Val; 980 unsigned SH, MB, ME; 981 if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) { 982 Val = Select(N->getOperand(0).getOperand(0)); 983 } else { 984 Val = Select(N->getOperand(0)); 985 isRunOfOnes(Imm, MB, ME); 986 SH = 0; 987 } 988 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Val, getI32Imm(SH), 989 getI32Imm(MB), getI32Imm(ME)); 990 return SDOperand(N, 0); 991 } 992 // Finally, check for the case where we are being asked to select 993 // and (not(a), b) or and (a, not(b)) which can be selected as andc. 994 if (isOprNot(N->getOperand(0).Val)) 995 CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(1)), 996 Select(N->getOperand(0).getOperand(0))); 997 else if (isOprNot(N->getOperand(1).Val)) 998 CurDAG->SelectNodeTo(N, PPC::ANDC, MVT::i32, Select(N->getOperand(0)), 999 Select(N->getOperand(1).getOperand(0))); 1000 else 1001 CurDAG->SelectNodeTo(N, PPC::AND, MVT::i32, Select(N->getOperand(0)), 1002 Select(N->getOperand(1))); 1003 return SDOperand(N, 0); 1004 } 1005 case ISD::OR: 1006 if (SDNode *I = SelectBitfieldInsert(N)) { 1007 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0)); 1008 N = I; 1009 return SDOperand(N, 0); 1010 } 1011 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), 1012 N->getOperand(1), 1013 PPC::ORIS, PPC::ORI)) { 1014 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0)); 1015 N = I; 1016 return SDOperand(N, 0); 1017 } 1018 // Finally, check for the case where we are being asked to select 1019 // 'or (not(a), b)' or 'or (a, not(b))' which can be selected as orc. 1020 if (isOprNot(N->getOperand(0).Val)) 1021 CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(1)), 1022 Select(N->getOperand(0).getOperand(0))); 1023 else if (isOprNot(N->getOperand(1).Val)) 1024 CurDAG->SelectNodeTo(N, PPC::ORC, MVT::i32, Select(N->getOperand(0)), 1025 Select(N->getOperand(1).getOperand(0))); 1026 else 1027 CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Select(N->getOperand(0)), 1028 Select(N->getOperand(1))); 1029 return SDOperand(N, 0); 1030 case ISD::XOR: 1031 // Check whether or not this node is a logical 'not'. This is represented 1032 // by llvm as a xor with the constant value -1 (all bits set). If this is a 1033 // 'not', then fold 'or' into 'nor', and so forth for the supported ops. 1034 if (isOprNot(N)) { 1035 unsigned Opc; 1036 SDOperand Val = Select(N->getOperand(0)); 1037 switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) { 1038 default: Opc = 0; break; 1039 case PPC::OR: Opc = PPC::NOR; break; 1040 case PPC::AND: Opc = PPC::NAND; break; 1041 case PPC::XOR: Opc = PPC::EQV; break; 1042 } 1043 if (Opc) 1044 CurDAG->SelectNodeTo(N, Opc, MVT::i32, Val.getOperand(0), 1045 Val.getOperand(1)); 1046 else 1047 CurDAG->SelectNodeTo(N, PPC::NOR, MVT::i32, Val, Val); 1048 return SDOperand(N, 0); 1049 } 1050 // If this is a xor with an immediate other than -1, then codegen it as high 1051 // and low 16 bit immediate xors. 1052 if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), 1053 N->getOperand(1), 1054 PPC::XORIS, PPC::XORI)) { 1055 CurDAG->ReplaceAllUsesWith(Op, SDOperand(I, 0)); 1056 N = I; 1057 return SDOperand(N, 0); 1058 } 1059 // Finally, check for the case where we are being asked to select 1060 // xor (not(a), b) which is equivalent to not(xor a, b), which is eqv 1061 if (isOprNot(N->getOperand(0).Val)) 1062 CurDAG->SelectNodeTo(N, PPC::EQV, MVT::i32, 1063 Select(N->getOperand(0).getOperand(0)), 1064 Select(N->getOperand(1))); 1065 else 1066 CurDAG->SelectNodeTo(N, PPC::XOR, MVT::i32, Select(N->getOperand(0)), 1067 Select(N->getOperand(1))); 1068 return SDOperand(N, 0); 1069 case ISD::SHL: { 1070 unsigned Imm, SH, MB, ME; 1071 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && 1072 isRotateAndMask(N, Imm, true, SH, MB, ME)) 1073 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 1074 Select(N->getOperand(0).getOperand(0)), 1075 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); 1076 else if (isIntImmediate(N->getOperand(1), Imm)) 1077 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)), 1078 getI32Imm(Imm), getI32Imm(0), getI32Imm(31-Imm)); 1079 else 1080 CurDAG->SelectNodeTo(N, PPC::SLW, MVT::i32, Select(N->getOperand(0)), 1081 Select(N->getOperand(1))); 1082 return SDOperand(N, 0); 1083 } 1084 case ISD::SRL: { 1085 unsigned Imm, SH, MB, ME; 1086 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && 1087 isRotateAndMask(N, Imm, true, SH, MB, ME)) 1088 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 1089 Select(N->getOperand(0).getOperand(0)), 1090 getI32Imm(SH & 0x1F), getI32Imm(MB), getI32Imm(ME)); 1091 else if (isIntImmediate(N->getOperand(1), Imm)) 1092 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Select(N->getOperand(0)), 1093 getI32Imm((32-Imm) & 0x1F), getI32Imm(Imm), 1094 getI32Imm(31)); 1095 else 1096 CurDAG->SelectNodeTo(N, PPC::SRW, MVT::i32, Select(N->getOperand(0)), 1097 Select(N->getOperand(1))); 1098 return SDOperand(N, 0); 1099 } 1100 case ISD::SRA: { 1101 unsigned Imm, SH, MB, ME; 1102 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) && 1103 isRotateAndMask(N, Imm, true, SH, MB, ME)) 1104 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, 1105 Select(N->getOperand(0).getOperand(0)), 1106 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME)); 1107 else if (isIntImmediate(N->getOperand(1), Imm)) 1108 CurDAG->SelectNodeTo(N, PPC::SRAWI, MVT::i32, Select(N->getOperand(0)), 1109 getI32Imm(Imm)); 1110 else 1111 CurDAG->SelectNodeTo(N, PPC::SRAW, MVT::i32, Select(N->getOperand(0)), 1112 Select(N->getOperand(1))); 1113 return SDOperand(N, 0); 1114 } 1115 case ISD::FABS: 1116 CurDAG->SelectNodeTo(N, PPC::FABS, N->getValueType(0), 1117 Select(N->getOperand(0))); 1118 return SDOperand(N, 0); 1119 case ISD::FP_EXTEND: 1120 assert(MVT::f64 == N->getValueType(0) && 1121 MVT::f32 == N->getOperand(0).getValueType() && "Illegal FP_EXTEND"); 1122 // We need to emit an FMR to make sure that the result has the right value 1123 // type. 1124 CurDAG->SelectNodeTo(N, PPC::FMR, MVT::f64, Select(N->getOperand(0))); 1125 return SDOperand(N, 0); 1126 case ISD::FP_ROUND: 1127 assert(MVT::f32 == N->getValueType(0) && 1128 MVT::f64 == N->getOperand(0).getValueType() && "Illegal FP_ROUND"); 1129 CurDAG->SelectNodeTo(N, PPC::FRSP, MVT::f32, Select(N->getOperand(0))); 1130 return SDOperand(N, 0); 1131 case ISD::FNEG: { 1132 SDOperand Val = Select(N->getOperand(0)); 1133 MVT::ValueType Ty = N->getValueType(0); 1134 if (Val.Val->hasOneUse()) { 1135 unsigned Opc; 1136 switch (Val.isTargetOpcode() ? Val.getTargetOpcode() : 0) { 1137 default: Opc = 0; break; 1138 case PPC::FABS: Opc = PPC::FNABS; break; 1139 case PPC::FMADD: Opc = PPC::FNMADD; break; 1140 case PPC::FMADDS: Opc = PPC::FNMADDS; break; 1141 case PPC::FMSUB: Opc = PPC::FNMSUB; break; 1142 case PPC::FMSUBS: Opc = PPC::FNMSUBS; break; 1143 } 1144 // If we inverted the opcode, then emit the new instruction with the 1145 // inverted opcode and the original instruction's operands. Otherwise, 1146 // fall through and generate a fneg instruction. 1147 if (Opc) { 1148 if (PPC::FNABS == Opc) 1149 CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0)); 1150 else 1151 CurDAG->SelectNodeTo(N, Opc, Ty, Val.getOperand(0), 1152 Val.getOperand(1), Val.getOperand(2)); 1153 return SDOperand(N, 0); 1154 } 1155 } 1156 CurDAG->SelectNodeTo(N, PPC::FNEG, Ty, Val); 1157 return SDOperand(N, 0); 1158 } 1159 case ISD::FSQRT: { 1160 MVT::ValueType Ty = N->getValueType(0); 1161 CurDAG->SelectNodeTo(N, Ty == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS, Ty, 1162 Select(N->getOperand(0))); 1163 return SDOperand(N, 0); 1164 } 1165 1166 case ISD::ADD_PARTS: { 1167 SDOperand LHSL = Select(N->getOperand(0)); 1168 SDOperand LHSH = Select(N->getOperand(1)); 1169 1170 unsigned Imm; 1171 bool ME = false, ZE = false; 1172 if (isIntImmediate(N->getOperand(3), Imm)) { 1173 ME = (signed)Imm == -1; 1174 ZE = Imm == 0; 1175 } 1176 1177 std::vector<SDOperand> Result; 1178 SDOperand CarryFromLo; 1179 if (isIntImmediate(N->getOperand(2), Imm) && 1180 ((signed)Imm >= -32768 || (signed)Imm < 32768)) { 1181 // Codegen the low 32 bits of the add. Interestingly, there is no 1182 // shifted form of add immediate carrying. 1183 CarryFromLo = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, 1184 LHSL, getI32Imm(Imm)); 1185 } else { 1186 CarryFromLo = CurDAG->getTargetNode(PPC::ADDC, MVT::i32, MVT::Flag, 1187 LHSL, Select(N->getOperand(2))); 1188 } 1189 CarryFromLo = CarryFromLo.getValue(1); 1190 1191 // Codegen the high 32 bits, adding zero, minus one, or the full value 1192 // along with the carry flag produced by addc/addic. 1193 SDOperand ResultHi; 1194 if (ZE) 1195 ResultHi = CurDAG->getTargetNode(PPC::ADDZE, MVT::i32, LHSH, CarryFromLo); 1196 else if (ME) 1197 ResultHi = CurDAG->getTargetNode(PPC::ADDME, MVT::i32, LHSH, CarryFromLo); 1198 else 1199 ResultHi = CurDAG->getTargetNode(PPC::ADDE, MVT::i32, LHSH, 1200 Select(N->getOperand(3)), CarryFromLo); 1201 Result.push_back(CarryFromLo.getValue(0)); 1202 Result.push_back(ResultHi); 1203 CurDAG->ReplaceAllUsesWith(N, Result); 1204 return Result[Op.ResNo]; 1205 } 1206 case ISD::SUB_PARTS: { 1207 SDOperand LHSL = Select(N->getOperand(0)); 1208 SDOperand LHSH = Select(N->getOperand(1)); 1209 SDOperand RHSL = Select(N->getOperand(2)); 1210 SDOperand RHSH = Select(N->getOperand(3)); 1211 1212 std::vector<SDOperand> Result; 1213 Result.push_back(CurDAG->getTargetNode(PPC::SUBFC, MVT::i32, MVT::Flag, 1214 RHSL, LHSL)); 1215 Result.push_back(CurDAG->getTargetNode(PPC::SUBFE, MVT::i32, RHSH, LHSH, 1216 Result[0].getValue(1))); 1217 CurDAG->ReplaceAllUsesWith(N, Result); 1218 return Result[Op.ResNo]; 1219 } 1220 1221 case ISD::LOAD: 1222 case ISD::EXTLOAD: 1223 case ISD::ZEXTLOAD: 1224 case ISD::SEXTLOAD: { 1225 SDOperand Op1, Op2; 1226 bool isIdx = SelectAddr(N->getOperand(1), Op1, Op2); 1227 1228 MVT::ValueType TypeBeingLoaded = (N->getOpcode() == ISD::LOAD) ? 1229 N->getValueType(0) : cast<VTSDNode>(N->getOperand(3))->getVT(); 1230 unsigned Opc; 1231 switch (TypeBeingLoaded) { 1232 default: N->dump(); assert(0 && "Cannot load this type!"); 1233 case MVT::i1: 1234 case MVT::i8: Opc = isIdx ? PPC::LBZX : PPC::LBZ; break; 1235 case MVT::i16: 1236 if (N->getOpcode() == ISD::SEXTLOAD) { // SEXT load? 1237 Opc = isIdx ? PPC::LHAX : PPC::LHA; 1238 } else { 1239 Opc = isIdx ? PPC::LHZX : PPC::LHZ; 1240 } 1241 break; 1242 case MVT::i32: Opc = isIdx ? PPC::LWZX : PPC::LWZ; break; 1243 case MVT::f32: Opc = isIdx ? PPC::LFSX : PPC::LFS; break; 1244 case MVT::f64: Opc = isIdx ? PPC::LFDX : PPC::LFD; break; 1245 } 1246 1247 CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), MVT::Other, 1248 Op1, Op2, Select(N->getOperand(0))); 1249 return SDOperand(N, Op.ResNo); 1250 } 1251 1252 case ISD::TRUNCSTORE: 1253 case ISD::STORE: { 1254 SDOperand AddrOp1, AddrOp2; 1255 bool isIdx = SelectAddr(N->getOperand(2), AddrOp1, AddrOp2); 1256 1257 unsigned Opc; 1258 if (N->getOpcode() == ISD::STORE) { 1259 switch (N->getOperand(1).getValueType()) { 1260 default: assert(0 && "unknown Type in store"); 1261 case MVT::i32: Opc = isIdx ? PPC::STWX : PPC::STW; break; 1262 case MVT::f64: Opc = isIdx ? PPC::STFDX : PPC::STFD; break; 1263 case MVT::f32: Opc = isIdx ? PPC::STFSX : PPC::STFS; break; 1264 } 1265 } else { //ISD::TRUNCSTORE 1266 switch(cast<VTSDNode>(N->getOperand(4))->getVT()) { 1267 default: assert(0 && "unknown Type in store"); 1268 case MVT::i8: Opc = isIdx ? PPC::STBX : PPC::STB; break; 1269 case MVT::i16: Opc = isIdx ? PPC::STHX : PPC::STH; break; 1270 } 1271 } 1272 1273 CurDAG->SelectNodeTo(N, Opc, MVT::Other, Select(N->getOperand(1)), 1274 AddrOp1, AddrOp2, Select(N->getOperand(0))); 1275 return SDOperand(N, 0); 1276 } 1277 1278 case ISD::SETCC: { 1279 unsigned Imm; 1280 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); 1281 if (isIntImmediate(N->getOperand(1), Imm)) { 1282 // We can codegen setcc op, imm very efficiently compared to a brcond. 1283 // Check for those cases here. 1284 // setcc op, 0 1285 if (Imm == 0) { 1286 SDOperand Op = Select(N->getOperand(0)); 1287 switch (CC) { 1288 default: assert(0 && "Unhandled SetCC condition"); abort(); 1289 case ISD::SETEQ: 1290 Op = CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op); 1291 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(27), 1292 getI32Imm(5), getI32Imm(31)); 1293 break; 1294 case ISD::SETNE: { 1295 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, 1296 Op, getI32Imm(~0U)); 1297 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1)); 1298 break; 1299 } 1300 case ISD::SETLT: 1301 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Op, getI32Imm(1), 1302 getI32Imm(31), getI32Imm(31)); 1303 break; 1304 case ISD::SETGT: { 1305 SDOperand T = CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op); 1306 T = CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op);; 1307 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, T, getI32Imm(1), 1308 getI32Imm(31), getI32Imm(31)); 1309 break; 1310 } 1311 } 1312 return SDOperand(N, 0); 1313 } else if (Imm == ~0U) { // setcc op, -1 1314 SDOperand Op = Select(N->getOperand(0)); 1315 switch (CC) { 1316 default: assert(0 && "Unhandled SetCC condition"); abort(); 1317 case ISD::SETEQ: 1318 Op = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, 1319 Op, getI32Imm(1)); 1320 CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, 1321 CurDAG->getTargetNode(PPC::LI, MVT::i32, 1322 getI32Imm(0)), 1323 Op.getValue(1)); 1324 break; 1325 case ISD::SETNE: { 1326 Op = CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op); 1327 SDOperand AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, 1328 Op, getI32Imm(~0U)); 1329 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, AD.getValue(1)); 1330 break; 1331 } 1332 case ISD::SETLT: { 1333 SDOperand AD = CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op, 1334 getI32Imm(1)); 1335 SDOperand AN = CurDAG->getTargetNode(PPC::AND, MVT::i32, AD, Op); 1336 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, AN, getI32Imm(1), 1337 getI32Imm(31), getI32Imm(31)); 1338 break; 1339 } 1340 case ISD::SETGT: 1341 Op = CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Op, getI32Imm(1), 1342 getI32Imm(31), getI32Imm(31)); 1343 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, getI32Imm(1)); 1344 break; 1345 } 1346 return SDOperand(N, 0); 1347 } 1348 } 1349 1350 bool Inv; 1351 unsigned Idx = getCRIdxForSetCC(CC, Inv); 1352 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); 1353 SDOperand IntCR; 1354 1355 // Force the ccreg into CR7. 1356 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); 1357 1358 std::vector<MVT::ValueType> VTs; 1359 VTs.push_back(MVT::Other); 1360 VTs.push_back(MVT::Flag); // NONSTANDARD CopyToReg node: defines a flag 1361 std::vector<SDOperand> Ops; 1362 Ops.push_back(CurDAG->getEntryNode()); 1363 Ops.push_back(CR7Reg); 1364 Ops.push_back(CCReg); 1365 CCReg = CurDAG->getNode(ISD::CopyToReg, VTs, Ops).getValue(1); 1366 1367 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor()) 1368 IntCR = CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg, CCReg); 1369 else 1370 IntCR = CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg); 1371 1372 if (!Inv) { 1373 CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, IntCR, 1374 getI32Imm(32-(3-Idx)), getI32Imm(31), getI32Imm(31)); 1375 } else { 1376 SDOperand Tmp = 1377 CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, IntCR, 1378 getI32Imm(32-(3-Idx)), getI32Imm(31),getI32Imm(31)); 1379 CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); 1380 } 1381 1382 return SDOperand(N, 0); 1383 } 1384 1385 case ISD::SELECT_CC: { 1386 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); 1387 1388 // handle the setcc cases here. select_cc lhs, 0, 1, 0, cc 1389 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 1390 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2))) 1391 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3))) 1392 if (N1C->isNullValue() && N3C->isNullValue() && 1393 N2C->getValue() == 1ULL && CC == ISD::SETNE) { 1394 SDOperand LHS = Select(N->getOperand(0)); 1395 SDOperand Tmp = 1396 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag, 1397 LHS, getI32Imm(~0U)); 1398 CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, Tmp, LHS, 1399 Tmp.getValue(1)); 1400 return SDOperand(N, 0); 1401 } 1402 1403 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC); 1404 unsigned BROpc = getBCCForSetCC(CC); 1405 1406 bool isFP = MVT::isFloatingPoint(N->getValueType(0)); 1407 unsigned SelectCCOp = isFP ? PPC::SELECT_CC_FP : PPC::SELECT_CC_Int; 1408 CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), CCReg, 1409 Select(N->getOperand(2)), Select(N->getOperand(3)), 1410 getI32Imm(BROpc)); 1411 return SDOperand(N, 0); 1412 } 1413 1414 case ISD::CALLSEQ_START: 1415 case ISD::CALLSEQ_END: { 1416 unsigned Amt = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 1417 unsigned Opc = N->getOpcode() == ISD::CALLSEQ_START ? 1418 PPC::ADJCALLSTACKDOWN : PPC::ADJCALLSTACKUP; 1419 CurDAG->SelectNodeTo(N, Opc, MVT::Other, 1420 getI32Imm(Amt), Select(N->getOperand(0))); 1421 return SDOperand(N, 0); 1422 } 1423 case ISD::CALL: 1424 case ISD::TAILCALL: { 1425 SDOperand Chain = Select(N->getOperand(0)); 1426 1427 unsigned CallOpcode; 1428 std::vector<SDOperand> CallOperands; 1429 1430 if (GlobalAddressSDNode *GASD = 1431 dyn_cast<GlobalAddressSDNode>(N->getOperand(1))) { 1432 CallOpcode = PPC::CALLpcrel; 1433 CallOperands.push_back(CurDAG->getTargetGlobalAddress(GASD->getGlobal(), 1434 MVT::i32)); 1435 } else if (ExternalSymbolSDNode *ESSDN = 1436 dyn_cast<ExternalSymbolSDNode>(N->getOperand(1))) { 1437 CallOpcode = PPC::CALLpcrel; 1438 CallOperands.push_back(N->getOperand(1)); 1439 } else { 1440 // Copy the callee address into the CTR register. 1441 SDOperand Callee = Select(N->getOperand(1)); 1442 Chain = CurDAG->getTargetNode(PPC::MTCTR, MVT::Other, Callee, Chain); 1443 1444 // Copy the callee address into R12 on darwin. 1445 SDOperand R12 = CurDAG->getRegister(PPC::R12, MVT::i32); 1446 Chain = CurDAG->getNode(ISD::CopyToReg, MVT::Other, Chain, R12, Callee); 1447 1448 CallOperands.push_back(getI32Imm(20)); // Information to encode indcall 1449 CallOperands.push_back(getI32Imm(0)); // Information to encode indcall 1450 CallOperands.push_back(R12); 1451 CallOpcode = PPC::CALLindirect; 1452 } 1453 1454 unsigned GPR_idx = 0, FPR_idx = 0; 1455 static const unsigned GPR[] = { 1456 PPC::R3, PPC::R4, PPC::R5, PPC::R6, 1457 PPC::R7, PPC::R8, PPC::R9, PPC::R10, 1458 }; 1459 static const unsigned FPR[] = { 1460 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7, 1461 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13 1462 }; 1463 1464 SDOperand InFlag; // Null incoming flag value. 1465 1466 for (unsigned i = 2, e = N->getNumOperands(); i != e; ++i) { 1467 unsigned DestReg = 0; 1468 MVT::ValueType RegTy = N->getOperand(i).getValueType(); 1469 if (RegTy == MVT::i32) { 1470 assert(GPR_idx < 8 && "Too many int args"); 1471 DestReg = GPR[GPR_idx++]; 1472 } else { 1473 assert(MVT::isFloatingPoint(N->getOperand(i).getValueType()) && 1474 "Unpromoted integer arg?"); 1475 assert(FPR_idx < 13 && "Too many fp args"); 1476 DestReg = FPR[FPR_idx++]; 1477 } 1478 1479 if (N->getOperand(i).getOpcode() != ISD::UNDEF) { 1480 SDOperand Val = Select(N->getOperand(i)); 1481 Chain = CurDAG->getCopyToReg(Chain, DestReg, Val, InFlag); 1482 InFlag = Chain.getValue(1); 1483 CallOperands.push_back(CurDAG->getRegister(DestReg, RegTy)); 1484 } 1485 } 1486 1487 // Finally, once everything is in registers to pass to the call, emit the 1488 // call itself. 1489 if (InFlag.Val) 1490 CallOperands.push_back(InFlag); // Strong dep on register copies. 1491 else 1492 CallOperands.push_back(Chain); // Weak dep on whatever occurs before 1493 Chain = CurDAG->getTargetNode(CallOpcode, MVT::Other, MVT::Flag, 1494 CallOperands); 1495 1496 std::vector<SDOperand> CallResults; 1497 1498 // If the call has results, copy the values out of the ret val registers. 1499 switch (N->getValueType(0)) { 1500 default: assert(0 && "Unexpected ret value!"); 1501 case MVT::Other: break; 1502 case MVT::i32: 1503 if (N->getValueType(1) == MVT::i32) { 1504 Chain = CurDAG->getCopyFromReg(Chain, PPC::R4, MVT::i32, 1505 Chain.getValue(1)).getValue(1); 1506 CallResults.push_back(Chain.getValue(0)); 1507 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32, 1508 Chain.getValue(1)).getValue(1); 1509 CallResults.push_back(Chain.getValue(0)); 1510 } else { 1511 Chain = CurDAG->getCopyFromReg(Chain, PPC::R3, MVT::i32, 1512 Chain.getValue(1)).getValue(1); 1513 CallResults.push_back(Chain.getValue(0)); 1514 } 1515 break; 1516 case MVT::f32: 1517 case MVT::f64: 1518 Chain = CurDAG->getCopyFromReg(Chain, PPC::F1, N->getValueType(0), 1519 Chain.getValue(1)).getValue(1); 1520 CallResults.push_back(Chain.getValue(0)); 1521 break; 1522 } 1523 1524 CallResults.push_back(Chain); 1525 CurDAG->ReplaceAllUsesWith(N, CallResults); 1526 return CallResults[Op.ResNo]; 1527 } 1528 case ISD::RET: { 1529 SDOperand Chain = Select(N->getOperand(0)); // Token chain. 1530 1531 if (N->getNumOperands() == 2) { 1532 SDOperand Val = Select(N->getOperand(1)); 1533 if (N->getOperand(1).getValueType() == MVT::i32) { 1534 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val); 1535 } else { 1536 assert(MVT::isFloatingPoint(N->getOperand(1).getValueType())); 1537 Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val); 1538 } 1539 } else if (N->getNumOperands() > 1) { 1540 assert(N->getOperand(1).getValueType() == MVT::i32 && 1541 N->getOperand(2).getValueType() == MVT::i32 && 1542 N->getNumOperands() == 3 && "Unknown two-register ret value!"); 1543 Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Select(N->getOperand(1))); 1544 Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Select(N->getOperand(2))); 1545 } 1546 1547 // Finally, select this to a blr (return) instruction. 1548 CurDAG->SelectNodeTo(N, PPC::BLR, MVT::Other, Chain); 1549 return SDOperand(N, 0); 1550 } 1551 case ISD::BR: 1552 CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(1), 1553 Select(N->getOperand(0))); 1554 return SDOperand(N, 0); 1555 case ISD::BR_CC: 1556 case ISD::BRTWOWAY_CC: { 1557 SDOperand Chain = Select(N->getOperand(0)); 1558 MachineBasicBlock *Dest = 1559 cast<BasicBlockSDNode>(N->getOperand(4))->getBasicBlock(); 1560 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); 1561 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC); 1562 unsigned Opc = getBCCForSetCC(CC); 1563 1564 // If this is a two way branch, then grab the fallthrough basic block 1565 // argument and build a PowerPC branch pseudo-op, suitable for long branch 1566 // conversion if necessary by the branch selection pass. Otherwise, emit a 1567 // standard conditional branch. 1568 if (N->getOpcode() == ISD::BRTWOWAY_CC) { 1569 MachineBasicBlock *Fallthrough = 1570 cast<BasicBlockSDNode>(N->getOperand(5))->getBasicBlock(); 1571 SDOperand CB = CurDAG->getTargetNode(PPC::COND_BRANCH, MVT::Other, 1572 CondCode, getI32Imm(Opc), 1573 N->getOperand(4), N->getOperand(5), 1574 Chain); 1575 CurDAG->SelectNodeTo(N, PPC::B, MVT::Other, N->getOperand(5), CB); 1576 } else { 1577 // Iterate to the next basic block 1578 ilist<MachineBasicBlock>::iterator It = BB; 1579 ++It; 1580 1581 // If the fallthrough path is off the end of the function, which would be 1582 // undefined behavior, set it to be the same as the current block because 1583 // we have nothing better to set it to, and leaving it alone will cause 1584 // the PowerPC Branch Selection pass to crash. 1585 if (It == BB->getParent()->end()) It = Dest; 1586 CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, CondCode, 1587 getI32Imm(Opc), N->getOperand(4), 1588 CurDAG->getBasicBlock(It), Chain); 1589 } 1590 return SDOperand(N, 0); 1591 } 1592 } 1593 1594 return SelectCode(Op); 1595} 1596 1597 1598/// createPPC32ISelDag - This pass converts a legalized DAG into a 1599/// PowerPC-specific DAG, ready for instruction scheduling. 1600/// 1601FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) { 1602 return new PPC32DAGToDAGISel(TM); 1603} 1604 1605