PPCInstrInfo.cpp revision 0965217e74fe07f1451350a80114ab566ced5de0 
1//===- PPCInstrInfo.cpp - PowerPC32 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the PowerPC implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCInstrInfo.h"
15#include "PPCInstrBuilder.h"
16#include "PPCMachineFunctionInfo.h"
17#include "PPCPredicates.h"
18#include "PPCGenInstrInfo.inc"
19#include "PPCTargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/Support/CommandLine.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
26#include "llvm/MC/MCAsmInfo.h"
27
28namespace llvm {
29extern cl::opt<bool> EnablePPC32RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
30extern cl::opt<bool> EnablePPC64RS;  // FIXME (64-bit): See PPCRegisterInfo.cpp.
31}
32
33using namespace llvm;
34
35PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
36  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
37    RI(*TM.getSubtargetImpl(), *this) {}
38
39bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
40                               unsigned& sourceReg,
41                               unsigned& destReg,
42                               unsigned& sourceSubIdx,
43                               unsigned& destSubIdx) const {
44  sourceSubIdx = destSubIdx = 0; // No sub-registers.
45
46  unsigned oc = MI.getOpcode();
47  if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
48      oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
49    assert(MI.getNumOperands() >= 3 &&
50           MI.getOperand(0).isReg() &&
51           MI.getOperand(1).isReg() &&
52           MI.getOperand(2).isReg() &&
53           "invalid PPC OR instruction!");
54    if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
55      sourceReg = MI.getOperand(1).getReg();
56      destReg = MI.getOperand(0).getReg();
57      return true;
58    }
59  } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
60    assert(MI.getNumOperands() >= 3 &&
61           MI.getOperand(0).isReg() &&
62           MI.getOperand(2).isImm() &&
63           "invalid PPC ADDI instruction!");
64    if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
65      sourceReg = MI.getOperand(1).getReg();
66      destReg = MI.getOperand(0).getReg();
67      return true;
68    }
69  } else if (oc == PPC::ORI) {             // ori r1, r2, 0
70    assert(MI.getNumOperands() >= 3 &&
71           MI.getOperand(0).isReg() &&
72           MI.getOperand(1).isReg() &&
73           MI.getOperand(2).isImm() &&
74           "invalid PPC ORI instruction!");
75    if (MI.getOperand(2).getImm() == 0) {
76      sourceReg = MI.getOperand(1).getReg();
77      destReg = MI.getOperand(0).getReg();
78      return true;
79    }
80  } else if (oc == PPC::FMR || oc == PPC::FMRSD) { // fmr r1, r2
81    assert(MI.getNumOperands() >= 2 &&
82           MI.getOperand(0).isReg() &&
83           MI.getOperand(1).isReg() &&
84           "invalid PPC FMR instruction");
85    sourceReg = MI.getOperand(1).getReg();
86    destReg = MI.getOperand(0).getReg();
87    return true;
88  } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
89    assert(MI.getNumOperands() >= 2 &&
90           MI.getOperand(0).isReg() &&
91           MI.getOperand(1).isReg() &&
92           "invalid PPC MCRF instruction");
93    sourceReg = MI.getOperand(1).getReg();
94    destReg = MI.getOperand(0).getReg();
95    return true;
96  }
97  return false;
98}
99
100unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
101                                           int &FrameIndex) const {
102  switch (MI->getOpcode()) {
103  default: break;
104  case PPC::LD:
105  case PPC::LWZ:
106  case PPC::LFS:
107  case PPC::LFD:
108    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
109        MI->getOperand(2).isFI()) {
110      FrameIndex = MI->getOperand(2).getIndex();
111      return MI->getOperand(0).getReg();
112    }
113    break;
114  }
115  return 0;
116}
117
118unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
119                                          int &FrameIndex) const {
120  switch (MI->getOpcode()) {
121  default: break;
122  case PPC::STD:
123  case PPC::STW:
124  case PPC::STFS:
125  case PPC::STFD:
126    if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
127        MI->getOperand(2).isFI()) {
128      FrameIndex = MI->getOperand(2).getIndex();
129      return MI->getOperand(0).getReg();
130    }
131    break;
132  }
133  return 0;
134}
135
136// commuteInstruction - We can commute rlwimi instructions, but only if the
137// rotate amt is zero.  We also have to munge the immediates a bit.
138MachineInstr *
139PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
140  MachineFunction &MF = *MI->getParent()->getParent();
141
142  // Normal instructions can be commuted the obvious way.
143  if (MI->getOpcode() != PPC::RLWIMI)
144    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
145
146  // Cannot commute if it has a non-zero rotate count.
147  if (MI->getOperand(3).getImm() != 0)
148    return 0;
149
150  // If we have a zero rotate count, we have:
151  //   M = mask(MB,ME)
152  //   Op0 = (Op1 & ~M) | (Op2 & M)
153  // Change this to:
154  //   M = mask((ME+1)&31, (MB-1)&31)
155  //   Op0 = (Op2 & ~M) | (Op1 & M)
156
157  // Swap op1/op2
158  unsigned Reg0 = MI->getOperand(0).getReg();
159  unsigned Reg1 = MI->getOperand(1).getReg();
160  unsigned Reg2 = MI->getOperand(2).getReg();
161  bool Reg1IsKill = MI->getOperand(1).isKill();
162  bool Reg2IsKill = MI->getOperand(2).isKill();
163  bool ChangeReg0 = false;
164  // If machine instrs are no longer in two-address forms, update
165  // destination register as well.
166  if (Reg0 == Reg1) {
167    // Must be two address instruction!
168    assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
169           "Expecting a two-address instruction!");
170    Reg2IsKill = false;
171    ChangeReg0 = true;
172  }
173
174  // Masks.
175  unsigned MB = MI->getOperand(4).getImm();
176  unsigned ME = MI->getOperand(5).getImm();
177
178  if (NewMI) {
179    // Create a new instruction.
180    unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
181    bool Reg0IsDead = MI->getOperand(0).isDead();
182    return BuildMI(MF, MI->getDebugLoc(), MI->getDesc())
183      .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
184      .addReg(Reg2, getKillRegState(Reg2IsKill))
185      .addReg(Reg1, getKillRegState(Reg1IsKill))
186      .addImm((ME+1) & 31)
187      .addImm((MB-1) & 31);
188  }
189
190  if (ChangeReg0)
191    MI->getOperand(0).setReg(Reg2);
192  MI->getOperand(2).setReg(Reg1);
193  MI->getOperand(1).setReg(Reg2);
194  MI->getOperand(2).setIsKill(Reg1IsKill);
195  MI->getOperand(1).setIsKill(Reg2IsKill);
196
197  // Swap the mask around.
198  MI->getOperand(4).setImm((ME+1) & 31);
199  MI->getOperand(5).setImm((MB-1) & 31);
200  return MI;
201}
202
203void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
204                              MachineBasicBlock::iterator MI) const {
205  DebugLoc DL;
206  if (MI != MBB.end()) DL = MI->getDebugLoc();
207
208  BuildMI(MBB, MI, DL, get(PPC::NOP));
209}
210
211
212// Branch analysis.
213bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
214                                 MachineBasicBlock *&FBB,
215                                 SmallVectorImpl<MachineOperand> &Cond,
216                                 bool AllowModify) const {
217  // If the block has no terminators, it just falls into the block after it.
218  MachineBasicBlock::iterator I = MBB.end();
219  if (I == MBB.begin())
220    return false;
221  --I;
222  while (I->isDebugValue()) {
223    if (I == MBB.begin())
224      return false;
225    --I;
226  }
227  if (!isUnpredicatedTerminator(I))
228    return false;
229
230  // Get the last instruction in the block.
231  MachineInstr *LastInst = I;
232
233  // If there is only one terminator instruction, process it.
234  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
235    if (LastInst->getOpcode() == PPC::B) {
236      if (!LastInst->getOperand(0).isMBB())
237        return true;
238      TBB = LastInst->getOperand(0).getMBB();
239      return false;
240    } else if (LastInst->getOpcode() == PPC::BCC) {
241      if (!LastInst->getOperand(2).isMBB())
242        return true;
243      // Block ends with fall-through condbranch.
244      TBB = LastInst->getOperand(2).getMBB();
245      Cond.push_back(LastInst->getOperand(0));
246      Cond.push_back(LastInst->getOperand(1));
247      return false;
248    }
249    // Otherwise, don't know what this is.
250    return true;
251  }
252
253  // Get the instruction before it if it's a terminator.
254  MachineInstr *SecondLastInst = I;
255
256  // If there are three terminators, we don't know what sort of block this is.
257  if (SecondLastInst && I != MBB.begin() &&
258      isUnpredicatedTerminator(--I))
259    return true;
260
261  // If the block ends with PPC::B and PPC:BCC, handle it.
262  if (SecondLastInst->getOpcode() == PPC::BCC &&
263      LastInst->getOpcode() == PPC::B) {
264    if (!SecondLastInst->getOperand(2).isMBB() ||
265        !LastInst->getOperand(0).isMBB())
266      return true;
267    TBB =  SecondLastInst->getOperand(2).getMBB();
268    Cond.push_back(SecondLastInst->getOperand(0));
269    Cond.push_back(SecondLastInst->getOperand(1));
270    FBB = LastInst->getOperand(0).getMBB();
271    return false;
272  }
273
274  // If the block ends with two PPC:Bs, handle it.  The second one is not
275  // executed, so remove it.
276  if (SecondLastInst->getOpcode() == PPC::B &&
277      LastInst->getOpcode() == PPC::B) {
278    if (!SecondLastInst->getOperand(0).isMBB())
279      return true;
280    TBB = SecondLastInst->getOperand(0).getMBB();
281    I = LastInst;
282    if (AllowModify)
283      I->eraseFromParent();
284    return false;
285  }
286
287  // Otherwise, can't handle this.
288  return true;
289}
290
291unsigned PPCInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
292  MachineBasicBlock::iterator I = MBB.end();
293  if (I == MBB.begin()) return 0;
294  --I;
295  while (I->isDebugValue()) {
296    if (I == MBB.begin())
297      return 0;
298    --I;
299  }
300  if (I->getOpcode() != PPC::B && I->getOpcode() != PPC::BCC)
301    return 0;
302
303  // Remove the branch.
304  I->eraseFromParent();
305
306  I = MBB.end();
307
308  if (I == MBB.begin()) return 1;
309  --I;
310  if (I->getOpcode() != PPC::BCC)
311    return 1;
312
313  // Remove the branch.
314  I->eraseFromParent();
315  return 2;
316}
317
318unsigned
319PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
320                           MachineBasicBlock *FBB,
321                           const SmallVectorImpl<MachineOperand> &Cond) const {
322  // FIXME this should probably have a DebugLoc argument
323  DebugLoc dl;
324  // Shouldn't be a fall through.
325  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
326  assert((Cond.size() == 2 || Cond.size() == 0) &&
327         "PPC branch conditions have two components!");
328
329  // One-way branch.
330  if (FBB == 0) {
331    if (Cond.empty())   // Unconditional branch
332      BuildMI(&MBB, dl, get(PPC::B)).addMBB(TBB);
333    else                // Conditional branch
334      BuildMI(&MBB, dl, get(PPC::BCC))
335        .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
336    return 1;
337  }
338
339  // Two-way Conditional Branch.
340  BuildMI(&MBB, dl, get(PPC::BCC))
341    .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
342  BuildMI(&MBB, dl, get(PPC::B)).addMBB(FBB);
343  return 2;
344}
345
346bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
347                                   MachineBasicBlock::iterator MI,
348                                   unsigned DestReg, unsigned SrcReg,
349                                   const TargetRegisterClass *DestRC,
350                                   const TargetRegisterClass *SrcRC) const {
351  if (DestRC != SrcRC) {
352    // Not yet supported!
353    return false;
354  }
355
356  DebugLoc DL;
357  if (MI != MBB.end()) DL = MI->getDebugLoc();
358
359  if (DestRC == PPC::GPRCRegisterClass) {
360    BuildMI(MBB, MI, DL, get(PPC::OR), DestReg).addReg(SrcReg).addReg(SrcReg);
361  } else if (DestRC == PPC::G8RCRegisterClass) {
362    BuildMI(MBB, MI, DL, get(PPC::OR8), DestReg).addReg(SrcReg).addReg(SrcReg);
363  } else if (DestRC == PPC::F4RCRegisterClass ||
364             DestRC == PPC::F8RCRegisterClass) {
365    BuildMI(MBB, MI, DL, get(PPC::FMR), DestReg).addReg(SrcReg);
366  } else if (DestRC == PPC::CRRCRegisterClass) {
367    BuildMI(MBB, MI, DL, get(PPC::MCRF), DestReg).addReg(SrcReg);
368  } else if (DestRC == PPC::VRRCRegisterClass) {
369    BuildMI(MBB, MI, DL, get(PPC::VOR), DestReg).addReg(SrcReg).addReg(SrcReg);
370  } else if (DestRC == PPC::CRBITRCRegisterClass) {
371    BuildMI(MBB, MI, DL, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
372  } else {
373    // Attempt to copy register that is not GPR or FPR
374    return false;
375  }
376
377  return true;
378}
379
380bool
381PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
382                                  unsigned SrcReg, bool isKill,
383                                  int FrameIdx,
384                                  const TargetRegisterClass *RC,
385                                  SmallVectorImpl<MachineInstr*> &NewMIs) const{
386  DebugLoc DL;
387  if (RC == PPC::GPRCRegisterClass) {
388    if (SrcReg != PPC::LR) {
389      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
390                                         .addReg(SrcReg,
391                                                 getKillRegState(isKill)),
392                                         FrameIdx));
393    } else {
394      // FIXME: this spills LR immediately to memory in one step.  To do this,
395      // we use R11, which we know cannot be used in the prolog/epilog.  This is
396      // a hack.
397      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11));
398      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
399                                         .addReg(PPC::R11,
400                                                 getKillRegState(isKill)),
401                                         FrameIdx));
402    }
403  } else if (RC == PPC::G8RCRegisterClass) {
404    if (SrcReg != PPC::LR8) {
405      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
406                                         .addReg(SrcReg,
407                                                 getKillRegState(isKill)),
408                                         FrameIdx));
409    } else {
410      // FIXME: this spills LR immediately to memory in one step.  To do this,
411      // we use R11, which we know cannot be used in the prolog/epilog.  This is
412      // a hack.
413      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11));
414      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD))
415                                         .addReg(PPC::X11,
416                                                 getKillRegState(isKill)),
417                                         FrameIdx));
418    }
419  } else if (RC == PPC::F8RCRegisterClass) {
420    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD))
421                                       .addReg(SrcReg,
422                                               getKillRegState(isKill)),
423                                       FrameIdx));
424  } else if (RC == PPC::F4RCRegisterClass) {
425    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS))
426                                       .addReg(SrcReg,
427                                               getKillRegState(isKill)),
428                                       FrameIdx));
429  } else if (RC == PPC::CRRCRegisterClass) {
430    if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
431        (EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
432      // FIXME (64-bit): Enable
433      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR))
434                                         .addReg(SrcReg,
435                                                 getKillRegState(isKill)),
436                                         FrameIdx));
437      return true;
438    } else {
439      // FIXME: We need a scatch reg here.  The trouble with using R0 is that
440      // it's possible for the stack frame to be so big the save location is
441      // out of range of immediate offsets, necessitating another register.
442      // We hack this on Darwin by reserving R2.  It's probably broken on Linux
443      // at the moment.
444
445      // We need to store the CR in the low 4-bits of the saved value.  First,
446      // issue a MFCR to save all of the CRBits.
447      unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
448                                                           PPC::R2 : PPC::R0;
449      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFCR), ScratchReg));
450
451      // If the saved register wasn't CR0, shift the bits left so that they are
452      // in CR0's slot.
453      if (SrcReg != PPC::CR0) {
454        unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
455        // rlwinm scratch, scratch, ShiftBits, 0, 31.
456        NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
457                       .addReg(ScratchReg).addImm(ShiftBits)
458                       .addImm(0).addImm(31));
459      }
460
461      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW))
462                                         .addReg(ScratchReg,
463                                                 getKillRegState(isKill)),
464                                         FrameIdx));
465    }
466  } else if (RC == PPC::CRBITRCRegisterClass) {
467    // FIXME: We use CRi here because there is no mtcrf on a bit. Since the
468    // backend currently only uses CR1EQ as an individual bit, this should
469    // not cause any bug. If we need other uses of CR bits, the following
470    // code may be invalid.
471    unsigned Reg = 0;
472    if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
473        SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
474      Reg = PPC::CR0;
475    else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
476             SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
477      Reg = PPC::CR1;
478    else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
479             SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
480      Reg = PPC::CR2;
481    else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
482             SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
483      Reg = PPC::CR3;
484    else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
485             SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
486      Reg = PPC::CR4;
487    else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
488             SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
489      Reg = PPC::CR5;
490    else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
491             SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
492      Reg = PPC::CR6;
493    else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
494             SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
495      Reg = PPC::CR7;
496
497    return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
498                               PPC::CRRCRegisterClass, NewMIs);
499
500  } else if (RC == PPC::VRRCRegisterClass) {
501    // We don't have indexed addressing for vector loads.  Emit:
502    // R0 = ADDI FI#
503    // STVX VAL, 0, R0
504    //
505    // FIXME: We use R0 here, because it isn't available for RA.
506    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
507                                       FrameIdx, 0, 0));
508    NewMIs.push_back(BuildMI(MF, DL, get(PPC::STVX))
509                     .addReg(SrcReg, getKillRegState(isKill))
510                     .addReg(PPC::R0)
511                     .addReg(PPC::R0));
512  } else {
513    llvm_unreachable("Unknown regclass!");
514  }
515
516  return false;
517}
518
519void
520PPCInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
521                                  MachineBasicBlock::iterator MI,
522                                  unsigned SrcReg, bool isKill, int FrameIdx,
523                                  const TargetRegisterClass *RC) const {
524  MachineFunction &MF = *MBB.getParent();
525  SmallVector<MachineInstr*, 4> NewMIs;
526
527  if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
528    PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
529    FuncInfo->setSpillsCR();
530  }
531
532  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
533    MBB.insert(MI, NewMIs[i]);
534}
535
536void
537PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF, DebugLoc DL,
538                                   unsigned DestReg, int FrameIdx,
539                                   const TargetRegisterClass *RC,
540                                   SmallVectorImpl<MachineInstr*> &NewMIs)const{
541  if (RC == PPC::GPRCRegisterClass) {
542    if (DestReg != PPC::LR) {
543      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
544                                                 DestReg), FrameIdx));
545    } else {
546      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
547                                                 PPC::R11), FrameIdx));
548      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR)).addReg(PPC::R11));
549    }
550  } else if (RC == PPC::G8RCRegisterClass) {
551    if (DestReg != PPC::LR8) {
552      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD), DestReg),
553                                         FrameIdx));
554    } else {
555      NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LD),
556                                                 PPC::R11), FrameIdx));
557      NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTLR8)).addReg(PPC::R11));
558    }
559  } else if (RC == PPC::F8RCRegisterClass) {
560    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFD), DestReg),
561                                       FrameIdx));
562  } else if (RC == PPC::F4RCRegisterClass) {
563    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LFS), DestReg),
564                                       FrameIdx));
565  } else if (RC == PPC::CRRCRegisterClass) {
566    // FIXME: We need a scatch reg here.  The trouble with using R0 is that
567    // it's possible for the stack frame to be so big the save location is
568    // out of range of immediate offsets, necessitating another register.
569    // We hack this on Darwin by reserving R2.  It's probably broken on Linux
570    // at the moment.
571    unsigned ScratchReg = TM.getSubtargetImpl()->isDarwinABI() ?
572                                                          PPC::R2 : PPC::R0;
573    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::LWZ),
574                                       ScratchReg), FrameIdx));
575
576    // If the reloaded register isn't CR0, shift the bits right so that they are
577    // in the right CR's slot.
578    if (DestReg != PPC::CR0) {
579      unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
580      // rlwinm r11, r11, 32-ShiftBits, 0, 31.
581      NewMIs.push_back(BuildMI(MF, DL, get(PPC::RLWINM), ScratchReg)
582                    .addReg(ScratchReg).addImm(32-ShiftBits).addImm(0)
583                    .addImm(31));
584    }
585
586    NewMIs.push_back(BuildMI(MF, DL, get(PPC::MTCRF), DestReg)
587                     .addReg(ScratchReg));
588  } else if (RC == PPC::CRBITRCRegisterClass) {
589
590    unsigned Reg = 0;
591    if (DestReg == PPC::CR0LT || DestReg == PPC::CR0GT ||
592        DestReg == PPC::CR0EQ || DestReg == PPC::CR0UN)
593      Reg = PPC::CR0;
594    else if (DestReg == PPC::CR1LT || DestReg == PPC::CR1GT ||
595             DestReg == PPC::CR1EQ || DestReg == PPC::CR1UN)
596      Reg = PPC::CR1;
597    else if (DestReg == PPC::CR2LT || DestReg == PPC::CR2GT ||
598             DestReg == PPC::CR2EQ || DestReg == PPC::CR2UN)
599      Reg = PPC::CR2;
600    else if (DestReg == PPC::CR3LT || DestReg == PPC::CR3GT ||
601             DestReg == PPC::CR3EQ || DestReg == PPC::CR3UN)
602      Reg = PPC::CR3;
603    else if (DestReg == PPC::CR4LT || DestReg == PPC::CR4GT ||
604             DestReg == PPC::CR4EQ || DestReg == PPC::CR4UN)
605      Reg = PPC::CR4;
606    else if (DestReg == PPC::CR5LT || DestReg == PPC::CR5GT ||
607             DestReg == PPC::CR5EQ || DestReg == PPC::CR5UN)
608      Reg = PPC::CR5;
609    else if (DestReg == PPC::CR6LT || DestReg == PPC::CR6GT ||
610             DestReg == PPC::CR6EQ || DestReg == PPC::CR6UN)
611      Reg = PPC::CR6;
612    else if (DestReg == PPC::CR7LT || DestReg == PPC::CR7GT ||
613             DestReg == PPC::CR7EQ || DestReg == PPC::CR7UN)
614      Reg = PPC::CR7;
615
616    return LoadRegFromStackSlot(MF, DL, Reg, FrameIdx,
617                                PPC::CRRCRegisterClass, NewMIs);
618
619  } else if (RC == PPC::VRRCRegisterClass) {
620    // We don't have indexed addressing for vector loads.  Emit:
621    // R0 = ADDI FI#
622    // Dest = LVX 0, R0
623    //
624    // FIXME: We use R0 here, because it isn't available for RA.
625    NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::ADDI), PPC::R0),
626                                       FrameIdx, 0, 0));
627    NewMIs.push_back(BuildMI(MF, DL, get(PPC::LVX),DestReg).addReg(PPC::R0)
628                     .addReg(PPC::R0));
629  } else {
630    llvm_unreachable("Unknown regclass!");
631  }
632}
633
634void
635PPCInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
636                                   MachineBasicBlock::iterator MI,
637                                   unsigned DestReg, int FrameIdx,
638                                   const TargetRegisterClass *RC) const {
639  MachineFunction &MF = *MBB.getParent();
640  SmallVector<MachineInstr*, 4> NewMIs;
641  DebugLoc DL;
642  if (MI != MBB.end()) DL = MI->getDebugLoc();
643  LoadRegFromStackSlot(MF, DL, DestReg, FrameIdx, RC, NewMIs);
644  for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
645    MBB.insert(MI, NewMIs[i]);
646}
647
648MachineInstr*
649PPCInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
650                                       unsigned FrameIx, uint64_t Offset,
651                                       const MDNode *MDPtr,
652                                       DebugLoc DL) const {
653  MachineInstrBuilder MIB = BuildMI(MF, DL, get(PPC::DBG_VALUE));
654  addFrameReference(MIB, FrameIx, 0, false).addImm(Offset).addMetadata(MDPtr);
655  return &*MIB;
656}
657
658/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
659/// copy instructions, turning them into load/store instructions.
660MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
661                                                  MachineInstr *MI,
662                                           const SmallVectorImpl<unsigned> &Ops,
663                                                  int FrameIndex) const {
664  if (Ops.size() != 1) return NULL;
665
666  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
667  // it takes more than one instruction to store it.
668  unsigned Opc = MI->getOpcode();
669  unsigned OpNum = Ops[0];
670
671  MachineInstr *NewMI = NULL;
672  if ((Opc == PPC::OR &&
673       MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
674    if (OpNum == 0) {  // move -> store
675      unsigned InReg = MI->getOperand(1).getReg();
676      bool isKill = MI->getOperand(1).isKill();
677      bool isUndef = MI->getOperand(1).isUndef();
678      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STW))
679                                .addReg(InReg,
680                                        getKillRegState(isKill) |
681                                        getUndefRegState(isUndef)),
682                                FrameIndex);
683    } else {           // move -> load
684      unsigned OutReg = MI->getOperand(0).getReg();
685      bool isDead = MI->getOperand(0).isDead();
686      bool isUndef = MI->getOperand(0).isUndef();
687      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LWZ))
688                                .addReg(OutReg,
689                                        RegState::Define |
690                                        getDeadRegState(isDead) |
691                                        getUndefRegState(isUndef)),
692                                FrameIndex);
693    }
694  } else if ((Opc == PPC::OR8 &&
695              MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
696    if (OpNum == 0) {  // move -> store
697      unsigned InReg = MI->getOperand(1).getReg();
698      bool isKill = MI->getOperand(1).isKill();
699      bool isUndef = MI->getOperand(1).isUndef();
700      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::STD))
701                                .addReg(InReg,
702                                        getKillRegState(isKill) |
703                                        getUndefRegState(isUndef)),
704                                FrameIndex);
705    } else {           // move -> load
706      unsigned OutReg = MI->getOperand(0).getReg();
707      bool isDead = MI->getOperand(0).isDead();
708      bool isUndef = MI->getOperand(0).isUndef();
709      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(), get(PPC::LD))
710                                .addReg(OutReg,
711                                        RegState::Define |
712                                        getDeadRegState(isDead) |
713                                        getUndefRegState(isUndef)),
714                                FrameIndex);
715    }
716  } else if (Opc == PPC::FMR || Opc == PPC::FMRSD) {
717    // The register may be F4RC or F8RC, and that determines the memory op.
718    unsigned OrigReg = MI->getOperand(OpNum).getReg();
719    // We cannot tell the register class from a physreg alone.
720    if (TargetRegisterInfo::isPhysicalRegister(OrigReg))
721      return NULL;
722    const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(OrigReg);
723    const bool is64 = RC == PPC::F8RCRegisterClass;
724
725    if (OpNum == 0) {  // move -> store
726      unsigned InReg = MI->getOperand(1).getReg();
727      bool isKill = MI->getOperand(1).isKill();
728      bool isUndef = MI->getOperand(1).isUndef();
729      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
730                                        get(is64 ? PPC::STFD : PPC::STFS))
731                                .addReg(InReg,
732                                        getKillRegState(isKill) |
733                                        getUndefRegState(isUndef)),
734                                FrameIndex);
735    } else {           // move -> load
736      unsigned OutReg = MI->getOperand(0).getReg();
737      bool isDead = MI->getOperand(0).isDead();
738      bool isUndef = MI->getOperand(0).isUndef();
739      NewMI = addFrameReference(BuildMI(MF, MI->getDebugLoc(),
740                                        get(is64 ? PPC::LFD : PPC::LFS))
741                                .addReg(OutReg,
742                                        RegState::Define |
743                                        getDeadRegState(isDead) |
744                                        getUndefRegState(isUndef)),
745                                FrameIndex);
746    }
747  }
748
749  return NewMI;
750}
751
752bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
753                                  const SmallVectorImpl<unsigned> &Ops) const {
754  if (Ops.size() != 1) return false;
755
756  // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
757  // it takes more than one instruction to store it.
758  unsigned Opc = MI->getOpcode();
759
760  if ((Opc == PPC::OR &&
761       MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
762    return true;
763  else if ((Opc == PPC::OR8 &&
764              MI->getOperand(1).getReg() == MI->getOperand(2).getReg()))
765    return true;
766  else if (Opc == PPC::FMR || Opc == PPC::FMRSD)
767    return true;
768
769  return false;
770}
771
772
773bool PPCInstrInfo::
774ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
775  assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
776  // Leave the CR# the same, but invert the condition.
777  Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
778  return false;
779}
780
781/// GetInstSize - Return the number of bytes of code the specified
782/// instruction may be.  This returns the maximum number of bytes.
783///
784unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
785  switch (MI->getOpcode()) {
786  case PPC::INLINEASM: {       // Inline Asm: Variable size.
787    const MachineFunction *MF = MI->getParent()->getParent();
788    const char *AsmStr = MI->getOperand(0).getSymbolName();
789    return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
790  }
791  case PPC::DBG_LABEL:
792  case PPC::EH_LABEL:
793  case PPC::GC_LABEL:
794  case PPC::DBG_VALUE:
795    return 0;
796  default:
797    return 4; // PowerPC instructions are all 4 bytes
798  }
799}
800