PPCSubtarget.cpp revision f5d5c434606161fb017a34cb656fa4aa5a3e076b 
1//===-- PowerPCSubtarget.cpp - PPC Subtarget Information ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the PPC specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#include "PPCSubtarget.h"
15#include "PPC.h"
16#include "PPCRegisterInfo.h"
17#include "llvm/IR/GlobalValue.h"
18#include "llvm/Support/Host.h"
19#include "llvm/Support/TargetRegistry.h"
20#include "llvm/Target/TargetMachine.h"
21#include <cstdlib>
22
23#define GET_SUBTARGETINFO_TARGET_DESC
24#define GET_SUBTARGETINFO_CTOR
25#include "PPCGenSubtargetInfo.inc"
26
27using namespace llvm;
28
29PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
30                           const std::string &FS, bool is64Bit)
31  : PPCGenSubtargetInfo(TT, CPU, FS)
32  , StackAlignment(16)
33  , DarwinDirective(PPC::DIR_NONE)
34  , HasMFOCRF(false)
35  , Has64BitSupport(false)
36  , Use64BitRegs(false)
37  , IsPPC64(is64Bit)
38  , HasAltivec(false)
39  , HasQPX(false)
40  , HasFSQRT(false)
41  , HasSTFIWX(false)
42  , HasFPRND(false)
43  , HasISEL(false)
44  , HasPOPCNTD(false)
45  , HasLDBRX(false)
46  , IsBookE(false)
47  , HasLazyResolverStubs(false)
48  , IsJITCodeModel(false)
49  , TargetTriple(TT) {
50
51  // Determine default and user specified characteristics
52  std::string CPUName = CPU;
53  if (CPUName.empty())
54    CPUName = "generic";
55#if (defined(__APPLE__) || defined(__linux__)) && \
56    (defined(__ppc__) || defined(__powerpc__))
57  if (CPUName == "generic")
58    CPUName = sys::getHostCPUName();
59#endif
60
61  // Initialize scheduling itinerary for the specified CPU.
62  InstrItins = getInstrItineraryForCPU(CPUName);
63
64  // Make sure 64-bit features are available when CPUname is generic
65  std::string FullFS = FS;
66
67  // If we are generating code for ppc64, verify that options make sense.
68  if (is64Bit) {
69    Has64BitSupport = true;
70    // Silently force 64-bit register use on ppc64.
71    Use64BitRegs = true;
72    if (!FullFS.empty())
73      FullFS = "+64bit," + FullFS;
74    else
75      FullFS = "+64bit";
76  }
77
78  // Parse features string.
79  ParseSubtargetFeatures(CPUName, FullFS);
80
81  // If the user requested use of 64-bit regs, but the cpu selected doesn't
82  // support it, ignore.
83  if (use64BitRegs() && !has64BitSupport())
84    Use64BitRegs = false;
85
86  // Set up darwin-specific properties.
87  if (isDarwin())
88    HasLazyResolverStubs = true;
89
90  // QPX requires a 32-byte aligned stack. Note that we need to do this if
91  // we're compiling for a BG/Q system regardless of whether or not QPX
92  // is enabled because external functions will assume this alignment.
93  if (hasQPX() || isBGQ())
94    StackAlignment = 32;
95}
96
97/// SetJITMode - This is called to inform the subtarget info that we are
98/// producing code for the JIT.
99void PPCSubtarget::SetJITMode() {
100  // JIT mode doesn't want lazy resolver stubs, it knows exactly where
101  // everything is.  This matters for PPC64, which codegens in PIC mode without
102  // stubs.
103  HasLazyResolverStubs = false;
104
105  // Calls to external functions need to use indirect calls
106  IsJITCodeModel = true;
107}
108
109
110/// hasLazyResolverStub - Return true if accesses to the specified global have
111/// to go through a dyld lazy resolution stub.  This means that an extra load
112/// is required to get the address of the global.
113bool PPCSubtarget::hasLazyResolverStub(const GlobalValue *GV,
114                                       const TargetMachine &TM) const {
115  // We never have stubs if HasLazyResolverStubs=false or if in static mode.
116  if (!HasLazyResolverStubs || TM.getRelocationModel() == Reloc::Static)
117    return false;
118  // If symbol visibility is hidden, the extra load is not needed if
119  // the symbol is definitely defined in the current translation unit.
120  bool isDecl = GV->isDeclaration() && !GV->isMaterializable();
121  if (GV->hasHiddenVisibility() && !isDecl && !GV->hasCommonLinkage())
122    return false;
123  return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
124         GV->hasCommonLinkage() || isDecl;
125}
126
127bool PPCSubtarget::enablePostRAScheduler(
128           CodeGenOpt::Level OptLevel,
129           TargetSubtargetInfo::AntiDepBreakMode& Mode,
130           RegClassVector& CriticalPathRCs) const {
131  // FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here,
132  // but we can't because we can't reassign the cr registers. There is a
133  // dependence between the cr register and the RLWINM instruction used
134  // to extract its value which the anti-dependency breaker can't currently
135  // see. Maybe we should make a late-expanded pseudo to encode this dependency.
136  // (the relevant code is in PPCDAGToDAGISel::SelectSETCC)
137
138  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
139
140  CriticalPathRCs.clear();
141
142  if (isPPC64())
143    CriticalPathRCs.push_back(&PPC::G8RCRegClass);
144  else
145    CriticalPathRCs.push_back(&PPC::GPRCRegClass);
146
147  CriticalPathRCs.push_back(&PPC::F8RCRegClass);
148  CriticalPathRCs.push_back(&PPC::VRRCRegClass);
149
150  return OptLevel >= CodeGenOpt::Default;
151}
152
153