PPCSubtarget.h revision dce4a407a24b04eebc6a376f8e62b41aaa7b071f 
1//===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the PowerPC specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef POWERPCSUBTARGET_H
15#define POWERPCSUBTARGET_H
16
17#include "llvm/ADT/Triple.h"
18#include "llvm/MC/MCInstrItineraries.h"
19#include "llvm/Target/TargetSubtargetInfo.h"
20#include <string>
21
22#define GET_SUBTARGETINFO_HEADER
23#include "PPCGenSubtargetInfo.inc"
24
25// GCC #defines PPC on Linux but we use it as our namespace name
26#undef PPC
27
28namespace llvm {
29class StringRef;
30
31namespace PPC {
32  // -m directive values.
33  enum {
34    DIR_NONE,
35    DIR_32,
36    DIR_440,
37    DIR_601,
38    DIR_602,
39    DIR_603,
40    DIR_7400,
41    DIR_750,
42    DIR_970,
43    DIR_A2,
44    DIR_E500mc,
45    DIR_E5500,
46    DIR_PWR3,
47    DIR_PWR4,
48    DIR_PWR5,
49    DIR_PWR5X,
50    DIR_PWR6,
51    DIR_PWR6X,
52    DIR_PWR7,
53    DIR_64
54  };
55}
56
57class GlobalValue;
58class TargetMachine;
59
60class PPCSubtarget : public PPCGenSubtargetInfo {
61protected:
62  /// stackAlignment - The minimum alignment known to hold of the stack frame on
63  /// entry to the function and which must be maintained by every function.
64  unsigned StackAlignment;
65
66  /// Selected instruction itineraries (one entry per itinerary class.)
67  InstrItineraryData InstrItins;
68
69  /// Which cpu directive was used.
70  unsigned DarwinDirective;
71
72  /// Used by the ISel to turn in optimizations for POWER4-derived architectures
73  bool HasMFOCRF;
74  bool Has64BitSupport;
75  bool Use64BitRegs;
76  bool UseCRBits;
77  bool IsPPC64;
78  bool HasAltivec;
79  bool HasQPX;
80  bool HasVSX;
81  bool HasFCPSGN;
82  bool HasFSQRT;
83  bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
84  bool HasRecipPrec;
85  bool HasSTFIWX;
86  bool HasLFIWAX;
87  bool HasFPRND;
88  bool HasFPCVT;
89  bool HasISEL;
90  bool HasPOPCNTD;
91  bool HasLDBRX;
92  bool IsBookE;
93  bool DeprecatedMFTB;
94  bool DeprecatedDST;
95  bool HasLazyResolverStubs;
96  bool IsJITCodeModel;
97  bool IsLittleEndian;
98
99  /// TargetTriple - What processor and OS we're targeting.
100  Triple TargetTriple;
101
102  /// OptLevel - What default optimization level we're emitting code for.
103  CodeGenOpt::Level OptLevel;
104
105public:
106  /// This constructor initializes the data members to match that
107  /// of the specified triple.
108  ///
109  PPCSubtarget(const std::string &TT, const std::string &CPU,
110               const std::string &FS, bool is64Bit,
111               CodeGenOpt::Level OptLevel);
112
113  /// ParseSubtargetFeatures - Parses features string setting specified
114  /// subtarget options.  Definition of function is auto generated by tblgen.
115  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
116
117  /// SetJITMode - This is called to inform the subtarget info that we are
118  /// producing code for the JIT.
119  void SetJITMode();
120
121  /// getStackAlignment - Returns the minimum alignment known to hold of the
122  /// stack frame on entry to the function and which must be maintained by every
123  /// function for this subtarget.
124  unsigned getStackAlignment() const { return StackAlignment; }
125
126  /// getDarwinDirective - Returns the -m directive specified for the cpu.
127  ///
128  unsigned getDarwinDirective() const { return DarwinDirective; }
129
130  /// getInstrItins - Return the instruction itineraies based on subtarget
131  /// selection.
132  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
133
134  /// \brief Reset the features for the PowerPC target.
135  void resetSubtargetFeatures(const MachineFunction *MF) override;
136private:
137  void initializeEnvironment();
138  void resetSubtargetFeatures(StringRef CPU, StringRef FS);
139
140public:
141  /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
142  ///
143  bool isPPC64() const { return IsPPC64; }
144
145  /// has64BitSupport - Return true if the selected CPU supports 64-bit
146  /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
147  bool has64BitSupport() const { return Has64BitSupport; }
148
149  /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
150  /// registers in 32-bit mode when possible.  This can only true if
151  /// has64BitSupport() returns true.
152  bool use64BitRegs() const { return Use64BitRegs; }
153
154  /// useCRBits - Return true if we should store and manipulate i1 values in
155  /// the individual condition register bits.
156  bool useCRBits() const { return UseCRBits; }
157
158  /// hasLazyResolverStub - Return true if accesses to the specified global have
159  /// to go through a dyld lazy resolution stub.  This means that an extra load
160  /// is required to get the address of the global.
161  bool hasLazyResolverStub(const GlobalValue *GV,
162                           const TargetMachine &TM) const;
163
164  // isJITCodeModel - True if we're generating code for the JIT
165  bool isJITCodeModel() const { return IsJITCodeModel; }
166
167  // isLittleEndian - True if generating little-endian code
168  bool isLittleEndian() const { return IsLittleEndian; }
169
170  // Specific obvious features.
171  bool hasFCPSGN() const { return HasFCPSGN; }
172  bool hasFSQRT() const { return HasFSQRT; }
173  bool hasFRE() const { return HasFRE; }
174  bool hasFRES() const { return HasFRES; }
175  bool hasFRSQRTE() const { return HasFRSQRTE; }
176  bool hasFRSQRTES() const { return HasFRSQRTES; }
177  bool hasRecipPrec() const { return HasRecipPrec; }
178  bool hasSTFIWX() const { return HasSTFIWX; }
179  bool hasLFIWAX() const { return HasLFIWAX; }
180  bool hasFPRND() const { return HasFPRND; }
181  bool hasFPCVT() const { return HasFPCVT; }
182  bool hasAltivec() const { return HasAltivec; }
183  bool hasQPX() const { return HasQPX; }
184  bool hasVSX() const { return HasVSX; }
185  bool hasMFOCRF() const { return HasMFOCRF; }
186  bool hasISEL() const { return HasISEL; }
187  bool hasPOPCNTD() const { return HasPOPCNTD; }
188  bool hasLDBRX() const { return HasLDBRX; }
189  bool isBookE() const { return IsBookE; }
190  bool isDeprecatedMFTB() const { return DeprecatedMFTB; }
191  bool isDeprecatedDST() const { return DeprecatedDST; }
192
193  const Triple &getTargetTriple() const { return TargetTriple; }
194
195  /// isDarwin - True if this is any darwin platform.
196  bool isDarwin() const { return TargetTriple.isMacOSX(); }
197  /// isBGQ - True if this is a BG/Q platform.
198  bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
199
200  bool isDarwinABI() const { return isDarwin(); }
201  bool isSVR4ABI() const { return !isDarwin(); }
202
203  /// enablePostRAScheduler - True at 'More' optimization.
204  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
205                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
206                             RegClassVector& CriticalPathRCs) const override;
207
208  bool enableEarlyIfConversion() const override { return hasISEL(); }
209
210  // Scheduling customization.
211  bool enableMachineScheduler() const override;
212  void overrideSchedPolicy(MachineSchedPolicy &Policy,
213                           MachineInstr *begin,
214                           MachineInstr *end,
215                           unsigned NumRegionInstrs) const override;
216  bool useAA() const override;
217};
218} // End llvm namespace
219
220#endif
221