AMDGPUISelLowering.h revision a2b4eb6d15a13de257319ac6231b5ab622cd02b1 
1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition of the TargetLowering class that is common
12/// to all AMD GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef AMDGPUISELLOWERING_H
17#define AMDGPUISELLOWERING_H
18
19#include "llvm/Target/TargetLowering.h"
20
21namespace llvm {
22
23class AMDGPUMachineFunction;
24class MachineRegisterInfo;
25
26class AMDGPUTargetLowering : public TargetLowering {
27private:
28  void ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
29                             SmallVectorImpl<SDValue> &Args,
30                             unsigned Start, unsigned Count) const;
31  SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
32  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
33  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
34  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
35  /// \brief Lower vector stores by merging the vector elements into an integer
36  /// of the same bitwidth.
37  SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
38  /// \brief Split a vector store into multiple scalar stores.
39  /// \returns The resulting chain.
40  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
41  SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
42
43protected:
44
45  /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
46  /// MachineFunction.
47  ///
48  /// \returns a RegisterSDNode representing Reg.
49  virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
50                                       const TargetRegisterClass *RC,
51                                       unsigned Reg, EVT VT) const;
52  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
53                             SelectionDAG &DAG) const;
54  /// \brief Split a vector load into multiple scalar loads.
55  SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
56  SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
57  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
58  bool isHWTrueValue(SDValue Op) const;
59  bool isHWFalseValue(SDValue Op) const;
60
61  /// The SelectionDAGBuilder will automatically promote function arguments
62  /// with illegal types.  However, this does not work for the AMDGPU targets
63  /// since the function arguments are stored in memory as these illegal types.
64  /// In order to handle this properly we need to get the origianl types sizes
65  /// from the LLVM IR Function and fixup the ISD:InputArg values before
66  /// passing them to AnalyzeFormalArguments()
67  void getOriginalFunctionArgs(SelectionDAG &DAG,
68                               const Function *F,
69                               const SmallVectorImpl<ISD::InputArg> &Ins,
70                               SmallVectorImpl<ISD::InputArg> &OrigIns) const;
71  void AnalyzeFormalArguments(CCState &State,
72                              const SmallVectorImpl<ISD::InputArg> &Ins) const;
73
74public:
75  AMDGPUTargetLowering(TargetMachine &TM);
76
77  virtual bool isFAbsFree(EVT VT) const;
78  virtual bool isFNegFree(EVT VT) const;
79  virtual MVT getVectorIdxTy() const;
80  virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
81                              bool isVarArg,
82                              const SmallVectorImpl<ISD::OutputArg> &Outs,
83                              const SmallVectorImpl<SDValue> &OutVals,
84                              SDLoc DL, SelectionDAG &DAG) const;
85  virtual SDValue LowerCall(CallLoweringInfo &CLI,
86                            SmallVectorImpl<SDValue> &InVals) const {
87    CLI.Callee.dump();
88    llvm_unreachable("Undefined function");
89  }
90
91  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
92  SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
93  SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
94  SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
95  virtual const char* getTargetNodeName(unsigned Opcode) const;
96
97  virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
98    return N;
99  }
100
101// Functions defined in AMDILISelLowering.cpp
102public:
103
104  /// \brief Determine which of the bits specified in \p Mask are known to be
105  /// either zero or one and return them in the \p KnownZero and \p KnownOne
106  /// bitsets.
107  virtual void computeMaskedBitsForTargetNode(const SDValue Op,
108                                              APInt &KnownZero,
109                                              APInt &KnownOne,
110                                              const SelectionDAG &DAG,
111                                              unsigned Depth = 0) const;
112
113  virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
114                                  const CallInst &I, unsigned Intrinsic) const;
115
116  /// We want to mark f32/f64 floating point values as legal.
117  bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
118
119  /// We don't want to shrink f64/f32 constants.
120  bool ShouldShrinkFPConstant(EVT VT) const;
121
122private:
123  void InitAMDILLowering();
124  SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
125  SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
126  SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
127  SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
128  SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
129  SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
130  SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
131  SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
132  SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
133  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
134  EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
135  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
136  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
137};
138
139namespace AMDGPUISD {
140
141enum {
142  // AMDIL ISD Opcodes
143  FIRST_NUMBER = ISD::BUILTIN_OP_END,
144  CALL,        // Function call based on a single integer
145  UMUL,        // 32bit unsigned multiplication
146  DIV_INF,      // Divide with infinity returned on zero divisor
147  RET_FLAG,
148  BRANCH_COND,
149  // End AMDIL ISD Opcodes
150  DWORDADDR,
151  FRACT,
152  COS_HW,
153  SIN_HW,
154  FMAX,
155  SMAX,
156  UMAX,
157  FMIN,
158  SMIN,
159  UMIN,
160  URECIP,
161  DOT4,
162  TEXTURE_FETCH,
163  EXPORT,
164  CONST_ADDRESS,
165  REGISTER_LOAD,
166  REGISTER_STORE,
167  LOAD_INPUT,
168  SAMPLE,
169  SAMPLEB,
170  SAMPLED,
171  SAMPLEL,
172  FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
173  STORE_MSKOR,
174  LOAD_CONSTANT,
175  TBUFFER_STORE_FORMAT,
176  LAST_AMDGPU_ISD_NUMBER
177};
178
179
180} // End namespace AMDGPUISD
181
182} // End namespace llvm
183
184#endif // AMDGPUISELLOWERING_H
185