| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 509a492442b7e889d615d3b451629c81a810aef1 |
|
15-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add target hook to prevent folding some bitcasted loads.
This is to avoid this transformation in some cases:
fold (conv (load x)) -> (load (conv*)x)
On architectures that don't natively support some vector
loads efficiently casting the load to a smaller vector of
larger types and loading is more efficient.
Patch by Micah Villmow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194783 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| a2b4eb6d15a13de257319ac6231b5ab622cd02b1 |
|
14-Nov-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add support for private address space load/store
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| aa1d078e7f42b605be03ff42d9b2e09923d3590d |
|
30-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Custom lower f32 = uint_to_fp i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| f95b1621887e3409ceec2db47e1b44271d934735 |
|
23-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Fix handling of vector kernel arguments
The SelectionDAGBuilder was promoting vector kernel arguments to legal
types, but this won't work for R600 and SI since kernel arguments are
stored in memory and can't be promoted. In order to handle vector
arguments correctly we need to look at the original types from the LLVM IR
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| a3c2bcf0ee2f63584f7a1e9df9fa153a8b5dfea1 |
|
12-Sep-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback
For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist.
The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take
a resource descriptor might be nicer.
The maximum number of input SGPRs is bumped to 17.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| d08a9303614355cfdcac5f2c27c09ce809565423 |
|
26-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add support for vector local memory loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 7a0282daeb214f14d75249cc2d90302c44586c4e |
|
26-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add support for v4i32 and v2i32 local stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 4c52d450dc3968267d1f089d36397fc785dcc7b4 |
|
16-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add support for global vector stores with elements less than 32-bits
Tested-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188520 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| ec484277dd04399d7b2ea37508e39fc4998bc9a7 |
|
16-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add support for i16 and i8 global stores
Tested-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| a41520cf9b9cefed2091a0624a34c5f7fdb42a68 |
|
15-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Improve legalization of vector operations
This should fix hangs in the OpenCL piglit tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 68db37b952be497c94c7aa98cf26f3baadb5afd3 |
|
15-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Convert v16i8 resource descriptors to i128
Now that compute support is better on SI, we can't continue using v16i8
for descriptors since this is also a legal type in OpenCL.
This patch fixes numerous hangs with the piglit OpenCL test and since
we now use a target specific DAG node for LOAD_CONSTANT with the
correct MemOperandFlags, this should also fix:
https://bugs.freedesktop.org/show_bug.cgi?id=66805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 2b272a1c8cb6d9f02223a598495d84cd9d75b13d |
|
06-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Implement TargetLowering::getVectorIdxTy()
We use MVT::i32 for the vector index type, because we use 32-bit
operations to caculate offsets when dynamically indexing vectors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 1f67c63cb23ba5d405452d72bb8892df6b7ccd4f |
|
24-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
DAGCombiner: Pass the correct type to TargetLowering::isF(Abs|Neg)Free
This commit also implements these functions for R600 and removes a test
case that was relying on the buggy behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| c6f13db656c7649f933c74c4f90c09ff74de52a8 |
|
09-Jul-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Use DAG lowering pass to handle fcos/fsin
NOTE: This is a candidate for the stable branch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185940 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| e3d4cbc7d25061441adafa47450a31571c87bf85 |
|
28-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add local memory support via LDS
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| e5fcc0dee4b41658986047f346201ad98757e7d5 |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add support for work item and work group intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 4956bc61e1c86e781fd8abe14431c121d960d65b |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Rework MUBUF store instructions
The lowering of stores is now mostly handled in the tablegen files. No
more BUFFER_STORE nodes I generated during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| ba534c21437ba133cb9d6b3f9dae80fa9c4f0cb7 |
|
20-May-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Swap the legality of rotl and rotr
The hardware supports rotr and not rotl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182285 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 4ed9917147b1d1f2616f7c941bbe6999b979f510 |
|
17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Relax some vector constraints on Dot4.
Dot4 now uses 8 scalar operands instead of 2 vectors one which allows register
coalescer to remove some unneeded COPY.
This patch also defines some structures/functions that can be used to handle
every vector instructions (CUBE, Cayman special instructions...) in a similar
fashion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182126 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| d3293b49f9c7af741d2edd3062499fb50db0e89b |
|
17-May-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Improve texture handling
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 17ea10cb792832c99677afa13b9b866098bc4679 |
|
06-Apr-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add support for buffer stores v2
v2:
- Use the ADDR64 bit
Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 90c64cbaa124e0e8541680efeaa56f0e6eb78d9a |
|
07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add proper formal parameter handling for SI
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| c018ecac2f2f475b6e1023e90d0e48fcf9bd6e1d |
|
26-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add folding helper
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| e3111964a0902bc38440980b0915b189f829c395 |
|
18-Feb-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| e9ba1830df2efef3da113a740909195e839ebd36 |
|
16-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: nuke SReg_1 v3
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.
This actually fixes a piglit test on SI.
v2: use correct register class in addRegisterClass,
set special classes as not allocatable
v3: revert setting special classes as not allocateable
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| d66bd704cc92fed8292e06018e4f26547d1c96d0 |
|
08-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Dump the function name when TargetLowering::LowerCall() fails
Also output a more useful error message.
NOTE: This is a candidate for the Mesa stable branch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8 |
|
06-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Support for indirect addressing v4
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| 29b15a378045762ce09642ab9dd741ece41f59a3 |
|
05-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: improve inputs/interpolation handling
Use one intrinsic for all sorts of interpolation.
Use two separate unexpanded instructions to represent INTERP_XY and _ZW -
this will allow to eliminate one part if it's not used.
Track liveness of special interpolation regs instead of reserving them -
this will allow to reuse those regs, lowering reg pressure.
Patch By: Vadim Girlin
v2[Vincent Lejeune]: Rebased against current llvm master
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174394 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| c7e1888d93f4cb2982266986f3af7e99df631fa1 |
|
23-Jan-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add a CONST_ADDRESS node to model constant buf read
Patch by: Vincent Lejeune
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|
| f98f2ce29e6e2996fa58f38979143eceaa818335 |
|
11-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelLowering.h
|