AMDGPUISelLowering.h revision f95b1621887e3409ceec2db47e1b44271d934735 
1//===-- AMDGPUISelLowering.h - AMDGPU Lowering Interface --------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition of the TargetLowering class that is common
12/// to all AMD GPUs.
13//
14//===----------------------------------------------------------------------===//
15
16#ifndef AMDGPUISELLOWERING_H
17#define AMDGPUISELLOWERING_H
18
19#include "llvm/Target/TargetLowering.h"
20
21namespace llvm {
22
23class AMDGPUMachineFunction;
24class MachineRegisterInfo;
25
26class AMDGPUTargetLowering : public TargetLowering {
27private:
28  void ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
29                             SmallVectorImpl<SDValue> &Args,
30                             unsigned Start, unsigned Count) const;
31  SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
32  SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
33  SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
34  /// \brief Lower vector stores by merging the vector elements into an integer
35  /// of the same bitwidth.
36  SDValue MergeVectorStore(const SDValue &Op, SelectionDAG &DAG) const;
37  /// \brief Split a vector store into multiple scalar stores.
38  /// \returns The resulting chain.
39  SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
40
41protected:
42
43  /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
44  /// MachineFunction.
45  ///
46  /// \returns a RegisterSDNode representing Reg.
47  virtual SDValue CreateLiveInRegister(SelectionDAG &DAG,
48                                       const TargetRegisterClass *RC,
49                                       unsigned Reg, EVT VT) const;
50  SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
51                             SelectionDAG &DAG) const;
52  /// \brief Split a vector load into multiple scalar loads.
53  SDValue SplitVectorLoad(const SDValue &Op, SelectionDAG &DAG) const;
54  SDValue SplitVectorStore(SDValue Op, SelectionDAG &DAG) const;
55  SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
56  bool isHWTrueValue(SDValue Op) const;
57  bool isHWFalseValue(SDValue Op) const;
58
59  /// The SelectionDAGBuilder will automatically promote function arguments
60  /// with illegal types.  However, this does not work for the AMDGPU targets
61  /// since the function arguments are stored in memory as these illegal types.
62  /// In order to handle this properly we need to get the origianl types sizes
63  /// from the LLVM IR Function and fixup the ISD:InputArg values before
64  /// passing them to AnalyzeFormalArguments()
65  void getOriginalFunctionArgs(SelectionDAG &DAG,
66                               const Function *F,
67                               const SmallVectorImpl<ISD::InputArg> &Ins,
68                               SmallVectorImpl<ISD::InputArg> &OrigIns) const;
69  void AnalyzeFormalArguments(CCState &State,
70                              const SmallVectorImpl<ISD::InputArg> &Ins) const;
71
72public:
73  AMDGPUTargetLowering(TargetMachine &TM);
74
75  virtual bool isFAbsFree(EVT VT) const;
76  virtual bool isFNegFree(EVT VT) const;
77  virtual MVT getVectorIdxTy() const;
78  virtual SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv,
79                              bool isVarArg,
80                              const SmallVectorImpl<ISD::OutputArg> &Outs,
81                              const SmallVectorImpl<SDValue> &OutVals,
82                              SDLoc DL, SelectionDAG &DAG) const;
83  virtual SDValue LowerCall(CallLoweringInfo &CLI,
84                            SmallVectorImpl<SDValue> &InVals) const {
85    CLI.Callee.dump();
86    llvm_unreachable("Undefined function");
87  }
88
89  virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
90  SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
91  SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
92  SDValue LowerMinMax(SDValue Op, SelectionDAG &DAG) const;
93  virtual const char* getTargetNodeName(unsigned Opcode) const;
94
95  virtual SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const {
96    return N;
97  }
98
99// Functions defined in AMDILISelLowering.cpp
100public:
101
102  /// \brief Determine which of the bits specified in \p Mask are known to be
103  /// either zero or one and return them in the \p KnownZero and \p KnownOne
104  /// bitsets.
105  virtual void computeMaskedBitsForTargetNode(const SDValue Op,
106                                              APInt &KnownZero,
107                                              APInt &KnownOne,
108                                              const SelectionDAG &DAG,
109                                              unsigned Depth = 0) const;
110
111  virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
112                                  const CallInst &I, unsigned Intrinsic) const;
113
114  /// We want to mark f32/f64 floating point values as legal.
115  bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
116
117  /// We don't want to shrink f64/f32 constants.
118  bool ShouldShrinkFPConstant(EVT VT) const;
119
120private:
121  void InitAMDILLowering();
122  SDValue LowerSREM(SDValue Op, SelectionDAG &DAG) const;
123  SDValue LowerSREM8(SDValue Op, SelectionDAG &DAG) const;
124  SDValue LowerSREM16(SDValue Op, SelectionDAG &DAG) const;
125  SDValue LowerSREM32(SDValue Op, SelectionDAG &DAG) const;
126  SDValue LowerSREM64(SDValue Op, SelectionDAG &DAG) const;
127  SDValue LowerSDIV(SDValue Op, SelectionDAG &DAG) const;
128  SDValue LowerSDIV24(SDValue Op, SelectionDAG &DAG) const;
129  SDValue LowerSDIV32(SDValue Op, SelectionDAG &DAG) const;
130  SDValue LowerSDIV64(SDValue Op, SelectionDAG &DAG) const;
131  SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
132  EVT genIntType(uint32_t size = 32, uint32_t numEle = 1) const;
133  SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
134  SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
135};
136
137namespace AMDGPUISD {
138
139enum {
140  // AMDIL ISD Opcodes
141  FIRST_NUMBER = ISD::BUILTIN_OP_END,
142  CALL,        // Function call based on a single integer
143  UMUL,        // 32bit unsigned multiplication
144  DIV_INF,      // Divide with infinity returned on zero divisor
145  RET_FLAG,
146  BRANCH_COND,
147  // End AMDIL ISD Opcodes
148  DWORDADDR,
149  FRACT,
150  COS_HW,
151  SIN_HW,
152  FMAX,
153  SMAX,
154  UMAX,
155  FMIN,
156  SMIN,
157  UMIN,
158  URECIP,
159  DOT4,
160  TEXTURE_FETCH,
161  EXPORT,
162  CONST_ADDRESS,
163  REGISTER_LOAD,
164  REGISTER_STORE,
165  LOAD_INPUT,
166  SAMPLE,
167  SAMPLEB,
168  SAMPLED,
169  SAMPLEL,
170  FIRST_MEM_OPCODE_NUMBER = ISD::FIRST_TARGET_MEMORY_OPCODE,
171  STORE_MSKOR,
172  LOAD_CONSTANT,
173  TBUFFER_STORE_FORMAT,
174  LAST_AMDGPU_ISD_NUMBER
175};
176
177
178} // End namespace AMDGPUISD
179
180} // End namespace llvm
181
182#endif // AMDGPUISELLOWERING_H
183