1//===-- CaymanInstructions.td - CM Instruction defs -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// TableGen definitions for instructions which are available only on Cayman 11// family GPUs. 12// 13//===----------------------------------------------------------------------===// 14 15def isCayman : Predicate<"Subtarget.hasCaymanISA()">; 16 17//===----------------------------------------------------------------------===// 18// Cayman Instructions 19//===----------------------------------------------------------------------===// 20 21let Predicates = [isCayman] in { 22 23def MULADD_INT24_cm : R600_3OP <0x08, "MULADD_INT24", 24 [(set i32:$dst, (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2))], VecALU 25>; 26def MUL_INT24_cm : R600_2OP <0x5B, "MUL_INT24", 27 [(set i32:$dst, (AMDGPUmul_i24 i32:$src0, i32:$src1))], VecALU 28>; 29 30def : IMad24Pat<MULADD_INT24_cm>; 31 32let isVector = 1 in { 33 34def RECIP_IEEE_cm : RECIP_IEEE_Common<0x86>; 35 36def MULLO_INT_cm : MULLO_INT_Common<0x8F>; 37def MULHI_INT_cm : MULHI_INT_Common<0x90>; 38def MULLO_UINT_cm : MULLO_UINT_Common<0x91>; 39def MULHI_UINT_cm : MULHI_UINT_Common<0x92>; 40def RECIPSQRT_CLAMPED_cm : RECIPSQRT_CLAMPED_Common<0x87>; 41def EXP_IEEE_cm : EXP_IEEE_Common<0x81>; 42def LOG_IEEE_cm : LOG_IEEE_Common<0x83>; 43def RECIP_CLAMPED_cm : RECIP_CLAMPED_Common<0x84>; 44def RECIPSQRT_IEEE_cm : RECIPSQRT_IEEE_Common<0x89>; 45def SIN_cm : SIN_Common<0x8D>; 46def COS_cm : COS_Common<0x8E>; 47} // End isVector = 1 48 49def : POW_Common <LOG_IEEE_cm, EXP_IEEE_cm, MUL>; 50 51defm DIV_cm : DIV_Common<RECIP_IEEE_cm>; 52defm : Expand24UBitOps<MULLO_UINT_cm, ADD_INT>; 53 54// RECIP_UINT emulation for Cayman 55// The multiplication scales from [0,1] to the unsigned integer range 56def : Pat < 57 (AMDGPUurecip i32:$src0), 58 (FLT_TO_UINT_eg (MUL_IEEE (RECIP_IEEE_cm (UINT_TO_FLT_eg $src0)), 59 (MOV_IMM_I32 CONST.FP_UINT_MAX_PLUS_1))) 60>; 61 62 def CF_END_CM : CF_CLAUSE_EG<32, (ins), "CF_END"> { 63 let ADDR = 0; 64 let POP_COUNT = 0; 65 let COUNT = 0; 66 } 67 68 69def : Pat<(fsqrt f32:$src), (MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_cm $src))>; 70 71class RAT_STORE_DWORD <RegisterClass rc, ValueType vt, bits<4> mask> : 72 CF_MEM_RAT_CACHELESS <0x14, 0, mask, 73 (ins rc:$rw_gpr, R600_TReg32_X:$index_gpr), 74 "STORE_DWORD $rw_gpr, $index_gpr", 75 [(global_store vt:$rw_gpr, i32:$index_gpr)]> { 76 let eop = 0; // This bit is not used on Cayman. 77} 78 79def RAT_STORE_DWORD32 : RAT_STORE_DWORD <R600_TReg32_X, i32, 0x1>; 80def RAT_STORE_DWORD64 : RAT_STORE_DWORD <R600_Reg64, v2i32, 0x3>; 81def RAT_STORE_DWORD128 : RAT_STORE_DWORD <R600_Reg128, v4i32, 0xf>; 82 83class VTX_READ_cm <string name, bits<8> buffer_id, dag outs, list<dag> pattern> 84 : VTX_WORD0_cm, VTX_READ<name, buffer_id, outs, pattern> { 85 86 // Static fields 87 let VC_INST = 0; 88 let FETCH_TYPE = 2; 89 let FETCH_WHOLE_QUAD = 0; 90 let BUFFER_ID = buffer_id; 91 let SRC_REL = 0; 92 // XXX: We can infer this field based on the SRC_GPR. This would allow us 93 // to store vertex addresses in any channel, not just X. 94 let SRC_SEL_X = 0; 95 let SRC_SEL_Y = 0; 96 let STRUCTURED_READ = 0; 97 let LDS_REQ = 0; 98 let COALESCED_READ = 0; 99 100 let Inst{31-0} = Word0; 101} 102 103class VTX_READ_8_cm <bits<8> buffer_id, list<dag> pattern> 104 : VTX_READ_cm <"VTX_READ_8 $dst_gpr, $src_gpr", buffer_id, 105 (outs R600_TReg32_X:$dst_gpr), pattern> { 106 107 let DST_SEL_X = 0; 108 let DST_SEL_Y = 7; // Masked 109 let DST_SEL_Z = 7; // Masked 110 let DST_SEL_W = 7; // Masked 111 let DATA_FORMAT = 1; // FMT_8 112} 113 114class VTX_READ_16_cm <bits<8> buffer_id, list<dag> pattern> 115 : VTX_READ_cm <"VTX_READ_16 $dst_gpr, $src_gpr", buffer_id, 116 (outs R600_TReg32_X:$dst_gpr), pattern> { 117 let DST_SEL_X = 0; 118 let DST_SEL_Y = 7; // Masked 119 let DST_SEL_Z = 7; // Masked 120 let DST_SEL_W = 7; // Masked 121 let DATA_FORMAT = 5; // FMT_16 122 123} 124 125class VTX_READ_32_cm <bits<8> buffer_id, list<dag> pattern> 126 : VTX_READ_cm <"VTX_READ_32 $dst_gpr, $src_gpr", buffer_id, 127 (outs R600_TReg32_X:$dst_gpr), pattern> { 128 129 let DST_SEL_X = 0; 130 let DST_SEL_Y = 7; // Masked 131 let DST_SEL_Z = 7; // Masked 132 let DST_SEL_W = 7; // Masked 133 let DATA_FORMAT = 0xD; // COLOR_32 134 135 // This is not really necessary, but there were some GPU hangs that appeared 136 // to be caused by ALU instructions in the next instruction group that wrote 137 // to the $src_gpr registers of the VTX_READ. 138 // e.g. 139 // %T3_X<def> = VTX_READ_PARAM_32_eg %T2_X<kill>, 24 140 // %T2_X<def> = MOV %ZERO 141 //Adding this constraint prevents this from happening. 142 let Constraints = "$src_gpr.ptr = $dst_gpr"; 143} 144 145class VTX_READ_64_cm <bits<8> buffer_id, list<dag> pattern> 146 : VTX_READ_cm <"VTX_READ_64 $dst_gpr, $src_gpr", buffer_id, 147 (outs R600_Reg64:$dst_gpr), pattern> { 148 149 let DST_SEL_X = 0; 150 let DST_SEL_Y = 1; 151 let DST_SEL_Z = 7; 152 let DST_SEL_W = 7; 153 let DATA_FORMAT = 0x1D; // COLOR_32_32 154} 155 156class VTX_READ_128_cm <bits<8> buffer_id, list<dag> pattern> 157 : VTX_READ_cm <"VTX_READ_128 $dst_gpr.XYZW, $src_gpr", buffer_id, 158 (outs R600_Reg128:$dst_gpr), pattern> { 159 160 let DST_SEL_X = 0; 161 let DST_SEL_Y = 1; 162 let DST_SEL_Z = 2; 163 let DST_SEL_W = 3; 164 let DATA_FORMAT = 0x22; // COLOR_32_32_32_32 165 166 // XXX: Need to force VTX_READ_128 instructions to write to the same register 167 // that holds its buffer address to avoid potential hangs. We can't use 168 // the same constraint as VTX_READ_32_eg, because the $src_gpr.ptr and $dst 169 // registers are different sizes. 170} 171 172//===----------------------------------------------------------------------===// 173// VTX Read from parameter memory space 174//===----------------------------------------------------------------------===// 175def VTX_READ_PARAM_8_cm : VTX_READ_8_cm <0, 176 [(set i32:$dst_gpr, (load_param_exti8 ADDRVTX_READ:$src_gpr))] 177>; 178 179def VTX_READ_PARAM_16_cm : VTX_READ_16_cm <0, 180 [(set i32:$dst_gpr, (load_param_exti16 ADDRVTX_READ:$src_gpr))] 181>; 182 183def VTX_READ_PARAM_32_cm : VTX_READ_32_cm <0, 184 [(set i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 185>; 186 187def VTX_READ_PARAM_64_cm : VTX_READ_64_cm <0, 188 [(set v2i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 189>; 190 191def VTX_READ_PARAM_128_cm : VTX_READ_128_cm <0, 192 [(set v4i32:$dst_gpr, (load_param ADDRVTX_READ:$src_gpr))] 193>; 194 195//===----------------------------------------------------------------------===// 196// VTX Read from global memory space 197//===----------------------------------------------------------------------===// 198 199// 8-bit reads 200def VTX_READ_GLOBAL_8_cm : VTX_READ_8_cm <1, 201 [(set i32:$dst_gpr, (az_extloadi8_global ADDRVTX_READ:$src_gpr))] 202>; 203 204def VTX_READ_GLOBAL_16_cm : VTX_READ_16_cm <1, 205 [(set i32:$dst_gpr, (az_extloadi16_global ADDRVTX_READ:$src_gpr))] 206>; 207 208// 32-bit reads 209def VTX_READ_GLOBAL_32_cm : VTX_READ_32_cm <1, 210 [(set i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 211>; 212 213// 64-bit reads 214def VTX_READ_GLOBAL_64_cm : VTX_READ_64_cm <1, 215 [(set v2i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 216>; 217 218// 128-bit reads 219def VTX_READ_GLOBAL_128_cm : VTX_READ_128_cm <1, 220 [(set v4i32:$dst_gpr, (global_load ADDRVTX_READ:$src_gpr))] 221>; 222 223} // End isCayman 224 225