R600InstrFormats.td revision 7e9381951eb4dadf9c59257786416ac51a6a6c09 
1//===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// R600 Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
15                InstrItinClass itin>
16    : AMDGPUInst <outs, ins, asm, pattern> {
17
18  field bits<64> Inst;
19  bit TransOnly = 0;
20  bit Trig = 0;
21  bit Op3 = 0;
22  bit isVector = 0;
23  bits<2> FlagOperandIdx = 0;
24  bit Op1 = 0;
25  bit Op2 = 0;
26  bit HasNativeOperands = 0;
27  bit VTXInst = 0;
28  bit TEXInst = 0;
29  bit ALUInst = 0;
30
31  let Namespace = "AMDGPU";
32  let OutOperandList = outs;
33  let InOperandList = ins;
34  let AsmString = asm;
35  let Pattern = pattern;
36  let Itinerary = itin;
37
38  let TSFlags{0} = TransOnly;
39  let TSFlags{4} = Trig;
40  let TSFlags{5} = Op3;
41
42  // Vector instructions are instructions that must fill all slots in an
43  // instruction group
44  let TSFlags{6} = isVector;
45  let TSFlags{8-7} = FlagOperandIdx;
46  let TSFlags{9} = HasNativeOperands;
47  let TSFlags{10} = Op1;
48  let TSFlags{11} = Op2;
49  let TSFlags{12} = VTXInst;
50  let TSFlags{13} = TEXInst;
51  let TSFlags{14} = ALUInst;
52}
53
54//===----------------------------------------------------------------------===//
55// ALU instructions
56//===----------------------------------------------------------------------===//
57
58class R600ALU_Word0 {
59  field bits<32> Word0;
60
61  bits<11> src0;
62  bits<1>  src0_neg;
63  bits<1>  src0_rel;
64  bits<11> src1;
65  bits<1>  src1_rel;
66  bits<1>  src1_neg;
67  bits<3>  index_mode = 0;
68  bits<2>  pred_sel;
69  bits<1>  last;
70
71  bits<9>  src0_sel  = src0{8-0};
72  bits<2>  src0_chan = src0{10-9};
73  bits<9>  src1_sel  = src1{8-0};
74  bits<2>  src1_chan = src1{10-9};
75
76  let Word0{8-0}   = src0_sel;
77  let Word0{9}     = src0_rel;
78  let Word0{11-10} = src0_chan;
79  let Word0{12}    = src0_neg;
80  let Word0{21-13} = src1_sel;
81  let Word0{22}    = src1_rel;
82  let Word0{24-23} = src1_chan;
83  let Word0{25}    = src1_neg;
84  let Word0{28-26} = index_mode;
85  let Word0{30-29} = pred_sel;
86  let Word0{31}    = last;
87}
88
89class R600ALU_Word1 {
90  field bits<32> Word1;
91
92  bits<11> dst;
93  bits<3>  bank_swizzle;
94  bits<1>  dst_rel;
95  bits<1>  clamp;
96
97  bits<7>  dst_sel  = dst{6-0};
98  bits<2>  dst_chan = dst{10-9};
99
100  let Word1{20-18} = bank_swizzle;
101  let Word1{27-21} = dst_sel;
102  let Word1{28}    = dst_rel;
103  let Word1{30-29} = dst_chan;
104  let Word1{31}    = clamp;
105}
106
107class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
108
109  bits<1>  src0_abs;
110  bits<1>  src1_abs;
111  bits<1>  update_exec_mask;
112  bits<1>  update_pred;
113  bits<1>  write;
114  bits<2>  omod;
115
116  let Word1{0}     = src0_abs;
117  let Word1{1}     = src1_abs;
118  let Word1{2}     = update_exec_mask;
119  let Word1{3}     = update_pred;
120  let Word1{4}     = write;
121  let Word1{6-5}   = omod;
122  let Word1{17-7}  = alu_inst;
123}
124
125class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
126
127  bits<11> src2;
128  bits<1>  src2_rel;
129  bits<1>  src2_neg;
130
131  bits<9>  src2_sel = src2{8-0};
132  bits<2>  src2_chan = src2{10-9};
133
134  let Word1{8-0}   = src2_sel;
135  let Word1{9}     = src2_rel;
136  let Word1{11-10} = src2_chan;
137  let Word1{12}    = src2_neg;
138  let Word1{17-13} = alu_inst;
139}
140
141/*
142XXX: R600 subtarget uses a slightly different encoding than the other
143subtargets.  We currently handle this in R600MCCodeEmitter, but we may
144want to use these instruction classes in the future.
145
146class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
147
148  bits<1>  fog_merge;
149  bits<10> alu_inst;
150
151  let Inst{37}    = fog_merge;
152  let Inst{39-38} = omod;
153  let Inst{49-40} = alu_inst;
154}
155
156class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
157
158  bits<11> alu_inst;
159
160  let Inst{38-37} = omod;
161  let Inst{49-39} = alu_inst;
162}
163*/
164
165//===----------------------------------------------------------------------===//
166// Vertex Fetch instructions
167//===----------------------------------------------------------------------===//
168
169class VTX_WORD0 {
170  field bits<32> Word0;
171  bits<7> src_gpr;
172  bits<5> VC_INST;
173  bits<2> FETCH_TYPE;
174  bits<1> FETCH_WHOLE_QUAD;
175  bits<8> BUFFER_ID;
176  bits<1> SRC_REL;
177  bits<2> SRC_SEL_X;
178
179  let Word0{4-0}   = VC_INST;
180  let Word0{6-5}   = FETCH_TYPE;
181  let Word0{7}     = FETCH_WHOLE_QUAD;
182  let Word0{15-8}  = BUFFER_ID;
183  let Word0{22-16} = src_gpr;
184  let Word0{23}    = SRC_REL;
185  let Word0{25-24} = SRC_SEL_X;
186}
187
188class VTX_WORD0_eg : VTX_WORD0 {
189
190  bits<6> MEGA_FETCH_COUNT;
191
192  let Word0{31-26} = MEGA_FETCH_COUNT;
193}
194
195class VTX_WORD0_cm : VTX_WORD0 {
196
197  bits<2> SRC_SEL_Y;
198  bits<2> STRUCTURED_READ;
199  bits<1> LDS_REQ;
200  bits<1> COALESCED_READ;
201
202  let Word0{27-26} = SRC_SEL_Y;
203  let Word0{29-28} = STRUCTURED_READ;
204  let Word0{30}    = LDS_REQ;
205  let Word0{31}    = COALESCED_READ;
206}
207
208class VTX_WORD1_GPR {
209  field bits<32> Word1;
210  bits<7> dst_gpr;
211  bits<1> DST_REL;
212  bits<3> DST_SEL_X;
213  bits<3> DST_SEL_Y;
214  bits<3> DST_SEL_Z;
215  bits<3> DST_SEL_W;
216  bits<1> USE_CONST_FIELDS;
217  bits<6> DATA_FORMAT;
218  bits<2> NUM_FORMAT_ALL;
219  bits<1> FORMAT_COMP_ALL;
220  bits<1> SRF_MODE_ALL;
221
222  let Word1{6-0} = dst_gpr;
223  let Word1{7}    = DST_REL;
224  let Word1{8}    = 0; // Reserved
225  let Word1{11-9} = DST_SEL_X;
226  let Word1{14-12} = DST_SEL_Y;
227  let Word1{17-15} = DST_SEL_Z;
228  let Word1{20-18} = DST_SEL_W;
229  let Word1{21}    = USE_CONST_FIELDS;
230  let Word1{27-22} = DATA_FORMAT;
231  let Word1{29-28} = NUM_FORMAT_ALL;
232  let Word1{30}    = FORMAT_COMP_ALL;
233  let Word1{31}    = SRF_MODE_ALL;
234}
235
236//===----------------------------------------------------------------------===//
237// Texture fetch instructions
238//===----------------------------------------------------------------------===//
239
240class TEX_WORD0 {
241  field bits<32> Word0;
242
243  bits<5> TEX_INST;
244  bits<2> INST_MOD;
245  bits<1> FETCH_WHOLE_QUAD;
246  bits<8> RESOURCE_ID;
247  bits<7> SRC_GPR;
248  bits<1> SRC_REL;
249  bits<1> ALT_CONST;
250  bits<2> RESOURCE_INDEX_MODE;
251  bits<2> SAMPLER_INDEX_MODE;
252
253  let Word0{4-0} = TEX_INST;
254  let Word0{6-5} = INST_MOD;
255  let Word0{7} = FETCH_WHOLE_QUAD;
256  let Word0{15-8} = RESOURCE_ID;
257  let Word0{22-16} = SRC_GPR;
258  let Word0{23} = SRC_REL;
259  let Word0{24} = ALT_CONST;
260  let Word0{26-25} = RESOURCE_INDEX_MODE;
261  let Word0{28-27} = SAMPLER_INDEX_MODE;
262}
263
264class TEX_WORD1 {
265  field bits<32> Word1;
266
267  bits<7> DST_GPR;
268  bits<1> DST_REL;
269  bits<3> DST_SEL_X;
270  bits<3> DST_SEL_Y;
271  bits<3> DST_SEL_Z;
272  bits<3> DST_SEL_W;
273  bits<7> LOD_BIAS;
274  bits<1> COORD_TYPE_X;
275  bits<1> COORD_TYPE_Y;
276  bits<1> COORD_TYPE_Z;
277  bits<1> COORD_TYPE_W;
278
279  let Word1{6-0} = DST_GPR;
280  let Word1{7} = DST_REL;
281  let Word1{11-9} = DST_SEL_X;
282  let Word1{14-12} = DST_SEL_Y;
283  let Word1{17-15} = DST_SEL_Z;
284  let Word1{20-18} = DST_SEL_W;
285  let Word1{27-21} = LOD_BIAS;
286  let Word1{28} = COORD_TYPE_X;
287  let Word1{29} = COORD_TYPE_Y;
288  let Word1{30} = COORD_TYPE_Z;
289  let Word1{31} = COORD_TYPE_W;
290}
291
292class TEX_WORD2 {
293  field bits<32> Word2;
294
295  bits<5> OFFSET_X;
296  bits<5> OFFSET_Y;
297  bits<5> OFFSET_Z;
298  bits<5> SAMPLER_ID;
299  bits<3> SRC_SEL_X;
300  bits<3> SRC_SEL_Y;
301  bits<3> SRC_SEL_Z;
302  bits<3> SRC_SEL_W;
303
304  let Word2{4-0} = OFFSET_X;
305  let Word2{9-5} = OFFSET_Y;
306  let Word2{14-10} = OFFSET_Z;
307  let Word2{19-15} = SAMPLER_ID;
308  let Word2{22-20} = SRC_SEL_X;
309  let Word2{25-23} = SRC_SEL_Y;
310  let Word2{28-26} = SRC_SEL_Z;
311  let Word2{31-29} = SRC_SEL_W;
312}
313
314//===----------------------------------------------------------------------===//
315// Control Flow Instructions
316//===----------------------------------------------------------------------===//
317
318class CF_WORD1_R600 {
319  field bits<32> Word1;
320
321  bits<3> POP_COUNT;
322  bits<5> CF_CONST;
323  bits<2> COND;
324  bits<3> COUNT;
325  bits<6> CALL_COUNT;
326  bits<1> COUNT_3;
327  bits<1> END_OF_PROGRAM;
328  bits<1> VALID_PIXEL_MODE;
329  bits<7> CF_INST;
330  bits<1> WHOLE_QUAD_MODE;
331  bits<1> BARRIER;
332
333  let Word1{2-0} = POP_COUNT;
334  let Word1{7-3} = CF_CONST;
335  let Word1{9-8} = COND;
336  let Word1{12-10} = COUNT;
337  let Word1{18-13} = CALL_COUNT;
338  let Word1{19} = COUNT_3;
339  let Word1{21} = END_OF_PROGRAM;
340  let Word1{22} = VALID_PIXEL_MODE;
341  let Word1{29-23} = CF_INST;
342  let Word1{30} = WHOLE_QUAD_MODE;
343  let Word1{31} = BARRIER;
344}
345
346class CF_WORD0_EG {
347  field bits<32> Word0;
348
349  bits<24> ADDR;
350  bits<3> JUMPTABLE_SEL;
351
352  let Word0{23-0} = ADDR;
353  let Word0{26-24} = JUMPTABLE_SEL;
354}
355
356class CF_WORD1_EG {
357  field bits<32> Word1;
358
359  bits<3> POP_COUNT;
360  bits<5> CF_CONST;
361  bits<2> COND;
362  bits<6> COUNT;
363  bits<1> VALID_PIXEL_MODE;
364  bits<1> END_OF_PROGRAM;
365  bits<8> CF_INST;
366  bits<1> BARRIER;
367
368  let Word1{2-0} = POP_COUNT;
369  let Word1{7-3} = CF_CONST;
370  let Word1{9-8} = COND;
371  let Word1{15-10} = COUNT;
372  let Word1{20} = VALID_PIXEL_MODE;
373  let Word1{21} = END_OF_PROGRAM;
374  let Word1{29-22} = CF_INST;
375  let Word1{31} = BARRIER;
376}
377
378class CF_ALU_WORD0 {
379  field bits<32> Word0;
380
381  bits<22> ADDR;
382  bits<4> KCACHE_BANK0;
383  bits<4> KCACHE_BANK1;
384  bits<2> KCACHE_MODE0;
385
386  let Word0{21-0} = ADDR;
387  let Word0{25-22} = KCACHE_BANK0;
388  let Word0{29-26} = KCACHE_BANK1;
389  let Word0{31-30} = KCACHE_MODE0;
390}
391
392class CF_ALU_WORD1 {
393  field bits<32> Word1;
394
395  bits<2> KCACHE_MODE1;
396  bits<8> KCACHE_ADDR0;
397  bits<8> KCACHE_ADDR1;
398  bits<7> COUNT;
399  bits<1> ALT_CONST;
400  bits<4> CF_INST;
401  bits<1> WHOLE_QUAD_MODE;
402  bits<1> BARRIER;
403
404  let Word1{1-0} = KCACHE_MODE1;
405  let Word1{9-2} = KCACHE_ADDR0;
406  let Word1{17-10} = KCACHE_ADDR1;
407  let Word1{24-18} = COUNT;
408  let Word1{25} = ALT_CONST;
409  let Word1{29-26} = CF_INST;
410  let Word1{30} = WHOLE_QUAD_MODE;
411  let Word1{31} = BARRIER;
412}
413
414class CF_ALLOC_EXPORT_WORD0_RAT {
415  field bits<32> Word0;
416
417  bits<4> rat_id;
418  bits<6> rat_inst;
419  bits<2> rim;
420  bits<2> type;
421  bits<7> rw_gpr;
422  bits<1> rw_rel;
423  bits<7> index_gpr;
424  bits<2> elem_size;
425
426  let Word0{3-0}   = rat_id;
427  let Word0{9-4}   = rat_inst;
428  let Word0{10}    = 0; // Reserved
429  let Word0{12-11} = rim;
430  let Word0{14-13} = type;
431  let Word0{21-15} = rw_gpr;
432  let Word0{22}    = rw_rel;
433  let Word0{29-23} = index_gpr;
434  let Word0{31-30} = elem_size;
435}
436
437class CF_ALLOC_EXPORT_WORD1_BUF {
438  field bits<32> Word1;
439
440  bits<12> array_size;
441  bits<4>  comp_mask;
442  bits<4>  burst_count;
443  bits<1>  vpm;
444  bits<1>  eop;
445  bits<8>  cf_inst;
446  bits<1>  mark;
447  bits<1>  barrier;
448
449  let Word1{11-0} = array_size;
450  let Word1{15-12} = comp_mask;
451  let Word1{19-16} = burst_count;
452  let Word1{20}    = vpm;
453  let Word1{21}    = eop;
454  let Word1{29-22} = cf_inst;
455  let Word1{30}    = mark;
456  let Word1{31}    = barrier;
457}
458