| b3df27d4402d8c8fc81d5acec812035360806cdc |
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04-Sep-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Use SchedModel enum for is{Trans,Vector}Only functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrFormats.td
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| 8e78012457682d335ee97cf2859dfe03b7e2ae93 |
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26-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add support for i8 and i16 local memory stores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189223 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrFormats.td
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| e7ac2ed1c268891a856ab38db1e34372a79da86a |
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16-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add IsExport bit to TableGen instruction definitions
Tested-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188516 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrFormats.td
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| af2ea2a4fb785652ec79dbe179c499823ea45f63 |
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31-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
This reverts commit 3f1de26cb5cc0543a6a1d71259a7a39d97139051.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrFormats.td
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| 3f1de26cb5cc0543a6a1d71259a7a39d97139051 |
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31-Jul-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600: Use SchedModel enum for is{Trans,Vector}Only functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187512 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrFormats.td
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| e3d4cbc7d25061441adafa47450a31571c87bf85 |
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28-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add local memory support via LDS
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrFormats.td
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| 7e9381951eb4dadf9c59257786416ac51a6a6c09 |
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28-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add ALUInst bit to tablegen definitions v2
v2:
- Remove functions left over from a previous rebase.
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrFormats.td
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| d6055262d23b1a8f2b5c74ab94fc6c143aca1c45 |
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15-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Use correct encoding for Vertex Fetch instructions on Cayman
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184016 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrFormats.td
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| c30b232349b44dcd158eaa5b4e8599615ae8144e |
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15-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184014 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrFormats.td
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| 2def95fc1e5537e5c156bd12027d41212e0b2fc2 |
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15-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Move instruction encoding definitions into a separate .td file
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184013 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/R600InstrFormats.td
|