R600InstrFormats.td revision c30b232349b44dcd158eaa5b4e8599615ae8144e 
1//===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// R600 Instruction format definitions.
11//
12//===----------------------------------------------------------------------===//
13
14class InstR600 <dag outs, dag ins, string asm, list<dag> pattern,
15                InstrItinClass itin>
16    : AMDGPUInst <outs, ins, asm, pattern> {
17
18  field bits<64> Inst;
19  bit TransOnly = 0;
20  bit Trig = 0;
21  bit Op3 = 0;
22  bit isVector = 0;
23  bits<2> FlagOperandIdx = 0;
24  bit Op1 = 0;
25  bit Op2 = 0;
26  bit HasNativeOperands = 0;
27  bit VTXInst = 0;
28  bit TEXInst = 0;
29
30  let Namespace = "AMDGPU";
31  let OutOperandList = outs;
32  let InOperandList = ins;
33  let AsmString = asm;
34  let Pattern = pattern;
35  let Itinerary = itin;
36
37  let TSFlags{0} = TransOnly;
38  let TSFlags{4} = Trig;
39  let TSFlags{5} = Op3;
40
41  // Vector instructions are instructions that must fill all slots in an
42  // instruction group
43  let TSFlags{6} = isVector;
44  let TSFlags{8-7} = FlagOperandIdx;
45  let TSFlags{9} = HasNativeOperands;
46  let TSFlags{10} = Op1;
47  let TSFlags{11} = Op2;
48  let TSFlags{12} = VTXInst;
49  let TSFlags{13} = TEXInst;
50}
51
52//===----------------------------------------------------------------------===//
53// ALU instructions
54//===----------------------------------------------------------------------===//
55
56class R600ALU_Word0 {
57  field bits<32> Word0;
58
59  bits<11> src0;
60  bits<1>  src0_neg;
61  bits<1>  src0_rel;
62  bits<11> src1;
63  bits<1>  src1_rel;
64  bits<1>  src1_neg;
65  bits<3>  index_mode = 0;
66  bits<2>  pred_sel;
67  bits<1>  last;
68
69  bits<9>  src0_sel  = src0{8-0};
70  bits<2>  src0_chan = src0{10-9};
71  bits<9>  src1_sel  = src1{8-0};
72  bits<2>  src1_chan = src1{10-9};
73
74  let Word0{8-0}   = src0_sel;
75  let Word0{9}     = src0_rel;
76  let Word0{11-10} = src0_chan;
77  let Word0{12}    = src0_neg;
78  let Word0{21-13} = src1_sel;
79  let Word0{22}    = src1_rel;
80  let Word0{24-23} = src1_chan;
81  let Word0{25}    = src1_neg;
82  let Word0{28-26} = index_mode;
83  let Word0{30-29} = pred_sel;
84  let Word0{31}    = last;
85}
86
87class R600ALU_Word1 {
88  field bits<32> Word1;
89
90  bits<11> dst;
91  bits<3>  bank_swizzle;
92  bits<1>  dst_rel;
93  bits<1>  clamp;
94
95  bits<7>  dst_sel  = dst{6-0};
96  bits<2>  dst_chan = dst{10-9};
97
98  let Word1{20-18} = bank_swizzle;
99  let Word1{27-21} = dst_sel;
100  let Word1{28}    = dst_rel;
101  let Word1{30-29} = dst_chan;
102  let Word1{31}    = clamp;
103}
104
105class R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{
106
107  bits<1>  src0_abs;
108  bits<1>  src1_abs;
109  bits<1>  update_exec_mask;
110  bits<1>  update_pred;
111  bits<1>  write;
112  bits<2>  omod;
113
114  let Word1{0}     = src0_abs;
115  let Word1{1}     = src1_abs;
116  let Word1{2}     = update_exec_mask;
117  let Word1{3}     = update_pred;
118  let Word1{4}     = write;
119  let Word1{6-5}   = omod;
120  let Word1{17-7}  = alu_inst;
121}
122
123class R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{
124
125  bits<11> src2;
126  bits<1>  src2_rel;
127  bits<1>  src2_neg;
128
129  bits<9>  src2_sel = src2{8-0};
130  bits<2>  src2_chan = src2{10-9};
131
132  let Word1{8-0}   = src2_sel;
133  let Word1{9}     = src2_rel;
134  let Word1{11-10} = src2_chan;
135  let Word1{12}    = src2_neg;
136  let Word1{17-13} = alu_inst;
137}
138
139/*
140XXX: R600 subtarget uses a slightly different encoding than the other
141subtargets.  We currently handle this in R600MCCodeEmitter, but we may
142want to use these instruction classes in the future.
143
144class R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 {
145
146  bits<1>  fog_merge;
147  bits<10> alu_inst;
148
149  let Inst{37}    = fog_merge;
150  let Inst{39-38} = omod;
151  let Inst{49-40} = alu_inst;
152}
153
154class R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 {
155
156  bits<11> alu_inst;
157
158  let Inst{38-37} = omod;
159  let Inst{49-39} = alu_inst;
160}
161*/
162
163//===----------------------------------------------------------------------===//
164// Vertex Fetch instructions
165//===----------------------------------------------------------------------===//
166
167class VTX_WORD0 {
168  field bits<32> Word0;
169  bits<7> SRC_GPR;
170  bits<5> VC_INST;
171  bits<2> FETCH_TYPE;
172  bits<1> FETCH_WHOLE_QUAD;
173  bits<8> BUFFER_ID;
174  bits<1> SRC_REL;
175  bits<2> SRC_SEL_X;
176  bits<6> MEGA_FETCH_COUNT;
177
178  let Word0{4-0}   = VC_INST;
179  let Word0{6-5}   = FETCH_TYPE;
180  let Word0{7}     = FETCH_WHOLE_QUAD;
181  let Word0{15-8}  = BUFFER_ID;
182  let Word0{22-16} = SRC_GPR;
183  let Word0{23}    = SRC_REL;
184  let Word0{25-24} = SRC_SEL_X;
185  let Word0{31-26} = MEGA_FETCH_COUNT;
186}
187
188class VTX_WORD1_GPR {
189  field bits<32> Word1;
190  bits<7> DST_GPR;
191  bits<1> DST_REL;
192  bits<3> DST_SEL_X;
193  bits<3> DST_SEL_Y;
194  bits<3> DST_SEL_Z;
195  bits<3> DST_SEL_W;
196  bits<1> USE_CONST_FIELDS;
197  bits<6> DATA_FORMAT;
198  bits<2> NUM_FORMAT_ALL;
199  bits<1> FORMAT_COMP_ALL;
200  bits<1> SRF_MODE_ALL;
201
202  let Word1{6-0} = DST_GPR;
203  let Word1{7}    = DST_REL;
204  let Word1{8}    = 0; // Reserved
205  let Word1{11-9} = DST_SEL_X;
206  let Word1{14-12} = DST_SEL_Y;
207  let Word1{17-15} = DST_SEL_Z;
208  let Word1{20-18} = DST_SEL_W;
209  let Word1{21}    = USE_CONST_FIELDS;
210  let Word1{27-22} = DATA_FORMAT;
211  let Word1{29-28} = NUM_FORMAT_ALL;
212  let Word1{30}    = FORMAT_COMP_ALL;
213  let Word1{31}    = SRF_MODE_ALL;
214}
215
216//===----------------------------------------------------------------------===//
217// Texture fetch instructions
218//===----------------------------------------------------------------------===//
219
220class TEX_WORD0 {
221  field bits<32> Word0;
222
223  bits<5> TEX_INST;
224  bits<2> INST_MOD;
225  bits<1> FETCH_WHOLE_QUAD;
226  bits<8> RESOURCE_ID;
227  bits<7> SRC_GPR;
228  bits<1> SRC_REL;
229  bits<1> ALT_CONST;
230  bits<2> RESOURCE_INDEX_MODE;
231  bits<2> SAMPLER_INDEX_MODE;
232
233  let Word0{4-0} = TEX_INST;
234  let Word0{6-5} = INST_MOD;
235  let Word0{7} = FETCH_WHOLE_QUAD;
236  let Word0{15-8} = RESOURCE_ID;
237  let Word0{22-16} = SRC_GPR;
238  let Word0{23} = SRC_REL;
239  let Word0{24} = ALT_CONST;
240  let Word0{26-25} = RESOURCE_INDEX_MODE;
241  let Word0{28-27} = SAMPLER_INDEX_MODE;
242}
243
244class TEX_WORD1 {
245  field bits<32> Word1;
246
247  bits<7> DST_GPR;
248  bits<1> DST_REL;
249  bits<3> DST_SEL_X;
250  bits<3> DST_SEL_Y;
251  bits<3> DST_SEL_Z;
252  bits<3> DST_SEL_W;
253  bits<7> LOD_BIAS;
254  bits<1> COORD_TYPE_X;
255  bits<1> COORD_TYPE_Y;
256  bits<1> COORD_TYPE_Z;
257  bits<1> COORD_TYPE_W;
258
259  let Word1{6-0} = DST_GPR;
260  let Word1{7} = DST_REL;
261  let Word1{11-9} = DST_SEL_X;
262  let Word1{14-12} = DST_SEL_Y;
263  let Word1{17-15} = DST_SEL_Z;
264  let Word1{20-18} = DST_SEL_W;
265  let Word1{27-21} = LOD_BIAS;
266  let Word1{28} = COORD_TYPE_X;
267  let Word1{29} = COORD_TYPE_Y;
268  let Word1{30} = COORD_TYPE_Z;
269  let Word1{31} = COORD_TYPE_W;
270}
271
272class TEX_WORD2 {
273  field bits<32> Word2;
274
275  bits<5> OFFSET_X;
276  bits<5> OFFSET_Y;
277  bits<5> OFFSET_Z;
278  bits<5> SAMPLER_ID;
279  bits<3> SRC_SEL_X;
280  bits<3> SRC_SEL_Y;
281  bits<3> SRC_SEL_Z;
282  bits<3> SRC_SEL_W;
283
284  let Word2{4-0} = OFFSET_X;
285  let Word2{9-5} = OFFSET_Y;
286  let Word2{14-10} = OFFSET_Z;
287  let Word2{19-15} = SAMPLER_ID;
288  let Word2{22-20} = SRC_SEL_X;
289  let Word2{25-23} = SRC_SEL_Y;
290  let Word2{28-26} = SRC_SEL_Z;
291  let Word2{31-29} = SRC_SEL_W;
292}
293
294//===----------------------------------------------------------------------===//
295// Control Flow Instructions
296//===----------------------------------------------------------------------===//
297
298class CF_WORD1_R600 {
299  field bits<32> Word1;
300
301  bits<3> POP_COUNT;
302  bits<5> CF_CONST;
303  bits<2> COND;
304  bits<3> COUNT;
305  bits<6> CALL_COUNT;
306  bits<1> COUNT_3;
307  bits<1> END_OF_PROGRAM;
308  bits<1> VALID_PIXEL_MODE;
309  bits<7> CF_INST;
310  bits<1> WHOLE_QUAD_MODE;
311  bits<1> BARRIER;
312
313  let Word1{2-0} = POP_COUNT;
314  let Word1{7-3} = CF_CONST;
315  let Word1{9-8} = COND;
316  let Word1{12-10} = COUNT;
317  let Word1{18-13} = CALL_COUNT;
318  let Word1{19} = COUNT_3;
319  let Word1{21} = END_OF_PROGRAM;
320  let Word1{22} = VALID_PIXEL_MODE;
321  let Word1{29-23} = CF_INST;
322  let Word1{30} = WHOLE_QUAD_MODE;
323  let Word1{31} = BARRIER;
324}
325
326class CF_WORD0_EG {
327  field bits<32> Word0;
328
329  bits<24> ADDR;
330  bits<3> JUMPTABLE_SEL;
331
332  let Word0{23-0} = ADDR;
333  let Word0{26-24} = JUMPTABLE_SEL;
334}
335
336class CF_WORD1_EG {
337  field bits<32> Word1;
338
339  bits<3> POP_COUNT;
340  bits<5> CF_CONST;
341  bits<2> COND;
342  bits<6> COUNT;
343  bits<1> VALID_PIXEL_MODE;
344  bits<1> END_OF_PROGRAM;
345  bits<8> CF_INST;
346  bits<1> BARRIER;
347
348  let Word1{2-0} = POP_COUNT;
349  let Word1{7-3} = CF_CONST;
350  let Word1{9-8} = COND;
351  let Word1{15-10} = COUNT;
352  let Word1{20} = VALID_PIXEL_MODE;
353  let Word1{21} = END_OF_PROGRAM;
354  let Word1{29-22} = CF_INST;
355  let Word1{31} = BARRIER;
356}
357
358class CF_ALU_WORD0 {
359  field bits<32> Word0;
360
361  bits<22> ADDR;
362  bits<4> KCACHE_BANK0;
363  bits<4> KCACHE_BANK1;
364  bits<2> KCACHE_MODE0;
365
366  let Word0{21-0} = ADDR;
367  let Word0{25-22} = KCACHE_BANK0;
368  let Word0{29-26} = KCACHE_BANK1;
369  let Word0{31-30} = KCACHE_MODE0;
370}
371
372class CF_ALU_WORD1 {
373  field bits<32> Word1;
374
375  bits<2> KCACHE_MODE1;
376  bits<8> KCACHE_ADDR0;
377  bits<8> KCACHE_ADDR1;
378  bits<7> COUNT;
379  bits<1> ALT_CONST;
380  bits<4> CF_INST;
381  bits<1> WHOLE_QUAD_MODE;
382  bits<1> BARRIER;
383
384  let Word1{1-0} = KCACHE_MODE1;
385  let Word1{9-2} = KCACHE_ADDR0;
386  let Word1{17-10} = KCACHE_ADDR1;
387  let Word1{24-18} = COUNT;
388  let Word1{25} = ALT_CONST;
389  let Word1{29-26} = CF_INST;
390  let Word1{30} = WHOLE_QUAD_MODE;
391  let Word1{31} = BARRIER;
392}
393
394class CF_ALLOC_EXPORT_WORD0_RAT {
395  field bits<32> Word0;
396
397  bits<4> rat_id;
398  bits<6> rat_inst;
399  bits<2> rim;
400  bits<2> type;
401  bits<7> rw_gpr;
402  bits<1> rw_rel;
403  bits<7> index_gpr;
404  bits<2> elem_size;
405
406  let Word0{3-0}   = rat_id;
407  let Word0{9-4}   = rat_inst;
408  let Word0{10}    = 0; // Reserved
409  let Word0{12-11} = rim;
410  let Word0{14-13} = type;
411  let Word0{21-15} = rw_gpr;
412  let Word0{22}    = rw_rel;
413  let Word0{29-23} = index_gpr;
414  let Word0{31-30} = elem_size;
415}
416
417class CF_ALLOC_EXPORT_WORD1_BUF {
418  field bits<32> Word1;
419
420  bits<12> array_size;
421  bits<4>  comp_mask;
422  bits<4>  burst_count;
423  bits<1>  vpm;
424  bits<1>  eop;
425  bits<8>  cf_inst;
426  bits<1>  mark;
427  bits<1>  barrier;
428
429  let Word1{11-0} = array_size;
430  let Word1{15-12} = comp_mask;
431  let Word1{19-16} = burst_count;
432  let Word1{20}    = vpm;
433  let Word1{21}    = eop;
434  let Word1{29-22} = cf_inst;
435  let Word1{30}    = mark;
436  let Word1{31}    = barrier;
437}
438