SIISelLowering.cpp revision 204a2d32ba44ff150e2201d7e0900815b4446bad 
1//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Custom DAG lowering for SI
12//
13//===----------------------------------------------------------------------===//
14
15#include "SIISelLowering.h"
16#include "AMDIL.h"
17#include "AMDILIntrinsicInfo.h"
18#include "SIInstrInfo.h"
19#include "SIMachineFunctionInfo.h"
20#include "SIRegisterInfo.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24
25using namespace llvm;
26
27SITargetLowering::SITargetLowering(TargetMachine &TM) :
28    AMDGPUTargetLowering(TM),
29    TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())),
30    TRI(TM.getRegisterInfo()) {
31
32  addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
33  addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
34
35  addRegisterClass(MVT::v16i8, &AMDGPU::SReg_128RegClass);
36  addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
37  addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
38
39  addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
40  addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
41
42  addRegisterClass(MVT::v1i32, &AMDGPU::VReg_32RegClass);
43
44  addRegisterClass(MVT::v2i32, &AMDGPU::VReg_64RegClass);
45  addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
46
47  addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
48  addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
49
50  addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
51  addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
52
53  addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
54  addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
55
56  computeRegisterProperties();
57
58  setOperationAction(ISD::ADD, MVT::i64, Legal);
59  setOperationAction(ISD::ADD, MVT::i32, Legal);
60
61  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
62
63  // We need to custom lower loads from the USER_SGPR address space, so we can
64  // add the SGPRs as livein registers.
65  setOperationAction(ISD::LOAD, MVT::i32, Custom);
66  setOperationAction(ISD::LOAD, MVT::i64, Custom);
67
68  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
69  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
70
71  setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
72  setTargetDAGCombine(ISD::SELECT_CC);
73
74  setTargetDAGCombine(ISD::SETCC);
75}
76
77MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
78    MachineInstr * MI, MachineBasicBlock * BB) const {
79  MachineRegisterInfo & MRI = BB->getParent()->getRegInfo();
80  MachineBasicBlock::iterator I = MI;
81
82  switch (MI->getOpcode()) {
83  default:
84    return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
85  case AMDGPU::BRANCH: return BB;
86  case AMDGPU::SHADER_TYPE:
87    BB->getParent()->getInfo<SIMachineFunctionInfo>()->ShaderType =
88                                        MI->getOperand(0).getImm();
89    MI->eraseFromParent();
90    break;
91
92  case AMDGPU::SI_INTERP:
93    LowerSI_INTERP(MI, *BB, I, MRI);
94    break;
95  case AMDGPU::SI_WQM:
96    LowerSI_WQM(MI, *BB, I, MRI);
97    break;
98  }
99  return BB;
100}
101
102void SITargetLowering::LowerSI_WQM(MachineInstr *MI, MachineBasicBlock &BB,
103    MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
104  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_WQM_B64), AMDGPU::EXEC)
105          .addReg(AMDGPU::EXEC);
106
107  MI->eraseFromParent();
108}
109
110void SITargetLowering::LowerSI_INTERP(MachineInstr *MI, MachineBasicBlock &BB,
111    MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const {
112  unsigned tmp = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
113  unsigned M0 = MRI.createVirtualRegister(&AMDGPU::M0RegRegClass);
114  MachineOperand dst = MI->getOperand(0);
115  MachineOperand iReg = MI->getOperand(1);
116  MachineOperand jReg = MI->getOperand(2);
117  MachineOperand attr_chan = MI->getOperand(3);
118  MachineOperand attr = MI->getOperand(4);
119  MachineOperand params = MI->getOperand(5);
120
121  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::S_MOV_B32), M0)
122          .addOperand(params);
123
124  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P1_F32), tmp)
125          .addOperand(iReg)
126          .addOperand(attr_chan)
127          .addOperand(attr)
128          .addReg(M0);
129
130  BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_INTERP_P2_F32))
131          .addOperand(dst)
132          .addReg(tmp)
133          .addOperand(jReg)
134          .addOperand(attr_chan)
135          .addOperand(attr)
136          .addReg(M0);
137
138  MI->eraseFromParent();
139}
140
141EVT SITargetLowering::getSetCCResultType(EVT VT) const {
142  return MVT::i1;
143}
144
145//===----------------------------------------------------------------------===//
146// Custom DAG Lowering Operations
147//===----------------------------------------------------------------------===//
148
149SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
150  switch (Op.getOpcode()) {
151  default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
152  case ISD::BRCOND: return LowerBRCOND(Op, DAG);
153  case ISD::LOAD: return LowerLOAD(Op, DAG);
154  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
155  case ISD::INTRINSIC_WO_CHAIN: {
156    unsigned IntrinsicID =
157                         cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
158    EVT VT = Op.getValueType();
159    switch (IntrinsicID) {
160    case AMDGPUIntrinsic::SI_vs_load_buffer_index:
161      return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
162                                  AMDGPU::VGPR0, VT);
163    default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
164    }
165    break;
166  }
167  }
168  return SDValue();
169}
170
171/// \brief Helper function for LowerBRCOND
172static SDNode *findUser(SDValue Value, unsigned Opcode) {
173
174  SDNode *Parent = Value.getNode();
175  for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
176       I != E; ++I) {
177
178    if (I.getUse().get() != Value)
179      continue;
180
181    if (I->getOpcode() == Opcode)
182      return *I;
183  }
184  return 0;
185}
186
187/// This transforms the control flow intrinsics to get the branch destination as
188/// last parameter, also switches branch target with BR if the need arise
189SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
190                                      SelectionDAG &DAG) const {
191
192  DebugLoc DL = BRCOND.getDebugLoc();
193
194  SDNode *Intr = BRCOND.getOperand(1).getNode();
195  SDValue Target = BRCOND.getOperand(2);
196  SDNode *BR = 0;
197
198  if (Intr->getOpcode() == ISD::SETCC) {
199    // As long as we negate the condition everything is fine
200    SDNode *SetCC = Intr;
201    assert(SetCC->getConstantOperandVal(1) == 1);
202    assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
203           ISD::SETNE);
204    Intr = SetCC->getOperand(0).getNode();
205
206  } else {
207    // Get the target from BR if we don't negate the condition
208    BR = findUser(BRCOND, ISD::BR);
209    Target = BR->getOperand(1);
210  }
211
212  assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
213
214  // Build the result and
215  SmallVector<EVT, 4> Res;
216  for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
217    Res.push_back(Intr->getValueType(i));
218
219  // operands of the new intrinsic call
220  SmallVector<SDValue, 4> Ops;
221  Ops.push_back(BRCOND.getOperand(0));
222  for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
223    Ops.push_back(Intr->getOperand(i));
224  Ops.push_back(Target);
225
226  // build the new intrinsic call
227  SDNode *Result = DAG.getNode(
228    Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
229    DAG.getVTList(Res.data(), Res.size()), Ops.data(), Ops.size()).getNode();
230
231  if (BR) {
232    // Give the branch instruction our target
233    SDValue Ops[] = {
234      BR->getOperand(0),
235      BRCOND.getOperand(2)
236    };
237    DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops, 2);
238  }
239
240  SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
241
242  // Copy the intrinsic results to registers
243  for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
244    SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
245    if (!CopyToReg)
246      continue;
247
248    Chain = DAG.getCopyToReg(
249      Chain, DL,
250      CopyToReg->getOperand(1),
251      SDValue(Result, i - 1),
252      SDValue());
253
254    DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
255  }
256
257  // Remove the old intrinsic from the chain
258  DAG.ReplaceAllUsesOfValueWith(
259    SDValue(Intr, Intr->getNumValues() - 1),
260    Intr->getOperand(0));
261
262  return Chain;
263}
264
265SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
266  EVT VT = Op.getValueType();
267  LoadSDNode *Ptr = dyn_cast<LoadSDNode>(Op);
268
269  assert(Ptr);
270
271  unsigned AddrSpace = Ptr->getPointerInfo().getAddrSpace();
272
273  // We only need to lower USER_SGPR address space loads
274  if (AddrSpace != AMDGPUAS::USER_SGPR_ADDRESS) {
275    return SDValue();
276  }
277
278  // Loads from the USER_SGPR address space can only have constant value
279  // pointers.
280  ConstantSDNode *BasePtr = dyn_cast<ConstantSDNode>(Ptr->getBasePtr());
281  assert(BasePtr);
282
283  unsigned TypeDwordWidth = VT.getSizeInBits() / 32;
284  const TargetRegisterClass * dstClass;
285  switch (TypeDwordWidth) {
286    default:
287      assert(!"USER_SGPR value size not implemented");
288      return SDValue();
289    case 1:
290      dstClass = &AMDGPU::SReg_32RegClass;
291      break;
292    case 2:
293      dstClass = &AMDGPU::SReg_64RegClass;
294      break;
295  }
296  uint64_t Index = BasePtr->getZExtValue();
297  assert(Index % TypeDwordWidth == 0 && "USER_SGPR not properly aligned");
298  unsigned SGPRIndex = Index / TypeDwordWidth;
299  unsigned Reg = dstClass->getRegister(SGPRIndex);
300
301  DAG.ReplaceAllUsesOfValueWith(Op, CreateLiveInRegister(DAG, dstClass, Reg,
302                                                         VT));
303  return SDValue();
304}
305
306SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
307  SDValue LHS = Op.getOperand(0);
308  SDValue RHS = Op.getOperand(1);
309  SDValue True = Op.getOperand(2);
310  SDValue False = Op.getOperand(3);
311  SDValue CC = Op.getOperand(4);
312  EVT VT = Op.getValueType();
313  DebugLoc DL = Op.getDebugLoc();
314
315  // Possible Min/Max pattern
316  SDValue MinMax = LowerMinMax(Op, DAG);
317  if (MinMax.getNode()) {
318    return MinMax;
319  }
320
321  SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
322  return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
323}
324
325//===----------------------------------------------------------------------===//
326// Custom DAG optimizations
327//===----------------------------------------------------------------------===//
328
329SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
330                                            DAGCombinerInfo &DCI) const {
331  SelectionDAG &DAG = DCI.DAG;
332  DebugLoc DL = N->getDebugLoc();
333  EVT VT = N->getValueType(0);
334
335  switch (N->getOpcode()) {
336    default: break;
337    case ISD::SELECT_CC: {
338      N->dump();
339      ConstantSDNode *True, *False;
340      // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
341      if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
342          && (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
343          && True->isAllOnesValue()
344          && False->isNullValue()
345          && VT == MVT::i1) {
346        return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
347                           N->getOperand(1), N->getOperand(4));
348
349      }
350      break;
351    }
352    case ISD::SETCC: {
353      SDValue Arg0 = N->getOperand(0);
354      SDValue Arg1 = N->getOperand(1);
355      SDValue CC = N->getOperand(2);
356      ConstantSDNode * C = NULL;
357      ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
358
359      // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
360      if (VT == MVT::i1
361          && Arg0.getOpcode() == ISD::SIGN_EXTEND
362          && Arg0.getOperand(0).getValueType() == MVT::i1
363          && (C = dyn_cast<ConstantSDNode>(Arg1))
364          && C->isNullValue()
365          && CCOp == ISD::SETNE) {
366        return SimplifySetCC(VT, Arg0.getOperand(0),
367                             DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
368      }
369      break;
370    }
371  }
372  return SDValue();
373}
374
375/// \brief Test if RegClass is one of the VSrc classes
376static bool isVSrc(unsigned RegClass) {
377  return AMDGPU::VSrc_32RegClassID == RegClass ||
378         AMDGPU::VSrc_64RegClassID == RegClass;
379}
380
381/// \brief Test if RegClass is one of the SSrc classes
382static bool isSSrc(unsigned RegClass) {
383  return AMDGPU::SSrc_32RegClassID == RegClass ||
384         AMDGPU::SSrc_64RegClassID == RegClass;
385}
386
387/// \brief Analyze the possible immediate value Op
388///
389/// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
390/// and the immediate value if it's a literal immediate
391int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
392
393  union {
394    int32_t I;
395    float F;
396  } Imm;
397
398  if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N))
399    Imm.I = Node->getSExtValue();
400  else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
401    Imm.F = Node->getValueAPF().convertToFloat();
402  else
403    return -1; // It isn't an immediate
404
405  if ((Imm.I >= -16 && Imm.I <= 64) ||
406      Imm.F == 0.5f || Imm.F == -0.5f ||
407      Imm.F == 1.0f || Imm.F == -1.0f ||
408      Imm.F == 2.0f || Imm.F == -2.0f ||
409      Imm.F == 4.0f || Imm.F == -4.0f)
410    return 0; // It's an inline immediate
411
412  return Imm.I; // It's a literal immediate
413}
414
415/// \brief Try to fold an immediate directly into an instruction
416bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
417                               bool &ScalarSlotUsed) const {
418
419  MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
420  if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode()))
421    return false;
422
423  const SDValue &Op = Mov->getOperand(0);
424  int32_t Value = analyzeImmediate(Op.getNode());
425  if (Value == -1) {
426    // Not an immediate at all
427    return false;
428
429  } else if (Value == 0) {
430    // Inline immediates can always be fold
431    Operand = Op;
432    return true;
433
434  } else if (Value == Immediate) {
435    // Already fold literal immediate
436    Operand = Op;
437    return true;
438
439  } else if (!ScalarSlotUsed && !Immediate) {
440    // Fold this literal immediate
441    ScalarSlotUsed = true;
442    Immediate = Value;
443    Operand = Op;
444    return true;
445
446  }
447
448  return false;
449}
450
451/// \brief Does "Op" fit into register class "RegClass" ?
452bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, SDValue &Op,
453                                    unsigned RegClass) const {
454
455  MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
456  SDNode *Node = Op.getNode();
457
458  int OpClass;
459  if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) {
460    const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
461    OpClass = Desc.OpInfo[Op.getResNo()].RegClass;
462
463  } else if (Node->getOpcode() == ISD::CopyFromReg) {
464    RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode());
465    OpClass = MRI.getRegClass(Reg->getReg())->getID();
466
467  } else
468    return false;
469
470  if (OpClass == -1)
471    return false;
472
473  return TRI->getRegClass(RegClass)->hasSubClassEq(TRI->getRegClass(OpClass));
474}
475
476/// \brief Make sure that we don't exeed the number of allowed scalars
477void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
478                                       unsigned RegClass,
479                                       bool &ScalarSlotUsed) const {
480
481  // First map the operands register class to a destination class
482  if (RegClass == AMDGPU::VSrc_32RegClassID)
483    RegClass = AMDGPU::VReg_32RegClassID;
484  else if (RegClass == AMDGPU::VSrc_64RegClassID)
485    RegClass = AMDGPU::VReg_64RegClassID;
486  else
487    return;
488
489  // Nothing todo if they fit naturaly
490  if (fitsRegClass(DAG, Operand, RegClass))
491    return;
492
493  // If the scalar slot isn't used yet use it now
494  if (!ScalarSlotUsed) {
495    ScalarSlotUsed = true;
496    return;
497  }
498
499  // This is a conservative aproach, it is possible that we can't determine
500  // the correct register class and copy too often, but better save than sorry.
501  SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
502  SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, DebugLoc(),
503                                    Operand.getValueType(), Operand, RC);
504  Operand = SDValue(Node, 0);
505}
506
507SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
508                                          SelectionDAG &DAG) const {
509
510  // Original encoding (either e32 or e64)
511  int Opcode = Node->getMachineOpcode();
512  const MCInstrDesc *Desc = &TII->get(Opcode);
513
514  unsigned NumDefs = Desc->getNumDefs();
515  unsigned NumOps = Desc->getNumOperands();
516
517  // e64 version if available, -1 otherwise
518  int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
519  const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64);
520
521  assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
522  assert(!DescE64 || DescE64->getNumOperands() == (NumOps + 4));
523
524  int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
525  bool HaveVSrc = false, HaveSSrc = false;
526
527  // First figure out what we alread have in this instruction
528  for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
529       i != e && Op < NumOps; ++i, ++Op) {
530
531    unsigned RegClass = Desc->OpInfo[Op].RegClass;
532    if (isVSrc(RegClass))
533      HaveVSrc = true;
534    else if (isSSrc(RegClass))
535      HaveSSrc = true;
536    else
537      continue;
538
539    int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
540    if (Imm != -1 && Imm != 0) {
541      // Literal immediate
542      Immediate = Imm;
543    }
544  }
545
546  // If we neither have VSrc nor SSrc it makes no sense to continue
547  if (!HaveVSrc && !HaveSSrc)
548    return Node;
549
550  // No scalar allowed when we have both VSrc and SSrc
551  bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
552
553  // Second go over the operands and try to fold them
554  std::vector<SDValue> Ops;
555  bool Promote2e64 = false;
556  for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
557       i != e && Op < NumOps; ++i, ++Op) {
558
559    const SDValue &Operand = Node->getOperand(i);
560    Ops.push_back(Operand);
561
562    // Already folded immediate ?
563    if (isa<ConstantSDNode>(Operand.getNode()) ||
564        isa<ConstantFPSDNode>(Operand.getNode()))
565      continue;
566
567    // Is this a VSrc or SSrc operand ?
568    unsigned RegClass = Desc->OpInfo[Op].RegClass;
569    if (!isVSrc(RegClass) && !isSSrc(RegClass)) {
570
571      if (i == 1 && Desc->isCommutable() &&
572          fitsRegClass(DAG, Ops[0], RegClass) &&
573          foldImm(Ops[1], Immediate, ScalarSlotUsed)) {
574
575        assert(isVSrc(Desc->OpInfo[NumDefs].RegClass) ||
576               isSSrc(Desc->OpInfo[NumDefs].RegClass));
577
578        // Swap commutable operands
579        SDValue Tmp = Ops[1];
580        Ops[1] = Ops[0];
581        Ops[0] = Tmp;
582
583      } else if (DescE64 && !Immediate) {
584        // Test if it makes sense to switch to e64 encoding
585
586        RegClass = DescE64->OpInfo[Op].RegClass;
587        int32_t TmpImm = -1;
588        if ((isVSrc(RegClass) || isSSrc(RegClass)) &&
589            foldImm(Ops[i], TmpImm, ScalarSlotUsed)) {
590
591          Immediate = -1;
592          Promote2e64 = true;
593          Desc = DescE64;
594          DescE64 = 0;
595        }
596      }
597      continue;
598    }
599
600    // Try to fold the immediates
601    if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
602      // Folding didn't worked, make sure we don't hit the SReg limit
603      ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
604    }
605  }
606
607  if (Promote2e64) {
608    // Add the modifier flags while promoting
609    for (unsigned i = 0; i < 4; ++i)
610      Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
611  }
612
613  // Add optional chain and glue
614  for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
615    Ops.push_back(Node->getOperand(i));
616
617  // Either create a complete new or update the current instruction
618  if (Promote2e64)
619    return DAG.getMachineNode(OpcodeE64, Node->getDebugLoc(),
620                              Node->getVTList(), Ops.data(), Ops.size());
621  else
622    return DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
623}
624