| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| fd76325f8afd780f3b5863a32d4a7f1bc88fec07 |
|
25-Nov-2013 |
Bill Wendling <isanbard@gmail.com> |
Merging r195514:
------------------------------------------------------------------------
r195514 | tstellar | 2013-11-22 15:07:58 -0800 (Fri, 22 Nov 2013) | 6 lines
R600/SI: Fixing handling of condition codes
We were ignoring the ordered/onordered bits and also the signed/unsigned
bits of condition codes when lowering the DAG to MachineInstrs.
NOTE: This is a candidate for the 3.4 branch.
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@195609 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e64a2896094be370f5ca3d755f62c762fb94b37a |
|
18-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
R600/SI: Implement add i64, but do not yet enable.
Test doesn't actually check the output. I need
to fix add i64 being matched for the addressing
calculations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| f38be91a829ad5a0391b6f139f0bd8cef341e689 |
|
18-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
R600/SI: addc / adde i32 are legal
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195038 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| a2b4eb6d15a13de257319ac6231b5ab622cd02b1 |
|
14-Nov-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add support for private address space load/store
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 9242b73286f050c53a26225b2a9acd14aeaa91da |
|
23-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Replace ffs(x) - 1 with countTrailingZeros(x)
ffs(x) broke the mingw buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193225 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 96b5670cf454a586bee6d364fa91398c2e085852 |
|
23-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: fix MIMG writemask adjustement
This fixes piglit:
- shaders/glsl-fs-texture2d-masked
- shaders/glsl-fs-texture2d-masked-4
Patch by: Marek Olšák
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193222 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| f95b1621887e3409ceec2db47e1b44271d934735 |
|
23-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Fix handling of vector kernel arguments
The SelectionDAGBuilder was promoting vector kernel arguments to legal
types, but this won't work for R600 and SI since kernel arguments are
stored in memory and can't be promoted. In order to handle vector
arguments correctly we need to look at the original types from the LLVM IR
function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193215 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 484091a50aa27dbf8d7483352b7f311def5d6036 |
|
16-Oct-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600/SI: Remove some leftover MI dump call
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 6a809a8d292ca4aa70cc07ce6b573239f397bb47 |
|
13-Oct-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600/SI: Support byval arguments
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 6c066c044ed5b477cdec3eb3e95267783e6ce757 |
|
11-Oct-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Fix typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192406 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 0f9eaaa8aa10bdb658e887782b86f03dbea79cb1 |
|
10-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Define a separate MIMG instruction for each possible output value type
During instruction selection, we rewrite the destination register
class for MIMG instructions based on their writemasks. This creates
machine verifier errors since the new register class does not match
the register class in the MIMG instruction definition.
We can avoid this by defining different MIMG instructions for each
possible destination type and then switching to the correct instruction
when we change the register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192365 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| a3c2bcf0ee2f63584f7a1e9df9fa153a8b5dfea1 |
|
12-Sep-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedback
For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist.
The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take
a resource descriptor might be nicer.
The maximum number of input SGPRs is bumped to 17.
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 3987e532f7e7b326083d3b5145bd29bb69e15410 |
|
05-Sep-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
R600: Fix i64 to i32 trunc on SI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| d08a9303614355cfdcac5f2c27c09ce809565423 |
|
26-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add support for vector local memory loads
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| da25cd3e6de8f21005590c2de49868f883cf2410 |
|
26-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
SelectionDAG: Use correct pointer size when lowering function arguments v2
This adds minimal support to the SelectionDAG for handling address spaces
with different pointer sizes. The SelectionDAG should now correctly
lower pointer function arguments to the correct size as well as generate
the correct code when lowering getelementptr.
This patch also updates the R600 DataLayout to use 32-bit pointers for
the local address space.
v2:
- Add more helper functions to TargetLoweringBase
- Use CHECK-LABEL for tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189221 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| d0cad1f3ed71bd98ef8017c31573abf22fac9588 |
|
16-Aug-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
R600: Allocate memoperand in the MachienFunction so it doesn't leak.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188555 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| a41520cf9b9cefed2091a0624a34c5f7fdb42a68 |
|
15-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Improve legalization of vector operations
This should fix hangs in the OpenCL piglit tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e8e33f448e8830590c498ac5101ef8b27446ca3b |
|
15-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Replace v1i32 type with i32 in imageload and sample intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 68db37b952be497c94c7aa98cf26f3baadb5afd3 |
|
15-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Convert v16i8 resource descriptors to i128
Now that compute support is better on SI, we can't continue using v16i8
for descriptors since this is also a legal type in OpenCL.
This patch fixes numerous hangs with the piglit OpenCL test and since
we now use a target specific DAG node for LOAD_CONSTANT with the
correct MemOperandFlags, this should also fix:
https://bugs.freedesktop.org/show_bug.cgi?id=66805
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| df4626ef15ba0eb5f571a3ee6314e5c388258927 |
|
15-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
The previous code declared the operand as unknown:$vaddr, which made
it possible for scalar registers to be used instead of vector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 6e4dbcd1150ea6d4fbf87a7840b3d8481bfcc8c5 |
|
10-Aug-2013 |
Niels Ole Salscheider <niels_ole@salscheider-online.de> |
R600/SI: FMA is faster than fmul and fadd for f64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 014773626d2678868adf696ac58c44d2b2980fa8 |
|
08-Aug-2013 |
Niels Ole Salscheider <niels_ole@salscheider-online.de> |
R600/SI: Implement fp32<->fp64 conversions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187988 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 3492eefa4b2509c87598678a6977074a3f6a50e6 |
|
07-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Use VSrc_* register classes as the default classes for types
Since the VSrc_* register classes contain both VGPRs and SGPRs, copies
that used be emitted by isel like this:
SGPR = COPY VGPR
Will now be emitted like this:
VSrC = COPY VGPR
This patch also adds a pass that tries to identify and fix situations where
a VGPR to SGPR copy may occur. Hopefully, these changes will make it
impossible for the compiler to generate illegal VGPR to SGPR copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 3406d882c02a6cd1e16f4636351c23dcb68d785f |
|
07-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add more special cases for opcodes to ensureSRegLimit()
Also factor out the register class lookup to its own function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187830 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 8cd70d3a5bbc5c2b02d288337748a4fd5ddc9f54 |
|
01-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Custom lower i64 ZERO_EXTEND
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187580 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| eb643b9b37cf2b15249f43aa21ed25a71e71862c |
|
23-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Improve support for < 32-bit loads
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186921 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 4e518fd941b119834b5764708fbabf41adc45040 |
|
18-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Fix crash with VSELECT
https://bugs.freedesktop.org/show_bug.cgi?id=66175
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186616 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| cd0f2458641ebebdb887da0381bd3acea6a1902f |
|
15-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add support for 64-bit loads
https://bugs.freedesktop.org/show_bug.cgi?id=65873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| d2442c10f9bfe8a9d6cdcb28030d32deb5b192b1 |
|
12-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add double precision fsub pattern for SI
Patch by: Niels Ole Salscheider
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 68e132866236f5d59271d2c7ffb77a9c8e743752 |
|
12-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add initial double precision support for SI
Patch by: Niels Ole Salscheider
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| a3e39dc7055486cbf514ccd868cfabc69d7f6f4e |
|
10-Jul-2013 |
Michel Danzer <michel.daenzer@amd.com> |
R600/SI: Initial local memory support
Enough for the radeonsi driver to use it for calculating derivatives.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186012 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| f97c7fef52098bbd6a7ccc69657d112a36d77660 |
|
25-Jun-2013 |
Aaron Watry <awatry@gmail.com> |
R600: Consolidate expansion of v2i32/v4i32 ops for EG/SI
By default, we expand these operations for both EG and SI. Move the
duplicated code into a common space for now. If the targets ever actually
implement these operations as instructions, we can override that in the relevant
target.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184848 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 1842ec4d9fc9eeceb2a77527026dfd84ee24cff1 |
|
25-Jun-2013 |
Aaron Watry <awatry@gmail.com> |
R600/SI: Expand xor v2i32/v4i32
Add test cases for both vector sizes on SI and also add v2i32 test for EG.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 41f3db569c893eb39a6413718a5152f6de3c5099 |
|
25-Jun-2013 |
Aaron Watry <awatry@gmail.com> |
R600/SI: Expand urem of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Note: I followed the guidance of the v4i32 EG check... UREM produces really
complex code, so let's just check that the instruction was lowered
successfully.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e80978f9dd6bd8951d968fd2e85ec4c0996b62f5 |
|
25-Jun-2013 |
Aaron Watry <awatry@gmail.com> |
R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EG
Also add lit test for both cases on SI, and v2i32 for evergreen.
Note: I followed the guidance of the v4i32 EG check... UDIV produces really
complex code, so let's just check that the instruction was lowered
successfully.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| c1fcf01d7fa41171fc715618d0a9359df7865aa6 |
|
25-Jun-2013 |
Aaron Watry <awatry@gmail.com> |
R600/SI: Expand ashr of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184842 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 61de9f83cb67a9738fa146e2b4542332aabee019 |
|
25-Jun-2013 |
Aaron Watry <awatry@gmail.com> |
R600/SI: Expand srl of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 60e6dacd1c21eba75599a294fe37a6072c37604f |
|
25-Jun-2013 |
Aaron Watry <awatry@gmail.com> |
R600/SI: Expand shl of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184840 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| b8ce77752b9654fa81f80d63a50a8d5c5b390c9a |
|
25-Jun-2013 |
Aaron Watry <awatry@gmail.com> |
R600/SI: Expand or of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184839 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 02ed261f7f7601f8ed5685345f3542b5120bcbf0 |
|
25-Jun-2013 |
Aaron Watry <awatry@gmail.com> |
R600/SI: Expand mul of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e3599ca1915f56ce13139fed58f6daac1cc7ca70 |
|
25-Jun-2013 |
Aaron Watry <awatry@gmail.com> |
R600/SI: Expand and of v2i32/v4i32 for SI
Also add lit test for both cases on SI, and v2i32 for evergreen.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184837 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 73e44d8ae4c227af92b8f96f447e4a7ed38f6de5 |
|
25-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Report unaligned memory accesses as legal for > 32-bit types
In reality, some unaligned memory accesses are legal for 32-bit types and
smaller too, but it all depends on the address space. Allowing
unaligned loads/stores for > 32-bit types is mainly to prevent the
legalizer from splitting one load into multiple loads of smaller types.
https://bugs.freedesktop.org/show_bug.cgi?id=65873
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184822 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 4010e438100fedeacd36ecd2385adabc02b6f236 |
|
20-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Expand sub for v2i32 and v4i32 for SI
Also add a v2i32 test to the existing v4i32 test.
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry<awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184482 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| fe91c515d788c4e07413704bcdaaa7de84e77be8 |
|
20-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Expand add for v2i32 and v4i32
Also add SI tests to existing file and a v2i32 test for both
R600 and SI.
Patch by: Aaron Watry
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 3ff0abfaabc2c7f604d490be587b9c27e7c91ac0 |
|
07-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Rework subtarget info and remove AMDILDevice classes
This should simplify the subtarget definitions and make it easier to
add new ones.
Reviewed-by: Vincent Lejeune <vljn@ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183566 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| b5632b5b456db647b42239cbd4d8b58c82290c4e |
|
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| c170230b3a8c1e0a43614a929061ad24888bfe52 |
|
06-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Replace predicate loop with predicate function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183351 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e5fcc0dee4b41658986047f346201ad98757e7d5 |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add support for work item and work group intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183138 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e7397ee81ad07cab36362bab5a086f20acc60a80 |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add a calling convention for compute shaders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183137 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e86f9d70ca29429ea83bc2361cf908dc566783af |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Custom lower i64 sign_extend
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 17e8ad67f0ba5e81e53ce21cd260fe3368d6231d |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Adjust some instructions' out register class after ISel
This is necessary to avoid generating VGPR to SGPR copies in some
cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183135 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| b89a467559d3eaade14993c7332afca3539f95d9 |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Handle REG_SEQUENCE in fitsRegClass()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 051a28e0e8a5a6f41d9360a58079af6231557152 |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Handle nodes with glue results correctly SITargetLowering::foldOperands()
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183133 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 4956bc61e1c86e781fd8abe14431c121d960d65b |
|
03-Jun-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Rework MUBUF store instructions
The lowering of stores is now mostly handled in the tablegen files. No
more BUFFER_STORE nodes I generated during legalization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| ac6d9bec671252dd1e596fa71180ff6b39d06b5d |
|
25-May-2013 |
Andrew Trick <atrick@apple.com> |
Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of
these functions to pass in SDLoc instead of DebugLoc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 5c35290fa35ae234fed02496404cb0fc37e1c8a5 |
|
23-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182594 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 879b071bf539163f90a5ef449d3e6a9ec73faa2f |
|
23-May-2013 |
Benjamin Kramer <benny.kra@googlemail.com> |
R600: Hide symbols of implementation details.
Also removes an unused function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182587 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| bbc45a3e28ed3a0b1e9becd227c361e0f8323e5b |
|
22-May-2013 |
Rafael Espindola <rafael.espindola@gmail.com> |
Attempt to fix the mingw32 bot.
This should hopefully fix
http://lab.llvm.org:8011/builders/clang-x86_64-darwin11-self-mingw32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182446 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 9bf4590aaa26ebb5afdbec079daeee8e0b268b47 |
|
20-May-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Make fitsRegClass() operands const
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182282 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 225ed7069caae9ece32d8bd3d15c6e41e21cc04b |
|
18-May-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add LLVMContext argument to getSetCCResultType
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e91967820879b79f95b0378124c5f40d9e6d54ee |
|
17-May-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: return undef instead of null for skipped arguments
This is a candidate for the stable branch.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=64694
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182084 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| ea73bd8a542f4a943a5a0d23c60777acf9471d87 |
|
07-May-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Handle arbitrary destination type in SITargetLowering::adjustWritemask
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181268 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 2a8bea7a8eba9bfa05dcc7a87e9152a0043841b2 |
|
20-Apr-2013 |
Michael Liao <michael.liao@intel.com> |
ArrayRefize getMachineNode(). No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179901 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 4d0e8a8a3e2e5b98f598acad4d57452b99d52e74 |
|
10-Apr-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: dynamical figure out the reg class of MIMG
Depending on the number of bits set in the writemask.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 84a775d8e3d5a3765e01db4b454f849ed8be99be |
|
10-Apr-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: adjust writemask to only the used components
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179165 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 17ea10cb792832c99677afa13b9b866098bc4679 |
|
06-Apr-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add support for buffer stores v2
v2:
- Use the ADDR64 bit
Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 2fc7443498aee66e0112ef65a8466fa98d46e712 |
|
06-Apr-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Avoid generating S_MOVs with 64-bit immediates v2
SITargetLowering::analyzeImmediate() was converting the 64-bit values
to 32-bit and then checking if they were an inline immediate. Some
of these conversions caused this check to succeed and produced
S_MOV instructions with 64-bit immediates, which are illegal.
v2:
- Clean up logic
Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e49230895d9c666b84beaa748259fbf1f6715122 |
|
27-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add cummuting of rev instructions
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 0c4e61ff0a712927eead06a4730f33ddd1a1ca55 |
|
26-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: improve post ISel folding
Not only fold immediates, but avoid unnecessary copies as well.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| c53270f885e8d778cfe0e741e07d7def2b66884a |
|
26-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: switch back to RegPressure scheduling
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178021 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 03cd75eedb8d26847464e4fdb815e4ca2a556676 |
|
26-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: replace WQM intrinsic
Just enable WQM when we see an LDS interpolation instruction.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178019 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| b9e8678025891a3eb5431c652df541b632902fc6 |
|
18-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: implement indirect adressing for SI
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| b87082228bb5151598addcf0eb3756cf0f906ab6 |
|
18-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add shl pattern
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| d787c047bcc5d0d81743f9d4403d5c54fe4757fe |
|
08-Mar-2013 |
Michel Danzer <michel.daenzer@amd.com> |
R600/SI: Use source scheduler
This is certainly not the last word on scheduling for this target, but
right now this allows a few apps to run / finish with radeonsi, most
notably UT2004 / Lightsmark. They fail to compile some shaders with the
default scheduler because it ends up trying to spill registers, which
we don't support yet (and which is probably a bad idea in general for
performance if it can be avoided).
NOTE: This is a candidate for the Mesa stable branch.
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176687 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| cc22640c4c8f0bc5d1e37b4ddcdf9e7c873e4383 |
|
07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: rework input interpolation v2
v2: update CMakeLists.txt as well
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 4cce3d02a071f9e30a38cb1619999c7a6365bdf7 |
|
07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: remove SI_vs_load_buffer_index
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| ff408c07282309a8a3d4daca7c7e127d2fce01ed |
|
07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: remove SGPR address space v2
v2: fix R600 regressions
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 90c64cbaa124e0e8541680efeaa56f0e6eb78d9a |
|
07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add proper formal parameter handling for SI
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176623 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| c3c169c8844db7f8934fbb3a411290dc3cdcb543 |
|
07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: remove shader type intrinsic
Just encode the type as target specific attribute.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 204a2d32ba44ff150e2201d7e0900815b4446bad |
|
07-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: switch types of SGPRs to v*i8
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176621 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 3c980d1632fa0a1cef065e558fbc96d83ebbdf40 |
|
26-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: Add promotion of e32 to e64 in operand folding
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176105 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| b37afdcf3fa41596ab1f70eef915a8ade68ccc24 |
|
26-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: swap operands if it helps folding
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176103 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| d3b5509b8099b72104bd8a0d9a998a69eb56ab2a |
|
26-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add post ISel folding for SI v2
Include immediate folding and SGPR limit handling for VOP3 instructions.
v2: remove leftover hasExtraSrcRegAllocReq
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| c018ecac2f2f475b6e1023e90d0e48fcf9bd6e1d |
|
26-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add folding helper
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176100 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 1fbb3b3ce5629b22129a47c83bc84e2d783dde57 |
|
21-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: replace SI_V_CNDLT with a pattern
It actually fixes quite a bunch of piglit tests.
This is a candidate for the mesa-stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175756 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 664a061f81228a8092895a695c8861d3025af5e8 |
|
21-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: use patterns for clamp, fabs, fneg
Instead of using custom inserters, it's simpler and
should make DAG folding easier.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 477963aff4f7fd93c3dfdb253c2983dc9f0450f9 |
|
21-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: rework VOP2_* pattern v2
Fixing asm operation names.
v2: use ZERO constant, also add asm operands
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e9ba1830df2efef3da113a740909195e839ebd36 |
|
16-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: nuke SReg_1 v3
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.
This actually fixes a piglit test on SI.
v2: use correct register class in addRegisterClass,
set special classes as not allocatable
v3: revert setting special classes as not allocateable
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e25e490793241e471036c3e2f969ce6a068e5ce1 |
|
16-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: cleanup literal handling v3
Seems to be allot simpler, and also paves the
way for further improvements.
v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
use VGPR0 in dummy EXP, avoid compiler warning, break
after encoding the first literal.
v3: correctly use V_ADD_F32_e64
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 01115b1f5032b848659669b161af1bdd9e646208 |
|
14-Feb-2013 |
Michel Danzer <michel.daenzer@amd.com> |
R600/SI: Fix int_SI_fs_interp_constant
The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition, drop the SI_INTERP_CONST pseudo instruction, pass the parameter
slot as an operand to V_INTERP_MOV_F32 instead of hardcoding it there, and
add a special operand class for the parameter slots for type checking and
pretty printing.
NOTE: This is a candidate for the Mesa stable branch.
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175193 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 311ea66db107917789c00f2ae11ec6b98eb64e59 |
|
11-Feb-2013 |
Michel Danzer <michel.daenzer@amd.com> |
R600/SI: Use V_ADD_F32 instead of V_MOV_B32 for clamp/neg/abs modifiers.
The modifiers don't seem to have any effect with V_MOV_B32, supposedly it's
meant to just move bits untouched.
Fixes 46 piglit tests with radeonsi, though unfortunately 11 of those had
just regressed because they started using the clamp modifier.
NOTE: This is a candidate for the Mesa stable branch.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174890 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 36ba9091843bd1205fe3499ba4b55bbedc6583c9 |
|
07-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add basic support for more integer vector types.
v1i32, v2i32, v8i32 and v16i32.
Only add VGPR register classes for integer vector types, to avoid attempts
copying from VGPR to SGPR registers, which is not possible.
Patch By: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 82d3d4524f2595b2dce617e963b6d67876b4f9ba |
|
18-Jan-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Proper insert S_WAITCNT instructions
Some instructions like memory reads/writes are executed
asynchronously, so we need to insert S_WAITCNT instructions
to block before accessing their results. Previously we have
just inserted S_WAITCNT instructions after each async
instruction, this patch fixes this and adds a prober
insertion pass.
Patch by: Christian König
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172846 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 935a91540b7aa8f29ea48fe2df657db0ce5b7d5d |
|
18-Jan-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Optimize and cleanup KILL on SI
We shouldn't insert KILL optimization if we don't have a
kill instruction at all.
Patch by: Christian König
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172845 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| e13a2a3fdeca6153314bb08c1b7161205d39d168 |
|
07-Jan-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
R600/SIISelLowering.cpp: Suppress a warning. [-Wunused-variable]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171728 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| 6b7d99d47321ebb478b22afd2e317fe89d2149db |
|
19-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
R600: New control flow for SI v2
This patch replaces the control flow handling with a new
pass which structurize the graph before transforming it to
machine instruction. This has a couple of different advantages
and currently fixes 20 piglit tests without a single regression.
It is now a general purpose transformation that could be not
only be used for SI/R6xx, but also for other hardware
implementations that use a form of structurized control flow.
v2: further cleanup, fixes and documentation
Patch by: Christian König
Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170591 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|
| f98f2ce29e6e2996fa58f38979143eceaa818335 |
|
11-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIISelLowering.cpp
|