SIISelLowering.cpp revision c170230b3a8c1e0a43614a929061ad24888bfe52 
1//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Custom DAG lowering for SI
12//
13//===----------------------------------------------------------------------===//
14
15#include "SIISelLowering.h"
16#include "AMDGPU.h"
17#include "AMDIL.h"
18#include "AMDILIntrinsicInfo.h"
19#include "SIInstrInfo.h"
20#include "SIMachineFunctionInfo.h"
21#include "SIRegisterInfo.h"
22#include "llvm/CodeGen/CallingConvLower.h"
23#include "llvm/CodeGen/MachineInstrBuilder.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/SelectionDAG.h"
26#include "llvm/IR/Function.h"
27
28const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
29
30using namespace llvm;
31
32SITargetLowering::SITargetLowering(TargetMachine &TM) :
33    AMDGPUTargetLowering(TM),
34    TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())),
35    TRI(TM.getRegisterInfo()) {
36
37  addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
38  addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
39
40  addRegisterClass(MVT::v16i8, &AMDGPU::SReg_128RegClass);
41  addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
42  addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
43
44  addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass);
45  addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass);
46
47  addRegisterClass(MVT::v1i32, &AMDGPU::VReg_32RegClass);
48
49  addRegisterClass(MVT::v2i32, &AMDGPU::VReg_64RegClass);
50  addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
51
52  addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass);
53  addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
54  addRegisterClass(MVT::i128, &AMDGPU::SReg_128RegClass);
55
56  addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass);
57  addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
58
59  addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
60  addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
61
62  computeRegisterProperties();
63
64  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
65  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
66  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
67  setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
68
69  setOperationAction(ISD::ADD, MVT::i64, Legal);
70  setOperationAction(ISD::ADD, MVT::i32, Legal);
71
72  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
73  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
74
75  setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
76
77  setOperationAction(ISD::SIGN_EXTEND, MVT::i64, Custom);
78
79  setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
80
81  setTargetDAGCombine(ISD::SELECT_CC);
82
83  setTargetDAGCombine(ISD::SETCC);
84
85  setSchedulingPreference(Sched::RegPressure);
86}
87
88SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT,
89                                         SDLoc DL, SDValue Chain,
90                                         unsigned Offset) const {
91  MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
92  PointerType *PtrTy = PointerType::get(VT.getTypeForEVT(*DAG.getContext()),
93                                            AMDGPUAS::CONSTANT_ADDRESS);
94  EVT ArgVT = MVT::getIntegerVT(VT.getSizeInBits());
95  SDValue BasePtr =  DAG.getCopyFromReg(Chain, DL,
96                           MRI.getLiveInVirtReg(AMDGPU::SGPR0_SGPR1), MVT::i64);
97  SDValue Ptr = DAG.getNode(ISD::ADD, DL, MVT::i64, BasePtr,
98                                             DAG.getConstant(Offset, MVT::i64));
99  return DAG.getExtLoad(ISD::ZEXTLOAD, DL, VT, Chain, Ptr,
100                            MachinePointerInfo(UndefValue::get(PtrTy)),
101                            VT, false, false, ArgVT.getSizeInBits() >> 3);
102
103}
104
105SDValue SITargetLowering::LowerFormalArguments(
106                                      SDValue Chain,
107                                      CallingConv::ID CallConv,
108                                      bool isVarArg,
109                                      const SmallVectorImpl<ISD::InputArg> &Ins,
110                                      SDLoc DL, SelectionDAG &DAG,
111                                      SmallVectorImpl<SDValue> &InVals) const {
112
113  const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
114
115  MachineFunction &MF = DAG.getMachineFunction();
116  FunctionType *FType = MF.getFunction()->getFunctionType();
117  SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
118
119  assert(CallConv == CallingConv::C);
120
121  SmallVector<ISD::InputArg, 16> Splits;
122  uint32_t Skipped = 0;
123
124  for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
125    const ISD::InputArg &Arg = Ins[i];
126
127    // First check if it's a PS input addr
128    if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg()) {
129
130      assert((PSInputNum <= 15) && "Too many PS inputs!");
131
132      if (!Arg.Used) {
133        // We can savely skip PS inputs
134        Skipped |= 1 << i;
135        ++PSInputNum;
136        continue;
137      }
138
139      Info->PSInputAddr |= 1 << PSInputNum++;
140    }
141
142    // Second split vertices into their elements
143    if (Info->ShaderType != ShaderType::COMPUTE && Arg.VT.isVector()) {
144      ISD::InputArg NewArg = Arg;
145      NewArg.Flags.setSplit();
146      NewArg.VT = Arg.VT.getVectorElementType();
147
148      // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
149      // three or five element vertex only needs three or five registers,
150      // NOT four or eigth.
151      Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
152      unsigned NumElements = ParamType->getVectorNumElements();
153
154      for (unsigned j = 0; j != NumElements; ++j) {
155        Splits.push_back(NewArg);
156        NewArg.PartOffset += NewArg.VT.getStoreSize();
157      }
158
159    } else {
160      Splits.push_back(Arg);
161    }
162  }
163
164  SmallVector<CCValAssign, 16> ArgLocs;
165  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
166                 getTargetMachine(), ArgLocs, *DAG.getContext());
167
168  // At least one interpolation mode must be enabled or else the GPU will hang.
169  if (Info->ShaderType == ShaderType::PIXEL && (Info->PSInputAddr & 0x7F) == 0) {
170    Info->PSInputAddr |= 1;
171    CCInfo.AllocateReg(AMDGPU::VGPR0);
172    CCInfo.AllocateReg(AMDGPU::VGPR1);
173  }
174
175  // The pointer to the list of arguments is stored in SGPR0, SGPR1
176  if (Info->ShaderType == ShaderType::COMPUTE) {
177    CCInfo.AllocateReg(AMDGPU::SGPR0);
178    CCInfo.AllocateReg(AMDGPU::SGPR1);
179    MF.addLiveIn(AMDGPU::SGPR0_SGPR1, &AMDGPU::SReg_64RegClass);
180  }
181
182  AnalyzeFormalArguments(CCInfo, Splits);
183
184  for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
185
186    const ISD::InputArg &Arg = Ins[i];
187    if (Skipped & (1 << i)) {
188      InVals.push_back(DAG.getUNDEF(Arg.VT));
189      continue;
190    }
191
192    CCValAssign &VA = ArgLocs[ArgIdx++];
193    EVT VT = VA.getLocVT();
194
195    if (VA.isMemLoc()) {
196      // The first 36 bytes of the input buffer contains information about
197      // thread group and global sizes.
198      SDValue Arg = LowerParameter(DAG, VT, DL, DAG.getRoot(),
199                                   36 + VA.getLocMemOffset());
200      InVals.push_back(Arg);
201      continue;
202    }
203    assert(VA.isRegLoc() && "Parameter must be in a register!");
204
205    unsigned Reg = VA.getLocReg();
206
207    if (VT == MVT::i64) {
208      // For now assume it is a pointer
209      Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
210                                     &AMDGPU::SReg_64RegClass);
211      Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
212      InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
213      continue;
214    }
215
216    const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
217
218    Reg = MF.addLiveIn(Reg, RC);
219    SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
220
221    if (Arg.VT.isVector()) {
222
223      // Build a vector from the registers
224      Type *ParamType = FType->getParamType(Arg.OrigArgIndex);
225      unsigned NumElements = ParamType->getVectorNumElements();
226
227      SmallVector<SDValue, 4> Regs;
228      Regs.push_back(Val);
229      for (unsigned j = 1; j != NumElements; ++j) {
230        Reg = ArgLocs[ArgIdx++].getLocReg();
231        Reg = MF.addLiveIn(Reg, RC);
232        Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT));
233      }
234
235      // Fill up the missing vector elements
236      NumElements = Arg.VT.getVectorNumElements() - NumElements;
237      for (unsigned j = 0; j != NumElements; ++j)
238        Regs.push_back(DAG.getUNDEF(VT));
239
240      InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT,
241                                   Regs.data(), Regs.size()));
242      continue;
243    }
244
245    InVals.push_back(Val);
246  }
247  return Chain;
248}
249
250MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
251    MachineInstr * MI, MachineBasicBlock * BB) const {
252
253  MachineBasicBlock::iterator I = *MI;
254
255  switch (MI->getOpcode()) {
256  default:
257    return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
258  case AMDGPU::BRANCH: return BB;
259  case AMDGPU::SI_ADDR64_RSRC: {
260    MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
261    unsigned SuperReg = MI->getOperand(0).getReg();
262    unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
263    unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
264    unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
265    unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
266    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo)
267            .addOperand(MI->getOperand(1));
268    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo)
269            .addImm(0);
270    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi)
271            .addImm(RSRC_DATA_FORMAT >> 32);
272    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi)
273            .addReg(SubRegHiLo)
274            .addImm(AMDGPU::sub0)
275            .addReg(SubRegHiHi)
276            .addImm(AMDGPU::sub1);
277    BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg)
278            .addReg(SubRegLo)
279            .addImm(AMDGPU::sub0_sub1)
280            .addReg(SubRegHi)
281            .addImm(AMDGPU::sub2_sub3);
282    MI->eraseFromParent();
283    break;
284  }
285  }
286  return BB;
287}
288
289EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
290  return MVT::i1;
291}
292
293MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const {
294  return MVT::i32;
295}
296
297//===----------------------------------------------------------------------===//
298// Custom DAG Lowering Operations
299//===----------------------------------------------------------------------===//
300
301SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
302  switch (Op.getOpcode()) {
303  default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
304  case ISD::BRCOND: return LowerBRCOND(Op, DAG);
305  case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
306  case ISD::SIGN_EXTEND: return LowerSIGN_EXTEND(Op, DAG);
307  case ISD::INTRINSIC_WO_CHAIN: {
308    unsigned IntrinsicID =
309                         cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
310    EVT VT = Op.getValueType();
311    SDLoc DL(Op);
312    //XXX: Hardcoded we only use two to store the pointer to the parameters.
313    unsigned NumUserSGPRs = 2;
314    switch (IntrinsicID) {
315    default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
316    case Intrinsic::r600_read_ngroups_x:
317      return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 0);
318    case Intrinsic::r600_read_ngroups_y:
319      return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 4);
320    case Intrinsic::r600_read_ngroups_z:
321      return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 8);
322    case Intrinsic::r600_read_global_size_x:
323      return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 12);
324    case Intrinsic::r600_read_global_size_y:
325      return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 16);
326    case Intrinsic::r600_read_global_size_z:
327      return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 20);
328    case Intrinsic::r600_read_local_size_x:
329      return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 24);
330    case Intrinsic::r600_read_local_size_y:
331      return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 28);
332    case Intrinsic::r600_read_local_size_z:
333      return LowerParameter(DAG, VT, DL, DAG.getEntryNode(), 32);
334    case Intrinsic::r600_read_tgid_x:
335      return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
336                     AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 0), VT);
337    case Intrinsic::r600_read_tgid_y:
338      return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
339                     AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 1), VT);
340    case Intrinsic::r600_read_tgid_z:
341      return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
342                     AMDGPU::SReg_32RegClass.getRegister(NumUserSGPRs + 2), VT);
343    case Intrinsic::r600_read_tidig_x:
344      return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
345                                  AMDGPU::VGPR0, VT);
346    case Intrinsic::r600_read_tidig_y:
347      return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
348                                  AMDGPU::VGPR1, VT);
349    case Intrinsic::r600_read_tidig_z:
350      return CreateLiveInRegister(DAG, &AMDGPU::VReg_32RegClass,
351                                  AMDGPU::VGPR2, VT);
352
353    }
354  }
355  }
356  return SDValue();
357}
358
359/// \brief Helper function for LowerBRCOND
360static SDNode *findUser(SDValue Value, unsigned Opcode) {
361
362  SDNode *Parent = Value.getNode();
363  for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
364       I != E; ++I) {
365
366    if (I.getUse().get() != Value)
367      continue;
368
369    if (I->getOpcode() == Opcode)
370      return *I;
371  }
372  return 0;
373}
374
375/// This transforms the control flow intrinsics to get the branch destination as
376/// last parameter, also switches branch target with BR if the need arise
377SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
378                                      SelectionDAG &DAG) const {
379
380  SDLoc DL(BRCOND);
381
382  SDNode *Intr = BRCOND.getOperand(1).getNode();
383  SDValue Target = BRCOND.getOperand(2);
384  SDNode *BR = 0;
385
386  if (Intr->getOpcode() == ISD::SETCC) {
387    // As long as we negate the condition everything is fine
388    SDNode *SetCC = Intr;
389    assert(SetCC->getConstantOperandVal(1) == 1);
390    assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
391           ISD::SETNE);
392    Intr = SetCC->getOperand(0).getNode();
393
394  } else {
395    // Get the target from BR if we don't negate the condition
396    BR = findUser(BRCOND, ISD::BR);
397    Target = BR->getOperand(1);
398  }
399
400  assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN);
401
402  // Build the result and
403  SmallVector<EVT, 4> Res;
404  for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i)
405    Res.push_back(Intr->getValueType(i));
406
407  // operands of the new intrinsic call
408  SmallVector<SDValue, 4> Ops;
409  Ops.push_back(BRCOND.getOperand(0));
410  for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i)
411    Ops.push_back(Intr->getOperand(i));
412  Ops.push_back(Target);
413
414  // build the new intrinsic call
415  SDNode *Result = DAG.getNode(
416    Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
417    DAG.getVTList(Res.data(), Res.size()), Ops.data(), Ops.size()).getNode();
418
419  if (BR) {
420    // Give the branch instruction our target
421    SDValue Ops[] = {
422      BR->getOperand(0),
423      BRCOND.getOperand(2)
424    };
425    DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops, 2);
426  }
427
428  SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
429
430  // Copy the intrinsic results to registers
431  for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
432    SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
433    if (!CopyToReg)
434      continue;
435
436    Chain = DAG.getCopyToReg(
437      Chain, DL,
438      CopyToReg->getOperand(1),
439      SDValue(Result, i - 1),
440      SDValue());
441
442    DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
443  }
444
445  // Remove the old intrinsic from the chain
446  DAG.ReplaceAllUsesOfValueWith(
447    SDValue(Intr, Intr->getNumValues() - 1),
448    Intr->getOperand(0));
449
450  return Chain;
451}
452
453SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
454  SDValue LHS = Op.getOperand(0);
455  SDValue RHS = Op.getOperand(1);
456  SDValue True = Op.getOperand(2);
457  SDValue False = Op.getOperand(3);
458  SDValue CC = Op.getOperand(4);
459  EVT VT = Op.getValueType();
460  SDLoc DL(Op);
461
462  // Possible Min/Max pattern
463  SDValue MinMax = LowerMinMax(Op, DAG);
464  if (MinMax.getNode()) {
465    return MinMax;
466  }
467
468  SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC);
469  return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
470}
471
472SDValue SITargetLowering::LowerSIGN_EXTEND(SDValue Op,
473                                           SelectionDAG &DAG) const {
474  EVT VT = Op.getValueType();
475  SDLoc DL(Op);
476
477  if (VT != MVT::i64) {
478    return SDValue();
479  }
480
481  SDValue Hi = DAG.getNode(ISD::SRA, DL, MVT::i32, Op.getOperand(0),
482                                                 DAG.getConstant(31, MVT::i32));
483
484  return DAG.getNode(ISD::BUILD_PAIR, DL, VT, Op.getOperand(0), Hi);
485}
486
487//===----------------------------------------------------------------------===//
488// Custom DAG optimizations
489//===----------------------------------------------------------------------===//
490
491SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
492                                            DAGCombinerInfo &DCI) const {
493  SelectionDAG &DAG = DCI.DAG;
494  SDLoc DL(N);
495  EVT VT = N->getValueType(0);
496
497  switch (N->getOpcode()) {
498    default: break;
499    case ISD::SELECT_CC: {
500      N->dump();
501      ConstantSDNode *True, *False;
502      // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc)
503      if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2)))
504          && (False = dyn_cast<ConstantSDNode>(N->getOperand(3)))
505          && True->isAllOnesValue()
506          && False->isNullValue()
507          && VT == MVT::i1) {
508        return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0),
509                           N->getOperand(1), N->getOperand(4));
510
511      }
512      break;
513    }
514    case ISD::SETCC: {
515      SDValue Arg0 = N->getOperand(0);
516      SDValue Arg1 = N->getOperand(1);
517      SDValue CC = N->getOperand(2);
518      ConstantSDNode * C = NULL;
519      ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get();
520
521      // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne)
522      if (VT == MVT::i1
523          && Arg0.getOpcode() == ISD::SIGN_EXTEND
524          && Arg0.getOperand(0).getValueType() == MVT::i1
525          && (C = dyn_cast<ConstantSDNode>(Arg1))
526          && C->isNullValue()
527          && CCOp == ISD::SETNE) {
528        return SimplifySetCC(VT, Arg0.getOperand(0),
529                             DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL);
530      }
531      break;
532    }
533  }
534  return SDValue();
535}
536
537/// \brief Test if RegClass is one of the VSrc classes
538static bool isVSrc(unsigned RegClass) {
539  return AMDGPU::VSrc_32RegClassID == RegClass ||
540         AMDGPU::VSrc_64RegClassID == RegClass;
541}
542
543/// \brief Test if RegClass is one of the SSrc classes
544static bool isSSrc(unsigned RegClass) {
545  return AMDGPU::SSrc_32RegClassID == RegClass ||
546         AMDGPU::SSrc_64RegClassID == RegClass;
547}
548
549/// \brief Analyze the possible immediate value Op
550///
551/// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
552/// and the immediate value if it's a literal immediate
553int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
554
555  union {
556    int32_t I;
557    float F;
558  } Imm;
559
560  if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
561    if (Node->getZExtValue() >> 32) {
562        return -1;
563    }
564    Imm.I = Node->getSExtValue();
565  } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N))
566    Imm.F = Node->getValueAPF().convertToFloat();
567  else
568    return -1; // It isn't an immediate
569
570  if ((Imm.I >= -16 && Imm.I <= 64) ||
571      Imm.F == 0.5f || Imm.F == -0.5f ||
572      Imm.F == 1.0f || Imm.F == -1.0f ||
573      Imm.F == 2.0f || Imm.F == -2.0f ||
574      Imm.F == 4.0f || Imm.F == -4.0f)
575    return 0; // It's an inline immediate
576
577  return Imm.I; // It's a literal immediate
578}
579
580/// \brief Try to fold an immediate directly into an instruction
581bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate,
582                               bool &ScalarSlotUsed) const {
583
584  MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand);
585  if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode()))
586    return false;
587
588  const SDValue &Op = Mov->getOperand(0);
589  int32_t Value = analyzeImmediate(Op.getNode());
590  if (Value == -1) {
591    // Not an immediate at all
592    return false;
593
594  } else if (Value == 0) {
595    // Inline immediates can always be fold
596    Operand = Op;
597    return true;
598
599  } else if (Value == Immediate) {
600    // Already fold literal immediate
601    Operand = Op;
602    return true;
603
604  } else if (!ScalarSlotUsed && !Immediate) {
605    // Fold this literal immediate
606    ScalarSlotUsed = true;
607    Immediate = Value;
608    Operand = Op;
609    return true;
610
611  }
612
613  return false;
614}
615
616/// \brief Does "Op" fit into register class "RegClass" ?
617bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op,
618                                    unsigned RegClass) const {
619
620  MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
621  SDNode *Node = Op.getNode();
622
623  const TargetRegisterClass *OpClass;
624  if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) {
625    const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode());
626    int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass;
627    if (OpClassID == -1) {
628      switch (MN->getMachineOpcode()) {
629      case AMDGPU::REG_SEQUENCE:
630        // Operand 0 is the register class id for REG_SEQUENCE instructions.
631        OpClass = TRI->getRegClass(
632                       cast<ConstantSDNode>(MN->getOperand(0))->getZExtValue());
633        break;
634      default:
635        OpClass = getRegClassFor(Op.getSimpleValueType());
636        break;
637      }
638    } else {
639      OpClass = TRI->getRegClass(OpClassID);
640    }
641
642  } else if (Node->getOpcode() == ISD::CopyFromReg) {
643    RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode());
644    OpClass = MRI.getRegClass(Reg->getReg());
645
646  } else
647    return false;
648
649  return TRI->getRegClass(RegClass)->hasSubClassEq(OpClass);
650}
651
652/// \brief Make sure that we don't exeed the number of allowed scalars
653void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand,
654                                       unsigned RegClass,
655                                       bool &ScalarSlotUsed) const {
656
657  // First map the operands register class to a destination class
658  if (RegClass == AMDGPU::VSrc_32RegClassID)
659    RegClass = AMDGPU::VReg_32RegClassID;
660  else if (RegClass == AMDGPU::VSrc_64RegClassID)
661    RegClass = AMDGPU::VReg_64RegClassID;
662  else
663    return;
664
665  // Nothing todo if they fit naturaly
666  if (fitsRegClass(DAG, Operand, RegClass))
667    return;
668
669  // If the scalar slot isn't used yet use it now
670  if (!ScalarSlotUsed) {
671    ScalarSlotUsed = true;
672    return;
673  }
674
675  // This is a conservative aproach, it is possible that we can't determine
676  // the correct register class and copy too often, but better save than sorry.
677  SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32);
678  SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(),
679                                    Operand.getValueType(), Operand, RC);
680  Operand = SDValue(Node, 0);
681}
682
683/// \returns true if \p Node's operands are different from the SDValue list
684/// \p Ops
685static bool isNodeChanged(const SDNode *Node, const std::vector<SDValue> &Ops) {
686  for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) {
687    if (Ops[i].getNode() != Node->getOperand(i).getNode()) {
688      return true;
689    }
690  }
691  return false;
692}
693
694/// \brief Try to fold the Nodes operands into the Node
695SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
696                                       SelectionDAG &DAG) const {
697
698  // Original encoding (either e32 or e64)
699  int Opcode = Node->getMachineOpcode();
700  const MCInstrDesc *Desc = &TII->get(Opcode);
701
702  unsigned NumDefs = Desc->getNumDefs();
703  unsigned NumOps = Desc->getNumOperands();
704
705  // Commuted opcode if available
706  int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1;
707  const MCInstrDesc *DescRev = OpcodeRev == -1 ? 0 : &TII->get(OpcodeRev);
708
709  assert(!DescRev || DescRev->getNumDefs() == NumDefs);
710  assert(!DescRev || DescRev->getNumOperands() == NumOps);
711
712  // e64 version if available, -1 otherwise
713  int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
714  const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64);
715
716  assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
717  assert(!DescE64 || DescE64->getNumOperands() == (NumOps + 4));
718
719  int32_t Immediate = Desc->getSize() == 4 ? 0 : -1;
720  bool HaveVSrc = false, HaveSSrc = false;
721
722  // First figure out what we alread have in this instruction
723  for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
724       i != e && Op < NumOps; ++i, ++Op) {
725
726    unsigned RegClass = Desc->OpInfo[Op].RegClass;
727    if (isVSrc(RegClass))
728      HaveVSrc = true;
729    else if (isSSrc(RegClass))
730      HaveSSrc = true;
731    else
732      continue;
733
734    int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode());
735    if (Imm != -1 && Imm != 0) {
736      // Literal immediate
737      Immediate = Imm;
738    }
739  }
740
741  // If we neither have VSrc nor SSrc it makes no sense to continue
742  if (!HaveVSrc && !HaveSSrc)
743    return Node;
744
745  // No scalar allowed when we have both VSrc and SSrc
746  bool ScalarSlotUsed = HaveVSrc && HaveSSrc;
747
748  // Second go over the operands and try to fold them
749  std::vector<SDValue> Ops;
750  bool Promote2e64 = false;
751  for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs;
752       i != e && Op < NumOps; ++i, ++Op) {
753
754    const SDValue &Operand = Node->getOperand(i);
755    Ops.push_back(Operand);
756
757    // Already folded immediate ?
758    if (isa<ConstantSDNode>(Operand.getNode()) ||
759        isa<ConstantFPSDNode>(Operand.getNode()))
760      continue;
761
762    // Is this a VSrc or SSrc operand ?
763    unsigned RegClass = Desc->OpInfo[Op].RegClass;
764    if (isVSrc(RegClass) || isSSrc(RegClass)) {
765      // Try to fold the immediates
766      if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) {
767        // Folding didn't worked, make sure we don't hit the SReg limit
768        ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed);
769      }
770      continue;
771    }
772
773    if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) {
774
775      unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass;
776      assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass));
777
778      // Test if it makes sense to swap operands
779      if (foldImm(Ops[1], Immediate, ScalarSlotUsed) ||
780          (!fitsRegClass(DAG, Ops[1], RegClass) &&
781           fitsRegClass(DAG, Ops[1], OtherRegClass))) {
782
783        // Swap commutable operands
784        SDValue Tmp = Ops[1];
785        Ops[1] = Ops[0];
786        Ops[0] = Tmp;
787
788        Desc = DescRev;
789        DescRev = 0;
790        continue;
791      }
792    }
793
794    if (DescE64 && !Immediate) {
795
796      // Test if it makes sense to switch to e64 encoding
797      unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
798      if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass))
799        continue;
800
801      int32_t TmpImm = -1;
802      if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) ||
803          (!fitsRegClass(DAG, Ops[i], RegClass) &&
804           fitsRegClass(DAG, Ops[1], OtherRegClass))) {
805
806        // Switch to e64 encoding
807        Immediate = -1;
808        Promote2e64 = true;
809        Desc = DescE64;
810        DescE64 = 0;
811      }
812    }
813  }
814
815  if (Promote2e64) {
816    // Add the modifier flags while promoting
817    for (unsigned i = 0; i < 4; ++i)
818      Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
819  }
820
821  // Add optional chain and glue
822  for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i)
823    Ops.push_back(Node->getOperand(i));
824
825  // Nodes that have a glue result are not CSE'd by getMachineNode(), so in
826  // this case a brand new node is always be created, even if the operands
827  // are the same as before.  So, manually check if anything has been changed.
828  if (Desc->Opcode == Opcode && !isNodeChanged(Node, Ops)) {
829    return Node;
830  }
831
832  // Create a complete new instruction
833  return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops);
834}
835
836/// \brief Helper function for adjustWritemask
837static unsigned SubIdx2Lane(unsigned Idx) {
838  switch (Idx) {
839  default: return 0;
840  case AMDGPU::sub0: return 0;
841  case AMDGPU::sub1: return 1;
842  case AMDGPU::sub2: return 2;
843  case AMDGPU::sub3: return 3;
844  }
845}
846
847/// \brief Adjust the writemask of MIMG instructions
848void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
849                                       SelectionDAG &DAG) const {
850  SDNode *Users[4] = { };
851  unsigned Writemask = 0, Lane = 0;
852
853  // Try to figure out the used register components
854  for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
855       I != E; ++I) {
856
857    // Abort if we can't understand the usage
858    if (!I->isMachineOpcode() ||
859        I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
860      return;
861
862    Lane = SubIdx2Lane(I->getConstantOperandVal(1));
863
864    // Abort if we have more than one user per component
865    if (Users[Lane])
866      return;
867
868    Users[Lane] = *I;
869    Writemask |= 1 << Lane;
870  }
871
872  // Abort if all components are used
873  if (Writemask == 0xf)
874    return;
875
876  // Adjust the writemask in the node
877  std::vector<SDValue> Ops;
878  Ops.push_back(DAG.getTargetConstant(Writemask, MVT::i32));
879  for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
880    Ops.push_back(Node->getOperand(i));
881  Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size());
882
883  // If we only got one lane, replace it with a copy
884  if (Writemask == (1U << Lane)) {
885    SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32);
886    SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
887                                      SDLoc(), Users[Lane]->getValueType(0),
888                                      SDValue(Node, 0), RC);
889    DAG.ReplaceAllUsesWith(Users[Lane], Copy);
890    return;
891  }
892
893  // Update the users of the node with the new indices
894  for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
895
896    SDNode *User = Users[i];
897    if (!User)
898      continue;
899
900    SDValue Op = DAG.getTargetConstant(Idx, MVT::i32);
901    DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
902
903    switch (Idx) {
904    default: break;
905    case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
906    case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
907    case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
908    }
909  }
910}
911
912/// \brief Fold the instructions after slecting them
913SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
914                                          SelectionDAG &DAG) const {
915  Node = AdjustRegClass(Node, DAG);
916
917  if (AMDGPU::isMIMG(Node->getMachineOpcode()) != -1)
918    adjustWritemask(Node, DAG);
919
920  return foldOperands(Node, DAG);
921}
922
923/// \brief Assign the register class depending on the number of
924/// bits set in the writemask
925void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI,
926                                                     SDNode *Node) const {
927  if (AMDGPU::isMIMG(MI->getOpcode()) == -1)
928    return;
929
930  unsigned VReg = MI->getOperand(0).getReg();
931  unsigned Writemask = MI->getOperand(1).getImm();
932  unsigned BitsSet = 0;
933  for (unsigned i = 0; i < 4; ++i)
934    BitsSet += Writemask & (1 << i) ? 1 : 0;
935
936  const TargetRegisterClass *RC;
937  switch (BitsSet) {
938  default: return;
939  case 1:  RC = &AMDGPU::VReg_32RegClass; break;
940  case 2:  RC = &AMDGPU::VReg_64RegClass; break;
941  case 3:  RC = &AMDGPU::VReg_96RegClass; break;
942  }
943
944  MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
945  MRI.setRegClass(VReg, RC);
946}
947
948MachineSDNode *SITargetLowering::AdjustRegClass(MachineSDNode *N,
949                                                SelectionDAG &DAG) const {
950
951  SDLoc DL(N);
952  unsigned NewOpcode = N->getMachineOpcode();
953
954  switch (N->getMachineOpcode()) {
955  default: return N;
956  case AMDGPU::REG_SEQUENCE: {
957    // MVT::i128 only use SGPRs, so i128 REG_SEQUENCEs don't need to be
958    // rewritten.
959    if (N->getValueType(0) == MVT::i128) {
960      return N;
961    }
962    const SDValue Ops[] = {
963      DAG.getTargetConstant(AMDGPU::VReg_64RegClassID, MVT::i32),
964      N->getOperand(1) , N->getOperand(2),
965      N->getOperand(3), N->getOperand(4)
966    };
967    return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::i64, Ops);
968  }
969
970  case AMDGPU::S_LOAD_DWORD_IMM:
971    NewOpcode = AMDGPU::BUFFER_LOAD_DWORD_ADDR64;
972    // Fall-through
973  case AMDGPU::S_LOAD_DWORDX2_SGPR:
974    if (NewOpcode == N->getMachineOpcode()) {
975      NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
976    }
977    // Fall-through
978  case AMDGPU::S_LOAD_DWORDX4_IMM:
979  case AMDGPU::S_LOAD_DWORDX4_SGPR: {
980    if (NewOpcode == N->getMachineOpcode()) {
981      NewOpcode = AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
982    }
983    if (fitsRegClass(DAG, N->getOperand(0), AMDGPU::SReg_64RegClassID)) {
984      return N;
985    }
986    ConstantSDNode *Offset = cast<ConstantSDNode>(N->getOperand(1));
987    SDValue Ops[] = {
988      SDValue(DAG.getMachineNode(AMDGPU::SI_ADDR64_RSRC, DL, MVT::i128,
989                                 DAG.getConstant(0, MVT::i64)), 0),
990      N->getOperand(0),
991      DAG.getConstant(Offset->getSExtValue() << 2, MVT::i32)
992    };
993    return DAG.getMachineNode(NewOpcode, DL, N->getVTList(), Ops);
994  }
995  }
996}
997
998SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
999                                               const TargetRegisterClass *RC,
1000                                               unsigned Reg, EVT VT) const {
1001  SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
1002
1003  return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
1004                            cast<RegisterSDNode>(VReg)->getReg(), VT);
1005}
1006