SIISelLowering.cpp revision b89a467559d3eaade14993c7332afca3539f95d9
1//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10/// \file 11/// \brief Custom DAG lowering for SI 12// 13//===----------------------------------------------------------------------===// 14 15#include "SIISelLowering.h" 16#include "AMDGPU.h" 17#include "AMDIL.h" 18#include "AMDILIntrinsicInfo.h" 19#include "SIInstrInfo.h" 20#include "SIMachineFunctionInfo.h" 21#include "SIRegisterInfo.h" 22#include "llvm/CodeGen/CallingConvLower.h" 23#include "llvm/CodeGen/MachineInstrBuilder.h" 24#include "llvm/CodeGen/MachineRegisterInfo.h" 25#include "llvm/CodeGen/SelectionDAG.h" 26#include "llvm/IR/Function.h" 27 28const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL; 29 30using namespace llvm; 31 32SITargetLowering::SITargetLowering(TargetMachine &TM) : 33 AMDGPUTargetLowering(TM), 34 TII(static_cast<const SIInstrInfo*>(TM.getInstrInfo())), 35 TRI(TM.getRegisterInfo()) { 36 37 addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass); 38 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass); 39 40 addRegisterClass(MVT::v16i8, &AMDGPU::SReg_128RegClass); 41 addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass); 42 addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass); 43 44 addRegisterClass(MVT::i32, &AMDGPU::VReg_32RegClass); 45 addRegisterClass(MVT::f32, &AMDGPU::VReg_32RegClass); 46 47 addRegisterClass(MVT::v1i32, &AMDGPU::VReg_32RegClass); 48 49 addRegisterClass(MVT::v2i32, &AMDGPU::VReg_64RegClass); 50 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass); 51 52 addRegisterClass(MVT::v4i32, &AMDGPU::VReg_128RegClass); 53 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass); 54 addRegisterClass(MVT::i128, &AMDGPU::SReg_128RegClass); 55 56 addRegisterClass(MVT::v8i32, &AMDGPU::VReg_256RegClass); 57 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass); 58 59 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass); 60 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass); 61 62 computeRegisterProperties(); 63 64 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand); 65 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand); 66 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand); 67 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand); 68 69 setOperationAction(ISD::ADD, MVT::i64, Legal); 70 setOperationAction(ISD::ADD, MVT::i32, Legal); 71 72 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 73 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 74 75 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 76 77 setTargetDAGCombine(ISD::SELECT_CC); 78 79 setTargetDAGCombine(ISD::SETCC); 80 81 setSchedulingPreference(Sched::RegPressure); 82} 83 84SDValue SITargetLowering::LowerFormalArguments( 85 SDValue Chain, 86 CallingConv::ID CallConv, 87 bool isVarArg, 88 const SmallVectorImpl<ISD::InputArg> &Ins, 89 SDLoc DL, SelectionDAG &DAG, 90 SmallVectorImpl<SDValue> &InVals) const { 91 92 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo(); 93 94 MachineFunction &MF = DAG.getMachineFunction(); 95 FunctionType *FType = MF.getFunction()->getFunctionType(); 96 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>(); 97 98 assert(CallConv == CallingConv::C); 99 100 SmallVector<ISD::InputArg, 16> Splits; 101 uint32_t Skipped = 0; 102 103 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) { 104 const ISD::InputArg &Arg = Ins[i]; 105 106 // First check if it's a PS input addr 107 if (Info->ShaderType == ShaderType::PIXEL && !Arg.Flags.isInReg()) { 108 109 assert((PSInputNum <= 15) && "Too many PS inputs!"); 110 111 if (!Arg.Used) { 112 // We can savely skip PS inputs 113 Skipped |= 1 << i; 114 ++PSInputNum; 115 continue; 116 } 117 118 Info->PSInputAddr |= 1 << PSInputNum++; 119 } 120 121 // Second split vertices into their elements 122 if (Arg.VT.isVector()) { 123 ISD::InputArg NewArg = Arg; 124 NewArg.Flags.setSplit(); 125 NewArg.VT = Arg.VT.getVectorElementType(); 126 127 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a 128 // three or five element vertex only needs three or five registers, 129 // NOT four or eigth. 130 Type *ParamType = FType->getParamType(Arg.OrigArgIndex); 131 unsigned NumElements = ParamType->getVectorNumElements(); 132 133 for (unsigned j = 0; j != NumElements; ++j) { 134 Splits.push_back(NewArg); 135 NewArg.PartOffset += NewArg.VT.getStoreSize(); 136 } 137 138 } else { 139 Splits.push_back(Arg); 140 } 141 } 142 143 SmallVector<CCValAssign, 16> ArgLocs; 144 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 145 getTargetMachine(), ArgLocs, *DAG.getContext()); 146 147 // At least one interpolation mode must be enabled or else the GPU will hang. 148 if (Info->ShaderType == ShaderType::PIXEL && (Info->PSInputAddr & 0x7F) == 0) { 149 Info->PSInputAddr |= 1; 150 CCInfo.AllocateReg(AMDGPU::VGPR0); 151 CCInfo.AllocateReg(AMDGPU::VGPR1); 152 } 153 154 AnalyzeFormalArguments(CCInfo, Splits); 155 156 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) { 157 158 const ISD::InputArg &Arg = Ins[i]; 159 if (Skipped & (1 << i)) { 160 InVals.push_back(DAG.getUNDEF(Arg.VT)); 161 continue; 162 } 163 164 CCValAssign &VA = ArgLocs[ArgIdx++]; 165 assert(VA.isRegLoc() && "Parameter must be in a register!"); 166 167 unsigned Reg = VA.getLocReg(); 168 MVT VT = VA.getLocVT(); 169 170 if (VT == MVT::i64) { 171 // For now assume it is a pointer 172 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0, 173 &AMDGPU::SReg_64RegClass); 174 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass); 175 InVals.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT)); 176 continue; 177 } 178 179 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT); 180 181 Reg = MF.addLiveIn(Reg, RC); 182 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT); 183 184 if (Arg.VT.isVector()) { 185 186 // Build a vector from the registers 187 Type *ParamType = FType->getParamType(Arg.OrigArgIndex); 188 unsigned NumElements = ParamType->getVectorNumElements(); 189 190 SmallVector<SDValue, 4> Regs; 191 Regs.push_back(Val); 192 for (unsigned j = 1; j != NumElements; ++j) { 193 Reg = ArgLocs[ArgIdx++].getLocReg(); 194 Reg = MF.addLiveIn(Reg, RC); 195 Regs.push_back(DAG.getCopyFromReg(Chain, DL, Reg, VT)); 196 } 197 198 // Fill up the missing vector elements 199 NumElements = Arg.VT.getVectorNumElements() - NumElements; 200 for (unsigned j = 0; j != NumElements; ++j) 201 Regs.push_back(DAG.getUNDEF(VT)); 202 203 InVals.push_back(DAG.getNode(ISD::BUILD_VECTOR, DL, Arg.VT, 204 Regs.data(), Regs.size())); 205 continue; 206 } 207 208 InVals.push_back(Val); 209 } 210 return Chain; 211} 212 213MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter( 214 MachineInstr * MI, MachineBasicBlock * BB) const { 215 216 MachineBasicBlock::iterator I = *MI; 217 218 switch (MI->getOpcode()) { 219 default: 220 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB); 221 case AMDGPU::BRANCH: return BB; 222 case AMDGPU::SI_ADDR64_RSRC: { 223 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); 224 unsigned SuperReg = MI->getOperand(0).getReg(); 225 unsigned SubRegLo = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); 226 unsigned SubRegHi = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass); 227 unsigned SubRegHiHi = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); 228 unsigned SubRegHiLo = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); 229 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B64), SubRegLo) 230 .addOperand(MI->getOperand(1)); 231 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiLo) 232 .addImm(0); 233 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::S_MOV_B32), SubRegHiHi) 234 .addImm(RSRC_DATA_FORMAT >> 32); 235 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SubRegHi) 236 .addReg(SubRegHiLo) 237 .addImm(AMDGPU::sub0) 238 .addReg(SubRegHiHi) 239 .addImm(AMDGPU::sub1); 240 BuildMI(*BB, I, MI->getDebugLoc(), TII->get(AMDGPU::REG_SEQUENCE), SuperReg) 241 .addReg(SubRegLo) 242 .addImm(AMDGPU::sub0_sub1) 243 .addReg(SubRegHi) 244 .addImm(AMDGPU::sub2_sub3); 245 MI->eraseFromParent(); 246 break; 247 } 248 } 249 return BB; 250} 251 252EVT SITargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 253 return MVT::i1; 254} 255 256MVT SITargetLowering::getScalarShiftAmountTy(EVT VT) const { 257 return MVT::i32; 258} 259 260//===----------------------------------------------------------------------===// 261// Custom DAG Lowering Operations 262//===----------------------------------------------------------------------===// 263 264SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 265 switch (Op.getOpcode()) { 266 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); 267 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 268 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 269 } 270 return SDValue(); 271} 272 273/// \brief Helper function for LowerBRCOND 274static SDNode *findUser(SDValue Value, unsigned Opcode) { 275 276 SDNode *Parent = Value.getNode(); 277 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end(); 278 I != E; ++I) { 279 280 if (I.getUse().get() != Value) 281 continue; 282 283 if (I->getOpcode() == Opcode) 284 return *I; 285 } 286 return 0; 287} 288 289/// This transforms the control flow intrinsics to get the branch destination as 290/// last parameter, also switches branch target with BR if the need arise 291SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND, 292 SelectionDAG &DAG) const { 293 294 SDLoc DL(BRCOND); 295 296 SDNode *Intr = BRCOND.getOperand(1).getNode(); 297 SDValue Target = BRCOND.getOperand(2); 298 SDNode *BR = 0; 299 300 if (Intr->getOpcode() == ISD::SETCC) { 301 // As long as we negate the condition everything is fine 302 SDNode *SetCC = Intr; 303 assert(SetCC->getConstantOperandVal(1) == 1); 304 assert(cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() == 305 ISD::SETNE); 306 Intr = SetCC->getOperand(0).getNode(); 307 308 } else { 309 // Get the target from BR if we don't negate the condition 310 BR = findUser(BRCOND, ISD::BR); 311 Target = BR->getOperand(1); 312 } 313 314 assert(Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN); 315 316 // Build the result and 317 SmallVector<EVT, 4> Res; 318 for (unsigned i = 1, e = Intr->getNumValues(); i != e; ++i) 319 Res.push_back(Intr->getValueType(i)); 320 321 // operands of the new intrinsic call 322 SmallVector<SDValue, 4> Ops; 323 Ops.push_back(BRCOND.getOperand(0)); 324 for (unsigned i = 1, e = Intr->getNumOperands(); i != e; ++i) 325 Ops.push_back(Intr->getOperand(i)); 326 Ops.push_back(Target); 327 328 // build the new intrinsic call 329 SDNode *Result = DAG.getNode( 330 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL, 331 DAG.getVTList(Res.data(), Res.size()), Ops.data(), Ops.size()).getNode(); 332 333 if (BR) { 334 // Give the branch instruction our target 335 SDValue Ops[] = { 336 BR->getOperand(0), 337 BRCOND.getOperand(2) 338 }; 339 DAG.MorphNodeTo(BR, ISD::BR, BR->getVTList(), Ops, 2); 340 } 341 342 SDValue Chain = SDValue(Result, Result->getNumValues() - 1); 343 344 // Copy the intrinsic results to registers 345 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) { 346 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg); 347 if (!CopyToReg) 348 continue; 349 350 Chain = DAG.getCopyToReg( 351 Chain, DL, 352 CopyToReg->getOperand(1), 353 SDValue(Result, i - 1), 354 SDValue()); 355 356 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0)); 357 } 358 359 // Remove the old intrinsic from the chain 360 DAG.ReplaceAllUsesOfValueWith( 361 SDValue(Intr, Intr->getNumValues() - 1), 362 Intr->getOperand(0)); 363 364 return Chain; 365} 366 367SDValue SITargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const { 368 SDValue LHS = Op.getOperand(0); 369 SDValue RHS = Op.getOperand(1); 370 SDValue True = Op.getOperand(2); 371 SDValue False = Op.getOperand(3); 372 SDValue CC = Op.getOperand(4); 373 EVT VT = Op.getValueType(); 374 SDLoc DL(Op); 375 376 // Possible Min/Max pattern 377 SDValue MinMax = LowerMinMax(Op, DAG); 378 if (MinMax.getNode()) { 379 return MinMax; 380 } 381 382 SDValue Cond = DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, CC); 383 return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False); 384} 385 386//===----------------------------------------------------------------------===// 387// Custom DAG optimizations 388//===----------------------------------------------------------------------===// 389 390SDValue SITargetLowering::PerformDAGCombine(SDNode *N, 391 DAGCombinerInfo &DCI) const { 392 SelectionDAG &DAG = DCI.DAG; 393 SDLoc DL(N); 394 EVT VT = N->getValueType(0); 395 396 switch (N->getOpcode()) { 397 default: break; 398 case ISD::SELECT_CC: { 399 N->dump(); 400 ConstantSDNode *True, *False; 401 // i1 selectcc(l, r, -1, 0, cc) -> i1 setcc(l, r, cc) 402 if ((True = dyn_cast<ConstantSDNode>(N->getOperand(2))) 403 && (False = dyn_cast<ConstantSDNode>(N->getOperand(3))) 404 && True->isAllOnesValue() 405 && False->isNullValue() 406 && VT == MVT::i1) { 407 return DAG.getNode(ISD::SETCC, DL, VT, N->getOperand(0), 408 N->getOperand(1), N->getOperand(4)); 409 410 } 411 break; 412 } 413 case ISD::SETCC: { 414 SDValue Arg0 = N->getOperand(0); 415 SDValue Arg1 = N->getOperand(1); 416 SDValue CC = N->getOperand(2); 417 ConstantSDNode * C = NULL; 418 ISD::CondCode CCOp = dyn_cast<CondCodeSDNode>(CC)->get(); 419 420 // i1 setcc (sext(i1), 0, setne) -> i1 setcc(i1, 0, setne) 421 if (VT == MVT::i1 422 && Arg0.getOpcode() == ISD::SIGN_EXTEND 423 && Arg0.getOperand(0).getValueType() == MVT::i1 424 && (C = dyn_cast<ConstantSDNode>(Arg1)) 425 && C->isNullValue() 426 && CCOp == ISD::SETNE) { 427 return SimplifySetCC(VT, Arg0.getOperand(0), 428 DAG.getConstant(0, MVT::i1), CCOp, true, DCI, DL); 429 } 430 break; 431 } 432 } 433 return SDValue(); 434} 435 436/// \brief Test if RegClass is one of the VSrc classes 437static bool isVSrc(unsigned RegClass) { 438 return AMDGPU::VSrc_32RegClassID == RegClass || 439 AMDGPU::VSrc_64RegClassID == RegClass; 440} 441 442/// \brief Test if RegClass is one of the SSrc classes 443static bool isSSrc(unsigned RegClass) { 444 return AMDGPU::SSrc_32RegClassID == RegClass || 445 AMDGPU::SSrc_64RegClassID == RegClass; 446} 447 448/// \brief Analyze the possible immediate value Op 449/// 450/// Returns -1 if it isn't an immediate, 0 if it's and inline immediate 451/// and the immediate value if it's a literal immediate 452int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const { 453 454 union { 455 int32_t I; 456 float F; 457 } Imm; 458 459 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) { 460 if (Node->getZExtValue() >> 32) { 461 return -1; 462 } 463 Imm.I = Node->getSExtValue(); 464 } else if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) 465 Imm.F = Node->getValueAPF().convertToFloat(); 466 else 467 return -1; // It isn't an immediate 468 469 if ((Imm.I >= -16 && Imm.I <= 64) || 470 Imm.F == 0.5f || Imm.F == -0.5f || 471 Imm.F == 1.0f || Imm.F == -1.0f || 472 Imm.F == 2.0f || Imm.F == -2.0f || 473 Imm.F == 4.0f || Imm.F == -4.0f) 474 return 0; // It's an inline immediate 475 476 return Imm.I; // It's a literal immediate 477} 478 479/// \brief Try to fold an immediate directly into an instruction 480bool SITargetLowering::foldImm(SDValue &Operand, int32_t &Immediate, 481 bool &ScalarSlotUsed) const { 482 483 MachineSDNode *Mov = dyn_cast<MachineSDNode>(Operand); 484 if (Mov == 0 || !TII->isMov(Mov->getMachineOpcode())) 485 return false; 486 487 const SDValue &Op = Mov->getOperand(0); 488 int32_t Value = analyzeImmediate(Op.getNode()); 489 if (Value == -1) { 490 // Not an immediate at all 491 return false; 492 493 } else if (Value == 0) { 494 // Inline immediates can always be fold 495 Operand = Op; 496 return true; 497 498 } else if (Value == Immediate) { 499 // Already fold literal immediate 500 Operand = Op; 501 return true; 502 503 } else if (!ScalarSlotUsed && !Immediate) { 504 // Fold this literal immediate 505 ScalarSlotUsed = true; 506 Immediate = Value; 507 Operand = Op; 508 return true; 509 510 } 511 512 return false; 513} 514 515/// \brief Does "Op" fit into register class "RegClass" ? 516bool SITargetLowering::fitsRegClass(SelectionDAG &DAG, const SDValue &Op, 517 unsigned RegClass) const { 518 519 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 520 SDNode *Node = Op.getNode(); 521 522 const TargetRegisterClass *OpClass; 523 if (MachineSDNode *MN = dyn_cast<MachineSDNode>(Node)) { 524 const MCInstrDesc &Desc = TII->get(MN->getMachineOpcode()); 525 int OpClassID = Desc.OpInfo[Op.getResNo()].RegClass; 526 if (OpClassID == -1) { 527 switch (MN->getMachineOpcode()) { 528 case AMDGPU::REG_SEQUENCE: 529 // Operand 0 is the register class id for REG_SEQUENCE instructions. 530 OpClass = TRI->getRegClass( 531 cast<ConstantSDNode>(MN->getOperand(0))->getZExtValue()); 532 break; 533 default: 534 OpClass = getRegClassFor(Op.getSimpleValueType()); 535 break; 536 } 537 } else { 538 OpClass = TRI->getRegClass(OpClassID); 539 } 540 541 } else if (Node->getOpcode() == ISD::CopyFromReg) { 542 RegisterSDNode *Reg = cast<RegisterSDNode>(Node->getOperand(1).getNode()); 543 OpClass = MRI.getRegClass(Reg->getReg()); 544 545 } else 546 return false; 547 548 return TRI->getRegClass(RegClass)->hasSubClassEq(OpClass); 549} 550 551/// \brief Make sure that we don't exeed the number of allowed scalars 552void SITargetLowering::ensureSRegLimit(SelectionDAG &DAG, SDValue &Operand, 553 unsigned RegClass, 554 bool &ScalarSlotUsed) const { 555 556 // First map the operands register class to a destination class 557 if (RegClass == AMDGPU::VSrc_32RegClassID) 558 RegClass = AMDGPU::VReg_32RegClassID; 559 else if (RegClass == AMDGPU::VSrc_64RegClassID) 560 RegClass = AMDGPU::VReg_64RegClassID; 561 else 562 return; 563 564 // Nothing todo if they fit naturaly 565 if (fitsRegClass(DAG, Operand, RegClass)) 566 return; 567 568 // If the scalar slot isn't used yet use it now 569 if (!ScalarSlotUsed) { 570 ScalarSlotUsed = true; 571 return; 572 } 573 574 // This is a conservative aproach, it is possible that we can't determine 575 // the correct register class and copy too often, but better save than sorry. 576 SDValue RC = DAG.getTargetConstant(RegClass, MVT::i32); 577 SDNode *Node = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, SDLoc(), 578 Operand.getValueType(), Operand, RC); 579 Operand = SDValue(Node, 0); 580} 581 582/// \brief Try to fold the Nodes operands into the Node 583SDNode *SITargetLowering::foldOperands(MachineSDNode *Node, 584 SelectionDAG &DAG) const { 585 586 // Original encoding (either e32 or e64) 587 int Opcode = Node->getMachineOpcode(); 588 const MCInstrDesc *Desc = &TII->get(Opcode); 589 590 unsigned NumDefs = Desc->getNumDefs(); 591 unsigned NumOps = Desc->getNumOperands(); 592 593 // Commuted opcode if available 594 int OpcodeRev = Desc->isCommutable() ? TII->commuteOpcode(Opcode) : -1; 595 const MCInstrDesc *DescRev = OpcodeRev == -1 ? 0 : &TII->get(OpcodeRev); 596 597 assert(!DescRev || DescRev->getNumDefs() == NumDefs); 598 assert(!DescRev || DescRev->getNumOperands() == NumOps); 599 600 // e64 version if available, -1 otherwise 601 int OpcodeE64 = AMDGPU::getVOPe64(Opcode); 602 const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? 0 : &TII->get(OpcodeE64); 603 604 assert(!DescE64 || DescE64->getNumDefs() == NumDefs); 605 assert(!DescE64 || DescE64->getNumOperands() == (NumOps + 4)); 606 607 int32_t Immediate = Desc->getSize() == 4 ? 0 : -1; 608 bool HaveVSrc = false, HaveSSrc = false; 609 610 // First figure out what we alread have in this instruction 611 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs; 612 i != e && Op < NumOps; ++i, ++Op) { 613 614 unsigned RegClass = Desc->OpInfo[Op].RegClass; 615 if (isVSrc(RegClass)) 616 HaveVSrc = true; 617 else if (isSSrc(RegClass)) 618 HaveSSrc = true; 619 else 620 continue; 621 622 int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode()); 623 if (Imm != -1 && Imm != 0) { 624 // Literal immediate 625 Immediate = Imm; 626 } 627 } 628 629 // If we neither have VSrc nor SSrc it makes no sense to continue 630 if (!HaveVSrc && !HaveSSrc) 631 return Node; 632 633 // No scalar allowed when we have both VSrc and SSrc 634 bool ScalarSlotUsed = HaveVSrc && HaveSSrc; 635 636 // Second go over the operands and try to fold them 637 std::vector<SDValue> Ops; 638 bool Promote2e64 = false; 639 for (unsigned i = 0, e = Node->getNumOperands(), Op = NumDefs; 640 i != e && Op < NumOps; ++i, ++Op) { 641 642 const SDValue &Operand = Node->getOperand(i); 643 Ops.push_back(Operand); 644 645 // Already folded immediate ? 646 if (isa<ConstantSDNode>(Operand.getNode()) || 647 isa<ConstantFPSDNode>(Operand.getNode())) 648 continue; 649 650 // Is this a VSrc or SSrc operand ? 651 unsigned RegClass = Desc->OpInfo[Op].RegClass; 652 if (isVSrc(RegClass) || isSSrc(RegClass)) { 653 // Try to fold the immediates 654 if (!foldImm(Ops[i], Immediate, ScalarSlotUsed)) { 655 // Folding didn't worked, make sure we don't hit the SReg limit 656 ensureSRegLimit(DAG, Ops[i], RegClass, ScalarSlotUsed); 657 } 658 continue; 659 } 660 661 if (i == 1 && DescRev && fitsRegClass(DAG, Ops[0], RegClass)) { 662 663 unsigned OtherRegClass = Desc->OpInfo[NumDefs].RegClass; 664 assert(isVSrc(OtherRegClass) || isSSrc(OtherRegClass)); 665 666 // Test if it makes sense to swap operands 667 if (foldImm(Ops[1], Immediate, ScalarSlotUsed) || 668 (!fitsRegClass(DAG, Ops[1], RegClass) && 669 fitsRegClass(DAG, Ops[1], OtherRegClass))) { 670 671 // Swap commutable operands 672 SDValue Tmp = Ops[1]; 673 Ops[1] = Ops[0]; 674 Ops[0] = Tmp; 675 676 Desc = DescRev; 677 DescRev = 0; 678 continue; 679 } 680 } 681 682 if (DescE64 && !Immediate) { 683 684 // Test if it makes sense to switch to e64 encoding 685 unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass; 686 if (!isVSrc(OtherRegClass) && !isSSrc(OtherRegClass)) 687 continue; 688 689 int32_t TmpImm = -1; 690 if (foldImm(Ops[i], TmpImm, ScalarSlotUsed) || 691 (!fitsRegClass(DAG, Ops[i], RegClass) && 692 fitsRegClass(DAG, Ops[1], OtherRegClass))) { 693 694 // Switch to e64 encoding 695 Immediate = -1; 696 Promote2e64 = true; 697 Desc = DescE64; 698 DescE64 = 0; 699 } 700 } 701 } 702 703 if (Promote2e64) { 704 // Add the modifier flags while promoting 705 for (unsigned i = 0; i < 4; ++i) 706 Ops.push_back(DAG.getTargetConstant(0, MVT::i32)); 707 } 708 709 // Add optional chain and glue 710 for (unsigned i = NumOps - NumDefs, e = Node->getNumOperands(); i < e; ++i) 711 Ops.push_back(Node->getOperand(i)); 712 713 // Nodes that have a glue result are not CSE'd by getMachineNode(), so in 714 // this case a brand new node is always be created, even if the operands 715 // are the same as before. So, manually check if anything has been changed. 716 if (Desc->Opcode == Opcode) { 717 bool Changed = false; 718 for (unsigned i = 0, e = Node->getNumOperands(); i < e; ++i) { 719 if (Ops[i].getNode() != Node->getOperand(i).getNode()) { 720 Changed = true; 721 break; 722 } 723 } 724 if (!Changed) { 725 return Node; 726 } 727 } 728 729 // Create a complete new instruction 730 return DAG.getMachineNode(Desc->Opcode, SDLoc(Node), Node->getVTList(), Ops); 731} 732 733/// \brief Helper function for adjustWritemask 734static unsigned SubIdx2Lane(unsigned Idx) { 735 switch (Idx) { 736 default: return 0; 737 case AMDGPU::sub0: return 0; 738 case AMDGPU::sub1: return 1; 739 case AMDGPU::sub2: return 2; 740 case AMDGPU::sub3: return 3; 741 } 742} 743 744/// \brief Adjust the writemask of MIMG instructions 745void SITargetLowering::adjustWritemask(MachineSDNode *&Node, 746 SelectionDAG &DAG) const { 747 SDNode *Users[4] = { }; 748 unsigned Writemask = 0, Lane = 0; 749 750 // Try to figure out the used register components 751 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end(); 752 I != E; ++I) { 753 754 // Abort if we can't understand the usage 755 if (!I->isMachineOpcode() || 756 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG) 757 return; 758 759 Lane = SubIdx2Lane(I->getConstantOperandVal(1)); 760 761 // Abort if we have more than one user per component 762 if (Users[Lane]) 763 return; 764 765 Users[Lane] = *I; 766 Writemask |= 1 << Lane; 767 } 768 769 // Abort if all components are used 770 if (Writemask == 0xf) 771 return; 772 773 // Adjust the writemask in the node 774 std::vector<SDValue> Ops; 775 Ops.push_back(DAG.getTargetConstant(Writemask, MVT::i32)); 776 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) 777 Ops.push_back(Node->getOperand(i)); 778 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops.data(), Ops.size()); 779 780 // If we only got one lane, replace it with a copy 781 if (Writemask == (1U << Lane)) { 782 SDValue RC = DAG.getTargetConstant(AMDGPU::VReg_32RegClassID, MVT::i32); 783 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS, 784 SDLoc(), Users[Lane]->getValueType(0), 785 SDValue(Node, 0), RC); 786 DAG.ReplaceAllUsesWith(Users[Lane], Copy); 787 return; 788 } 789 790 // Update the users of the node with the new indices 791 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) { 792 793 SDNode *User = Users[i]; 794 if (!User) 795 continue; 796 797 SDValue Op = DAG.getTargetConstant(Idx, MVT::i32); 798 DAG.UpdateNodeOperands(User, User->getOperand(0), Op); 799 800 switch (Idx) { 801 default: break; 802 case AMDGPU::sub0: Idx = AMDGPU::sub1; break; 803 case AMDGPU::sub1: Idx = AMDGPU::sub2; break; 804 case AMDGPU::sub2: Idx = AMDGPU::sub3; break; 805 } 806 } 807} 808 809/// \brief Fold the instructions after slecting them 810SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node, 811 SelectionDAG &DAG) const { 812 813 if (AMDGPU::isMIMG(Node->getMachineOpcode()) != -1) 814 adjustWritemask(Node, DAG); 815 816 return foldOperands(Node, DAG); 817} 818 819/// \brief Assign the register class depending on the number of 820/// bits set in the writemask 821void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 822 SDNode *Node) const { 823 if (AMDGPU::isMIMG(MI->getOpcode()) == -1) 824 return; 825 826 unsigned VReg = MI->getOperand(0).getReg(); 827 unsigned Writemask = MI->getOperand(1).getImm(); 828 unsigned BitsSet = 0; 829 for (unsigned i = 0; i < 4; ++i) 830 BitsSet += Writemask & (1 << i) ? 1 : 0; 831 832 const TargetRegisterClass *RC; 833 switch (BitsSet) { 834 default: return; 835 case 1: RC = &AMDGPU::VReg_32RegClass; break; 836 case 2: RC = &AMDGPU::VReg_64RegClass; break; 837 case 3: RC = &AMDGPU::VReg_96RegClass; break; 838 } 839 840 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 841 MRI.setRegClass(VReg, RC); 842} 843