SparcInstPrinter.cpp revision cd81d94322a39503e4a3e87b6ee03d4fcb3465fb 
1//===-- SparcInstPrinter.cpp - Convert Sparc MCInst to assembly syntax -----==//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an Sparc MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcInstPrinter.h"
15#include "Sparc.h"
16#include "llvm/MC/MCExpr.h"
17#include "llvm/MC/MCInst.h"
18#include "llvm/MC/MCRegisterInfo.h"
19#include "llvm/MC/MCSymbol.h"
20#include "llvm/Support/raw_ostream.h"
21using namespace llvm;
22
23#define DEBUG_TYPE "asm-printer"
24
25// The generated AsmMatcher SparcGenAsmWriter uses "Sparc" as the target
26// namespace. But SPARC backend uses "SP" as its namespace.
27namespace llvm {
28namespace Sparc {
29  using namespace SP;
30}
31}
32
33#define GET_INSTRUCTION_NAME
34#define PRINT_ALIAS_INSTR
35#include "SparcGenAsmWriter.inc"
36
37bool SparcInstPrinter::isV9() const {
38  return (STI.getFeatureBits() & Sparc::FeatureV9) != 0;
39}
40
41void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
42{
43  OS << '%' << StringRef(getRegisterName(RegNo)).lower();
44}
45
46void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
47                               StringRef Annot)
48{
49  if (!printAliasInstr(MI, O) && !printSparcAliasInstr(MI, O))
50    printInstruction(MI, O);
51  printAnnotation(O, Annot);
52}
53
54bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O)
55{
56  switch (MI->getOpcode()) {
57  default: return false;
58  case SP::JMPLrr:
59  case SP::JMPLri: {
60    if (MI->getNumOperands() != 3)
61      return false;
62    if (!MI->getOperand(0).isReg())
63      return false;
64    switch (MI->getOperand(0).getReg()) {
65    default: return false;
66    case SP::G0: // jmp $addr | ret | retl
67      if (MI->getOperand(2).isImm() &&
68          MI->getOperand(2).getImm() == 8) {
69        switch(MI->getOperand(1).getReg()) {
70        default: break;
71        case SP::I7: O << "\tret"; return true;
72        case SP::O7: O << "\tretl"; return true;
73        }
74      }
75      O << "\tjmp "; printMemOperand(MI, 1, O);
76      return true;
77    case SP::O7: // call $addr
78      O << "\tcall "; printMemOperand(MI, 1, O);
79      return true;
80    }
81  }
82  case SP::V9FCMPS:  case SP::V9FCMPD:  case SP::V9FCMPQ:
83  case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: {
84    if (isV9()
85        || (MI->getNumOperands() != 3)
86        || (!MI->getOperand(0).isReg())
87        || (MI->getOperand(0).getReg() != SP::FCC0))
88      return false;
89    // if V8, skip printing %fcc0.
90    switch(MI->getOpcode()) {
91    default:
92    case SP::V9FCMPS:  O << "\tfcmps "; break;
93    case SP::V9FCMPD:  O << "\tfcmpd "; break;
94    case SP::V9FCMPQ:  O << "\tfcmpq "; break;
95    case SP::V9FCMPES: O << "\tfcmpes "; break;
96    case SP::V9FCMPED: O << "\tfcmped "; break;
97    case SP::V9FCMPEQ: O << "\tfcmpeq "; break;
98    }
99    printOperand(MI, 1, O);
100    O << ", ";
101    printOperand(MI, 2, O);
102    return true;
103  }
104  }
105}
106
107void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
108                                    raw_ostream &O)
109{
110  const MCOperand &MO = MI->getOperand (opNum);
111
112  if (MO.isReg()) {
113    printRegName(O, MO.getReg());
114    return ;
115  }
116
117  if (MO.isImm()) {
118    O << (int)MO.getImm();
119    return;
120  }
121
122  assert(MO.isExpr() && "Unknown operand kind in printOperand");
123  MO.getExpr()->print(O);
124}
125
126void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
127                                      raw_ostream &O, const char *Modifier)
128{
129  printOperand(MI, opNum, O);
130
131  // If this is an ADD operand, emit it like normal operands.
132  if (Modifier && !strcmp(Modifier, "arith")) {
133    O << ", ";
134    printOperand(MI, opNum+1, O);
135    return;
136  }
137  const MCOperand &MO = MI->getOperand(opNum+1);
138
139  if (MO.isReg() && MO.getReg() == SP::G0)
140    return;   // don't print "+%g0"
141  if (MO.isImm() && MO.getImm() == 0)
142    return;   // don't print "+0"
143
144  O << "+";
145
146  printOperand(MI, opNum+1, O);
147}
148
149void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
150                                     raw_ostream &O)
151{
152  int CC = (int)MI->getOperand(opNum).getImm();
153  switch (MI->getOpcode()) {
154  default: break;
155  case SP::FBCOND:
156  case SP::FBCONDA:
157  case SP::BPFCC:
158  case SP::BPFCCA:
159  case SP::BPFCCNT:
160  case SP::BPFCCANT:
161  case SP::MOVFCCrr:  case SP::V9MOVFCCrr:
162  case SP::MOVFCCri:  case SP::V9MOVFCCri:
163  case SP::FMOVS_FCC: case SP::V9FMOVS_FCC:
164  case SP::FMOVD_FCC: case SP::V9FMOVD_FCC:
165  case SP::FMOVQ_FCC: case SP::V9FMOVQ_FCC:
166    // Make sure CC is a fp conditional flag.
167    CC = (CC < 16) ? (CC + 16) : CC;
168    break;
169  }
170  O << SPARCCondCodeToString((SPCC::CondCodes)CC);
171}
172
173bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
174                                  raw_ostream &O)
175{
176  llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX.");
177  return true;
178}
179