SparcMCTargetDesc.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
169e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal//===-- SparcMCTargetDesc.cpp - Sparc Target Descriptions -----------------===// 269e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal// 369e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal// The LLVM Compiler Infrastructure 469e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal// 569e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal// This file is distributed under the University of Illinois Open Source 669e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal// License. See LICENSE.TXT for details. 769e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal// 869e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal//===----------------------------------------------------------------------===// 969e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal// 1069e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal// This file provides Sparc specific target descriptions. 1169e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal// 1269e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal//===----------------------------------------------------------------------===// 1369e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal 1469e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "SparcMCTargetDesc.h" 1569e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "InstPrinter/SparcInstPrinter.h" 1669e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "SparcMCAsmInfo.h" 1769e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "SparcTargetStreamer.h" 1869e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "llvm/MC/MCCodeGenInfo.h" 1969e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "llvm/MC/MCInstrInfo.h" 2069e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "llvm/MC/MCRegisterInfo.h" 2169e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "llvm/MC/MCSubtargetInfo.h" 2269e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "llvm/Support/ErrorHandling.h" 2369e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "llvm/Support/TargetRegistry.h" 2469e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal 2569e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#define GET_INSTRINFO_MC_DESC 2669e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "SparcGenInstrInfo.inc" 2769e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal 2869e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#define GET_SUBTARGETINFO_MC_DESC 2969e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "SparcGenSubtargetInfo.inc" 3069e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal 3169e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#define GET_REGINFO_MC_DESC 3269e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal#include "SparcGenRegisterInfo.inc" 3369e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal 3469e17611504376e4d4603925f8528dfc890fd2c6Luis Sigalusing namespace llvm; 3569e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal 3669e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal 3769e17611504376e4d4603925f8528dfc890fd2c6Luis Sigalstatic MCAsmInfo *createSparcMCAsmInfo(const MCRegisterInfo &MRI, 3869e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal StringRef TT) { 3969e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); 4069e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); 4169e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 0); 4269e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal MAI->addInitialFrameState(Inst); 4369e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal return MAI; 4469e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal} 4569e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal 4669e17611504376e4d4603925f8528dfc890fd2c6Luis Sigalstatic MCAsmInfo *createSparcV9MCAsmInfo(const MCRegisterInfo &MRI, 4769e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal StringRef TT) { 4869e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal MCAsmInfo *MAI = new SparcELFMCAsmInfo(TT); 4969e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal unsigned Reg = MRI.getDwarfRegNum(SP::O6, true); 5069e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal MCCFIInstruction Inst = MCCFIInstruction::createDefCfa(0, Reg, 2047); 5169e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal MAI->addInitialFrameState(Inst); 5269e17611504376e4d4603925f8528dfc890fd2c6Luis Sigal return MAI; 53} 54 55static MCInstrInfo *createSparcMCInstrInfo() { 56 MCInstrInfo *X = new MCInstrInfo(); 57 InitSparcMCInstrInfo(X); 58 return X; 59} 60 61static MCRegisterInfo *createSparcMCRegisterInfo(StringRef TT) { 62 MCRegisterInfo *X = new MCRegisterInfo(); 63 InitSparcMCRegisterInfo(X, SP::O7); 64 return X; 65} 66 67static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, 68 StringRef FS) { 69 MCSubtargetInfo *X = new MCSubtargetInfo(); 70 Triple TheTriple(TT); 71 if (CPU.empty()) 72 CPU = (TheTriple.getArch() == Triple::sparcv9) ? "v9" : "v8"; 73 InitSparcMCSubtargetInfo(X, TT, CPU, FS); 74 return X; 75} 76 77// Code models. Some only make sense for 64-bit code. 78// 79// SunCC Reloc CodeModel Constraints 80// abs32 Static Small text+data+bss linked below 2^32 bytes 81// abs44 Static Medium text+data+bss linked below 2^44 bytes 82// abs64 Static Large text smaller than 2^31 bytes 83// pic13 PIC_ Small GOT < 2^13 bytes 84// pic32 PIC_ Medium GOT < 2^32 bytes 85// 86// All code models require that the text segment is smaller than 2GB. 87 88static MCCodeGenInfo *createSparcMCCodeGenInfo(StringRef TT, Reloc::Model RM, 89 CodeModel::Model CM, 90 CodeGenOpt::Level OL) { 91 MCCodeGenInfo *X = new MCCodeGenInfo(); 92 93 // The default 32-bit code model is abs32/pic32 and the default 32-bit 94 // code model for JIT is abs32. 95 switch (CM) { 96 default: break; 97 case CodeModel::Default: 98 case CodeModel::JITDefault: CM = CodeModel::Small; break; 99 } 100 101 X->InitMCCodeGenInfo(RM, CM, OL); 102 return X; 103} 104 105static MCCodeGenInfo *createSparcV9MCCodeGenInfo(StringRef TT, Reloc::Model RM, 106 CodeModel::Model CM, 107 CodeGenOpt::Level OL) { 108 MCCodeGenInfo *X = new MCCodeGenInfo(); 109 110 // The default 64-bit code model is abs44/pic32 and the default 64-bit 111 // code model for JIT is abs64. 112 switch (CM) { 113 default: break; 114 case CodeModel::Default: 115 CM = RM == Reloc::PIC_ ? CodeModel::Small : CodeModel::Medium; 116 break; 117 case CodeModel::JITDefault: 118 CM = CodeModel::Large; 119 break; 120 } 121 122 X->InitMCCodeGenInfo(RM, CM, OL); 123 return X; 124} 125 126static MCStreamer *createMCStreamer(const Target &T, StringRef TT, 127 MCContext &Context, MCAsmBackend &MAB, 128 raw_ostream &OS, MCCodeEmitter *Emitter, 129 const MCSubtargetInfo &STI, bool RelaxAll, 130 bool NoExecStack) { 131 MCStreamer *S = 132 createELFStreamer(Context, MAB, OS, Emitter, RelaxAll, NoExecStack); 133 new SparcTargetELFStreamer(*S); 134 return S; 135} 136 137static MCStreamer * 138createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS, 139 bool isVerboseAsm, bool useCFI, bool useDwarfDirectory, 140 MCInstPrinter *InstPrint, MCCodeEmitter *CE, 141 MCAsmBackend *TAB, bool ShowInst) { 142 143 MCStreamer *S = 144 llvm::createAsmStreamer(Ctx, OS, isVerboseAsm, useCFI, useDwarfDirectory, 145 InstPrint, CE, TAB, ShowInst); 146 new SparcTargetAsmStreamer(*S, OS); 147 return S; 148} 149 150static MCInstPrinter *createSparcMCInstPrinter(const Target &T, 151 unsigned SyntaxVariant, 152 const MCAsmInfo &MAI, 153 const MCInstrInfo &MII, 154 const MCRegisterInfo &MRI, 155 const MCSubtargetInfo &STI) { 156 return new SparcInstPrinter(MAI, MII, MRI, STI); 157} 158 159extern "C" void LLVMInitializeSparcTargetMC() { 160 // Register the MC asm info. 161 RegisterMCAsmInfoFn X(TheSparcTarget, createSparcMCAsmInfo); 162 RegisterMCAsmInfoFn Y(TheSparcV9Target, createSparcV9MCAsmInfo); 163 164 // Register the MC codegen info. 165 TargetRegistry::RegisterMCCodeGenInfo(TheSparcTarget, 166 createSparcMCCodeGenInfo); 167 TargetRegistry::RegisterMCCodeGenInfo(TheSparcV9Target, 168 createSparcV9MCCodeGenInfo); 169 170 // Register the MC instruction info. 171 TargetRegistry::RegisterMCInstrInfo(TheSparcTarget, createSparcMCInstrInfo); 172 TargetRegistry::RegisterMCInstrInfo(TheSparcV9Target, createSparcMCInstrInfo); 173 174 // Register the MC register info. 175 TargetRegistry::RegisterMCRegInfo(TheSparcTarget, createSparcMCRegisterInfo); 176 TargetRegistry::RegisterMCRegInfo(TheSparcV9Target, 177 createSparcMCRegisterInfo); 178 179 // Register the MC subtarget info. 180 TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget, 181 createSparcMCSubtargetInfo); 182 TargetRegistry::RegisterMCSubtargetInfo(TheSparcV9Target, 183 createSparcMCSubtargetInfo); 184 185 // Register the MC Code Emitter. 186 TargetRegistry::RegisterMCCodeEmitter(TheSparcTarget, 187 createSparcMCCodeEmitter); 188 TargetRegistry::RegisterMCCodeEmitter(TheSparcV9Target, 189 createSparcMCCodeEmitter); 190 191 //Register the asm backend. 192 TargetRegistry::RegisterMCAsmBackend(TheSparcTarget, 193 createSparcAsmBackend); 194 TargetRegistry::RegisterMCAsmBackend(TheSparcV9Target, 195 createSparcAsmBackend); 196 197 // Register the object streamer. 198 TargetRegistry::RegisterMCObjectStreamer(TheSparcTarget, 199 createMCStreamer); 200 TargetRegistry::RegisterMCObjectStreamer(TheSparcV9Target, 201 createMCStreamer); 202 203 // Register the asm streamer. 204 TargetRegistry::RegisterAsmStreamer(TheSparcTarget, 205 createMCAsmStreamer); 206 TargetRegistry::RegisterAsmStreamer(TheSparcV9Target, 207 createMCAsmStreamer); 208 209 // Register the MCInstPrinter 210 TargetRegistry::RegisterMCInstPrinter(TheSparcTarget, 211 createSparcMCInstPrinter); 212 TargetRegistry::RegisterMCInstPrinter(TheSparcV9Target, 213 createSparcMCInstPrinter); 214} 215