SparcISelDAGToDAG.cpp revision 00fee65fd21f9615d1a604b8b7d42cd16a3f6b47 
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the SPARC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcTargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/Intrinsics.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24#include "llvm/CodeGen/SelectionDAGISel.h"
25#include "llvm/Target/TargetLowering.h"
26#include "llvm/Support/Compiler.h"
27#include "llvm/Support/Debug.h"
28#include <queue>
29#include <set>
30using namespace llvm;
31
32//===----------------------------------------------------------------------===//
33// TargetLowering Implementation
34//===----------------------------------------------------------------------===//
35
36namespace SPISD {
37  enum {
38    FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
39    CMPICC,      // Compare two GPR operands, set icc.
40    CMPFCC,      // Compare two FP operands, set fcc.
41    BRICC,       // Branch to dest on icc condition
42    BRFCC,       // Branch to dest on fcc condition
43    SELECT_ICC,  // Select between two values using the current ICC flags.
44    SELECT_FCC,  // Select between two values using the current FCC flags.
45
46    Hi, Lo,      // Hi/Lo operations, typically on a global address.
47
48    FTOI,        // FP to Int within a FP register.
49    ITOF,        // Int to FP within a FP register.
50
51    CALL,        // A call instruction.
52    RET_FLAG     // Return with a flag operand.
53  };
54}
55
56/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
57/// condition.
58static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
59  switch (CC) {
60  default: assert(0 && "Unknown integer condition code!");
61  case ISD::SETEQ:  return SPCC::ICC_E;
62  case ISD::SETNE:  return SPCC::ICC_NE;
63  case ISD::SETLT:  return SPCC::ICC_L;
64  case ISD::SETGT:  return SPCC::ICC_G;
65  case ISD::SETLE:  return SPCC::ICC_LE;
66  case ISD::SETGE:  return SPCC::ICC_GE;
67  case ISD::SETULT: return SPCC::ICC_CS;
68  case ISD::SETULE: return SPCC::ICC_LEU;
69  case ISD::SETUGT: return SPCC::ICC_GU;
70  case ISD::SETUGE: return SPCC::ICC_CC;
71  }
72}
73
74/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
75/// FCC condition.
76static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
77  switch (CC) {
78  default: assert(0 && "Unknown fp condition code!");
79  case ISD::SETEQ:
80  case ISD::SETOEQ: return SPCC::FCC_E;
81  case ISD::SETNE:
82  case ISD::SETUNE: return SPCC::FCC_NE;
83  case ISD::SETLT:
84  case ISD::SETOLT: return SPCC::FCC_L;
85  case ISD::SETGT:
86  case ISD::SETOGT: return SPCC::FCC_G;
87  case ISD::SETLE:
88  case ISD::SETOLE: return SPCC::FCC_LE;
89  case ISD::SETGE:
90  case ISD::SETOGE: return SPCC::FCC_GE;
91  case ISD::SETULT: return SPCC::FCC_UL;
92  case ISD::SETULE: return SPCC::FCC_ULE;
93  case ISD::SETUGT: return SPCC::FCC_UG;
94  case ISD::SETUGE: return SPCC::FCC_UGE;
95  case ISD::SETUO:  return SPCC::FCC_U;
96  case ISD::SETO:   return SPCC::FCC_O;
97  case ISD::SETONE: return SPCC::FCC_LG;
98  case ISD::SETUEQ: return SPCC::FCC_UE;
99  }
100}
101
102namespace {
103  class SparcTargetLowering : public TargetLowering {
104    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
105  public:
106    SparcTargetLowering(TargetMachine &TM);
107    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
108
109    /// computeMaskedBitsForTargetNode - Determine which of the bits specified
110    /// in Mask are known to be either zero or one and return them in the
111    /// KnownZero/KnownOne bitsets.
112    virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
113                                                const APInt &Mask,
114                                                APInt &KnownZero,
115                                                APInt &KnownOne,
116                                                const SelectionDAG &DAG,
117                                                unsigned Depth = 0) const;
118
119    virtual std::vector<SDOperand>
120      LowerArguments(Function &F, SelectionDAG &DAG);
121    virtual std::pair<SDOperand, SDOperand>
122      LowerCallTo(SDOperand Chain, const Type *RetTy,
123                  bool RetSExt, bool RetZExt, bool isVarArg,
124                  unsigned CC, bool isTailCall, SDOperand Callee,
125                  ArgListTy &Args, SelectionDAG &DAG);
126    virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
127                                                        MachineBasicBlock *MBB);
128
129    virtual const char *getTargetNodeName(unsigned Opcode) const;
130  };
131}
132
133SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
134  : TargetLowering(TM) {
135
136  // Set up the register classes.
137  addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
138  addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
139  addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
140
141  // Turn FP extload into load/fextend
142  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
143
144  // Sparc doesn't have i1 sign extending load
145  setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
146
147  // Custom legalize GlobalAddress nodes into LO/HI parts.
148  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
149  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
150  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
151
152  // Sparc doesn't have sext_inreg, replace them with shl/sra
153  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
154  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
155  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
156
157  // Sparc has no REM or DIVREM operations.
158  setOperationAction(ISD::UREM, MVT::i32, Expand);
159  setOperationAction(ISD::SREM, MVT::i32, Expand);
160  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
161  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
162
163  // Custom expand fp<->sint
164  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
165  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
166
167  // Expand fp<->uint
168  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
169  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
170
171  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
172  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
173
174  // Sparc has no select or setcc: expand to SELECT_CC.
175  setOperationAction(ISD::SELECT, MVT::i32, Expand);
176  setOperationAction(ISD::SELECT, MVT::f32, Expand);
177  setOperationAction(ISD::SELECT, MVT::f64, Expand);
178  setOperationAction(ISD::SETCC, MVT::i32, Expand);
179  setOperationAction(ISD::SETCC, MVT::f32, Expand);
180  setOperationAction(ISD::SETCC, MVT::f64, Expand);
181
182  // Sparc doesn't have BRCOND either, it has BR_CC.
183  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
184  setOperationAction(ISD::BRIND, MVT::Other, Expand);
185  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
186  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
187  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
188  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
189
190  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
191  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
192  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
193
194  // SPARC has no intrinsics for these particular operations.
195  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
196  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
197  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
198
199  setOperationAction(ISD::FSIN , MVT::f64, Expand);
200  setOperationAction(ISD::FCOS , MVT::f64, Expand);
201  setOperationAction(ISD::FREM , MVT::f64, Expand);
202  setOperationAction(ISD::FSIN , MVT::f32, Expand);
203  setOperationAction(ISD::FCOS , MVT::f32, Expand);
204  setOperationAction(ISD::FREM , MVT::f32, Expand);
205  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
206  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
207  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
208  setOperationAction(ISD::ROTL , MVT::i32, Expand);
209  setOperationAction(ISD::ROTR , MVT::i32, Expand);
210  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
211  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
212  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
213  setOperationAction(ISD::FPOW , MVT::f64, Expand);
214  setOperationAction(ISD::FPOW , MVT::f32, Expand);
215
216  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
217  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
218  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
219
220  // We don't have line number support yet.
221  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
222  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
223  setOperationAction(ISD::LABEL, MVT::Other, Expand);
224
225  // RET must be custom lowered, to meet ABI requirements
226  setOperationAction(ISD::RET               , MVT::Other, Custom);
227
228  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
229  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
230  // VAARG needs to be lowered to not do unaligned accesses for doubles.
231  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
232
233  // Use the default implementation.
234  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
235  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
236  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
237  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
238  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
239
240  setStackPointerRegisterToSaveRestore(SP::O6);
241
242  if (TM.getSubtarget<SparcSubtarget>().isV9()) {
243    setOperationAction(ISD::CTPOP, MVT::i32, Legal);
244  }
245
246  computeRegisterProperties();
247}
248
249const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
250  switch (Opcode) {
251  default: return 0;
252  case SPISD::CMPICC:     return "SPISD::CMPICC";
253  case SPISD::CMPFCC:     return "SPISD::CMPFCC";
254  case SPISD::BRICC:      return "SPISD::BRICC";
255  case SPISD::BRFCC:      return "SPISD::BRFCC";
256  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
257  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
258  case SPISD::Hi:         return "SPISD::Hi";
259  case SPISD::Lo:         return "SPISD::Lo";
260  case SPISD::FTOI:       return "SPISD::FTOI";
261  case SPISD::ITOF:       return "SPISD::ITOF";
262  case SPISD::CALL:       return "SPISD::CALL";
263  case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
264  }
265}
266
267/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
268/// be zero. Op is expected to be a target specific node. Used by DAG
269/// combiner.
270void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
271                                                         const APInt &Mask,
272                                                         APInt &KnownZero,
273                                                         APInt &KnownOne,
274                                                         const SelectionDAG &DAG,
275                                                         unsigned Depth) const {
276  APInt KnownZero2, KnownOne2;
277  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);   // Don't know anything.
278
279  switch (Op.getOpcode()) {
280  default: break;
281  case SPISD::SELECT_ICC:
282  case SPISD::SELECT_FCC:
283    DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
284                          Depth+1);
285    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
286                          Depth+1);
287    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
288    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
289
290    // Only known if known in both the LHS and RHS.
291    KnownOne &= KnownOne2;
292    KnownZero &= KnownZero2;
293    break;
294  }
295}
296
297/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
298/// either one or two GPRs, including FP values.  TODO: we should pass FP values
299/// in FP registers for fastcc functions.
300std::vector<SDOperand>
301SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
302  MachineFunction &MF = DAG.getMachineFunction();
303  MachineRegisterInfo &RegInfo = MF.getRegInfo();
304  std::vector<SDOperand> ArgValues;
305
306  static const unsigned ArgRegs[] = {
307    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
308  };
309
310  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
311  unsigned ArgOffset = 68;
312
313  SDOperand Root = DAG.getRoot();
314  std::vector<SDOperand> OutChains;
315
316  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
317    MVT::ValueType ObjectVT = getValueType(I->getType());
318
319    switch (ObjectVT) {
320    default: assert(0 && "Unhandled argument type!");
321    case MVT::i1:
322    case MVT::i8:
323    case MVT::i16:
324    case MVT::i32:
325      if (I->use_empty()) {                // Argument is dead.
326        if (CurArgReg < ArgRegEnd) ++CurArgReg;
327        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
328      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
329        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
330        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
331        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
332        if (ObjectVT != MVT::i32) {
333          unsigned AssertOp = ISD::AssertSext;
334          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
335                            DAG.getValueType(ObjectVT));
336          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
337        }
338        ArgValues.push_back(Arg);
339      } else {
340        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
341        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
342        SDOperand Load;
343        if (ObjectVT == MVT::i32) {
344          Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
345        } else {
346          ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
347
348          // Sparc is big endian, so add an offset based on the ObjectVT.
349          unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
350          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
351                              DAG.getConstant(Offset, MVT::i32));
352          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
353                                NULL, 0, ObjectVT);
354          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
355        }
356        ArgValues.push_back(Load);
357      }
358
359      ArgOffset += 4;
360      break;
361    case MVT::f32:
362      if (I->use_empty()) {                // Argument is dead.
363        if (CurArgReg < ArgRegEnd) ++CurArgReg;
364        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
365      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
366        // FP value is passed in an integer register.
367        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
368        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
369        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
370
371        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
372        ArgValues.push_back(Arg);
373      } else {
374        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
375        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
376        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
377        ArgValues.push_back(Load);
378      }
379      ArgOffset += 4;
380      break;
381
382    case MVT::i64:
383    case MVT::f64:
384      if (I->use_empty()) {                // Argument is dead.
385        if (CurArgReg < ArgRegEnd) ++CurArgReg;
386        if (CurArgReg < ArgRegEnd) ++CurArgReg;
387        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
388      } else if (/* FIXME: Apparently this isn't safe?? */
389                 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
390                 ((CurArgReg-ArgRegs) & 1) == 0) {
391        // If this is a double argument and the whole thing lives on the stack,
392        // and the argument is aligned, load the double straight from the stack.
393        // We can't do a load in cases like void foo([6ints], int,double),
394        // because the double wouldn't be aligned!
395        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
396        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
397        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
398      } else {
399        SDOperand HiVal;
400        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
401          unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
402          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
403          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
404        } else {
405          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
406          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
407          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
408        }
409
410        SDOperand LoVal;
411        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
412          unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
413          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
414          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
415        } else {
416          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
417          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
418          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
419        }
420
421        // Compose the two halves together into an i64 unit.
422        SDOperand WholeValue =
423          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
424
425        // If we want a double, do a bit convert.
426        if (ObjectVT == MVT::f64)
427          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
428
429        ArgValues.push_back(WholeValue);
430      }
431      ArgOffset += 8;
432      break;
433    }
434  }
435
436  // Store remaining ArgRegs to the stack if this is a varargs function.
437  if (F.getFunctionType()->isVarArg()) {
438    // Remember the vararg offset for the va_start implementation.
439    VarArgsFrameOffset = ArgOffset;
440
441    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
442      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
443      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
444      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
445
446      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
447      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
448
449      OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
450      ArgOffset += 4;
451    }
452  }
453
454  if (!OutChains.empty())
455    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
456                            &OutChains[0], OutChains.size()));
457
458  // Finally, inform the code generator which regs we return values in.
459  switch (getValueType(F.getReturnType())) {
460  default: assert(0 && "Unknown type!");
461  case MVT::isVoid: break;
462  case MVT::i1:
463  case MVT::i8:
464  case MVT::i16:
465  case MVT::i32:
466    MF.getRegInfo().addLiveOut(SP::I0);
467    break;
468  case MVT::i64:
469    MF.getRegInfo().addLiveOut(SP::I0);
470    MF.getRegInfo().addLiveOut(SP::I1);
471    break;
472  case MVT::f32:
473    MF.getRegInfo().addLiveOut(SP::F0);
474    break;
475  case MVT::f64:
476    MF.getRegInfo().addLiveOut(SP::D0);
477    break;
478  }
479
480  return ArgValues;
481}
482
483std::pair<SDOperand, SDOperand>
484SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
485                                 bool RetSExt, bool RetZExt, bool isVarArg,
486                                 unsigned CC, bool isTailCall, SDOperand Callee,
487                                 ArgListTy &Args, SelectionDAG &DAG) {
488  // Count the size of the outgoing arguments.
489  unsigned ArgsSize = 0;
490  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
491    switch (getValueType(Args[i].Ty)) {
492    default: assert(0 && "Unknown value type!");
493    case MVT::i1:
494    case MVT::i8:
495    case MVT::i16:
496    case MVT::i32:
497    case MVT::f32:
498      ArgsSize += 4;
499      break;
500    case MVT::i64:
501    case MVT::f64:
502      ArgsSize += 8;
503      break;
504    }
505  }
506  if (ArgsSize > 4*6)
507    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
508  else
509    ArgsSize = 0;
510
511  // Keep stack frames 8-byte aligned.
512  ArgsSize = (ArgsSize+7) & ~7;
513
514  Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
515
516  SDOperand StackPtr;
517  std::vector<SDOperand> Stores;
518  std::vector<SDOperand> RegValuesToPass;
519  unsigned ArgOffset = 68;
520  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
521    SDOperand Val = Args[i].Node;
522    MVT::ValueType ObjectVT = Val.getValueType();
523    SDOperand ValToStore(0, 0);
524    unsigned ObjSize;
525    switch (ObjectVT) {
526    default: assert(0 && "Unhandled argument type!");
527    case MVT::i1:
528    case MVT::i8:
529    case MVT::i16: {
530      // Promote the integer to 32-bits.  If the input type is signed, use a
531      // sign extend, otherwise use a zero extend.
532      ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
533      if (Args[i].isSExt)
534        ExtendKind = ISD::SIGN_EXTEND;
535      else if (Args[i].isZExt)
536        ExtendKind = ISD::ZERO_EXTEND;
537      Val = DAG.getNode(ExtendKind, MVT::i32, Val);
538      // FALL THROUGH
539    }
540    case MVT::i32:
541      ObjSize = 4;
542
543      if (RegValuesToPass.size() >= 6) {
544        ValToStore = Val;
545      } else {
546        RegValuesToPass.push_back(Val);
547      }
548      break;
549    case MVT::f32:
550      ObjSize = 4;
551      if (RegValuesToPass.size() >= 6) {
552        ValToStore = Val;
553      } else {
554        // Convert this to a FP value in an int reg.
555        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
556        RegValuesToPass.push_back(Val);
557      }
558      break;
559    case MVT::f64:
560      ObjSize = 8;
561      // If we can store this directly into the outgoing slot, do so.  We can
562      // do this when all ArgRegs are used and if the outgoing slot is aligned.
563      // FIXME: McGill/misr fails with this.
564      if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
565        ValToStore = Val;
566        break;
567      }
568
569      // Otherwise, convert this to a FP value in int regs.
570      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
571      // FALL THROUGH
572    case MVT::i64:
573      ObjSize = 8;
574      if (RegValuesToPass.size() >= 6) {
575        ValToStore = Val;    // Whole thing is passed in memory.
576        break;
577      }
578
579      // Split the value into top and bottom part.  Top part goes in a reg.
580      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
581                                 DAG.getConstant(1, MVT::i32));
582      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
583                                 DAG.getConstant(0, MVT::i32));
584      RegValuesToPass.push_back(Hi);
585
586      if (RegValuesToPass.size() >= 6) {
587        ValToStore = Lo;
588        ArgOffset += 4;
589        ObjSize = 4;
590      } else {
591        RegValuesToPass.push_back(Lo);
592      }
593      break;
594    }
595
596    if (ValToStore.Val) {
597      if (!StackPtr.Val) {
598        StackPtr = DAG.getRegister(SP::O6, MVT::i32);
599      }
600      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
601      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
602      Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
603    }
604    ArgOffset += ObjSize;
605  }
606
607  // Emit all stores, make sure the occur before any copies into physregs.
608  if (!Stores.empty())
609    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
610
611  static const unsigned ArgRegs[] = {
612    SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
613  };
614
615  // Build a sequence of copy-to-reg nodes chained together with token chain
616  // and flag operands which copy the outgoing args into O[0-5].
617  SDOperand InFlag;
618  for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
619    Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
620    InFlag = Chain.getValue(1);
621  }
622
623  // If the callee is a GlobalAddress node (quite common, every direct call is)
624  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
625  // Likewise ExternalSymbol -> TargetExternalSymbol.
626  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
627    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
628  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
629    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
630
631  std::vector<MVT::ValueType> NodeTys;
632  NodeTys.push_back(MVT::Other);   // Returns a chain
633  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
634  SDOperand Ops[] = { Chain, Callee, InFlag };
635  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
636  InFlag = Chain.getValue(1);
637
638  MVT::ValueType RetTyVT = getValueType(RetTy);
639  SDOperand RetVal;
640  if (RetTyVT != MVT::isVoid) {
641    switch (RetTyVT) {
642    default: assert(0 && "Unknown value type to return!");
643    case MVT::i1:
644    case MVT::i8:
645    case MVT::i16: {
646      RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
647      Chain = RetVal.getValue(1);
648
649      // Add a note to keep track of whether it is sign or zero extended.
650      ISD::NodeType AssertKind = ISD::DELETED_NODE;
651      if (RetSExt)
652        AssertKind = ISD::AssertSext;
653      else if (RetZExt)
654        AssertKind = ISD::AssertZext;
655
656      if (AssertKind != ISD::DELETED_NODE)
657        RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal,
658                             DAG.getValueType(RetTyVT));
659
660      RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
661      break;
662    }
663    case MVT::i32:
664      RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
665      Chain = RetVal.getValue(1);
666      break;
667    case MVT::f32:
668      RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
669      Chain = RetVal.getValue(1);
670      break;
671    case MVT::f64:
672      RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
673      Chain = RetVal.getValue(1);
674      break;
675    case MVT::i64:
676      SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
677      SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
678                                        Lo.getValue(2));
679      RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
680      Chain = Hi.getValue(1);
681      break;
682    }
683  }
684
685  Chain = DAG.getCALLSEQ_END(Chain,
686                             DAG.getConstant(ArgsSize, getPointerTy()),
687                             DAG.getConstant(0, getPointerTy()),
688                             SDOperand());
689  return std::make_pair(RetVal, Chain);
690}
691
692// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
693// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
694static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
695                             ISD::CondCode CC, unsigned &SPCC) {
696  if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
697      CC == ISD::SETNE &&
698      ((LHS.getOpcode() == SPISD::SELECT_ICC &&
699        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
700       (LHS.getOpcode() == SPISD::SELECT_FCC &&
701        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
702      isa<ConstantSDNode>(LHS.getOperand(0)) &&
703      isa<ConstantSDNode>(LHS.getOperand(1)) &&
704      cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
705      cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
706    SDOperand CMPCC = LHS.getOperand(3);
707    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
708    LHS = CMPCC.getOperand(0);
709    RHS = CMPCC.getOperand(1);
710  }
711}
712
713
714SDOperand SparcTargetLowering::
715LowerOperation(SDOperand Op, SelectionDAG &DAG) {
716  switch (Op.getOpcode()) {
717  default: assert(0 && "Should not custom lower this!");
718  case ISD::GlobalTLSAddress:
719    assert(0 && "TLS not implemented for Sparc.");
720  case ISD::GlobalAddress: {
721    GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
722    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
723    SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
724    SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
725    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
726  }
727  case ISD::ConstantPool: {
728    Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal();
729    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
730                                  cast<ConstantPoolSDNode>(Op)->getAlignment());
731    SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
732    SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
733    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
734  }
735  case ISD::FP_TO_SINT:
736    // Convert the fp value to integer in an FP register.
737    assert(Op.getValueType() == MVT::i32);
738    Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
739    return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
740  case ISD::SINT_TO_FP: {
741    assert(Op.getOperand(0).getValueType() == MVT::i32);
742    SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
743    // Convert the int value to FP in an FP register.
744    return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
745  }
746  case ISD::BR_CC: {
747    SDOperand Chain = Op.getOperand(0);
748    ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
749    SDOperand LHS = Op.getOperand(2);
750    SDOperand RHS = Op.getOperand(3);
751    SDOperand Dest = Op.getOperand(4);
752    unsigned Opc, SPCC = ~0U;
753
754    // If this is a br_cc of a "setcc", and if the setcc got lowered into
755    // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
756    LookThroughSetCC(LHS, RHS, CC, SPCC);
757
758    // Get the condition flag.
759    SDOperand CompareFlag;
760    if (LHS.getValueType() == MVT::i32) {
761      std::vector<MVT::ValueType> VTs;
762      VTs.push_back(MVT::i32);
763      VTs.push_back(MVT::Flag);
764      SDOperand Ops[2] = { LHS, RHS };
765      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
766      if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
767      Opc = SPISD::BRICC;
768    } else {
769      CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
770      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
771      Opc = SPISD::BRFCC;
772    }
773    return DAG.getNode(Opc, MVT::Other, Chain, Dest,
774                       DAG.getConstant(SPCC, MVT::i32), CompareFlag);
775  }
776  case ISD::SELECT_CC: {
777    SDOperand LHS = Op.getOperand(0);
778    SDOperand RHS = Op.getOperand(1);
779    ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
780    SDOperand TrueVal = Op.getOperand(2);
781    SDOperand FalseVal = Op.getOperand(3);
782    unsigned Opc, SPCC = ~0U;
783
784    // If this is a select_cc of a "setcc", and if the setcc got lowered into
785    // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
786    LookThroughSetCC(LHS, RHS, CC, SPCC);
787
788    SDOperand CompareFlag;
789    if (LHS.getValueType() == MVT::i32) {
790      std::vector<MVT::ValueType> VTs;
791      VTs.push_back(LHS.getValueType());   // subcc returns a value
792      VTs.push_back(MVT::Flag);
793      SDOperand Ops[2] = { LHS, RHS };
794      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
795      Opc = SPISD::SELECT_ICC;
796      if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
797    } else {
798      CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
799      Opc = SPISD::SELECT_FCC;
800      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
801    }
802    return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
803                       DAG.getConstant(SPCC, MVT::i32), CompareFlag);
804  }
805  case ISD::VASTART: {
806    // vastart just stores the address of the VarArgsFrameIndex slot into the
807    // memory location argument.
808    SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
809                                   DAG.getRegister(SP::I6, MVT::i32),
810                                DAG.getConstant(VarArgsFrameOffset, MVT::i32));
811    const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
812    return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
813  }
814  case ISD::VAARG: {
815    SDNode *Node = Op.Val;
816    MVT::ValueType VT = Node->getValueType(0);
817    SDOperand InChain = Node->getOperand(0);
818    SDOperand VAListPtr = Node->getOperand(1);
819    const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
820    SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, SV, 0);
821    // Increment the pointer, VAList, to the next vaarg
822    SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
823                                    DAG.getConstant(MVT::getSizeInBits(VT)/8,
824                                                    getPointerTy()));
825    // Store the incremented VAList to the legalized pointer
826    InChain = DAG.getStore(VAList.getValue(1), NextPtr,
827                           VAListPtr, SV, 0);
828    // Load the actual argument out of the pointer VAList, unless this is an
829    // f64 load.
830    if (VT != MVT::f64) {
831      return DAG.getLoad(VT, InChain, VAList, NULL, 0);
832    } else {
833      // Otherwise, load it as i64, then do a bitconvert.
834      SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
835      std::vector<MVT::ValueType> Tys;
836      Tys.push_back(MVT::f64);
837      Tys.push_back(MVT::Other);
838      // Bit-Convert the value to f64.
839      SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
840                           V.getValue(1) };
841      return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
842    }
843  }
844  case ISD::DYNAMIC_STACKALLOC: {
845    SDOperand Chain = Op.getOperand(0);  // Legalize the chain.
846    SDOperand Size  = Op.getOperand(1);  // Legalize the size.
847
848    unsigned SPReg = SP::O6;
849    SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
850    SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);    // Value
851    Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP);      // Output chain
852
853    // The resultant pointer is actually 16 words from the bottom of the stack,
854    // to provide a register spill area.
855    SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
856                                   DAG.getConstant(96, MVT::i32));
857    std::vector<MVT::ValueType> Tys;
858    Tys.push_back(MVT::i32);
859    Tys.push_back(MVT::Other);
860    SDOperand Ops[2] = { NewVal, Chain };
861    return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
862  }
863  case ISD::RET: {
864    SDOperand Copy;
865
866    switch(Op.getNumOperands()) {
867    default:
868      assert(0 && "Do not know how to return this many arguments!");
869      abort();
870    case 1:
871      return SDOperand(); // ret void is legal
872    case 3: {
873      unsigned ArgReg;
874      switch(Op.getOperand(1).getValueType()) {
875      default: assert(0 && "Unknown type to return!");
876      case MVT::i32: ArgReg = SP::I0; break;
877      case MVT::f32: ArgReg = SP::F0; break;
878      case MVT::f64: ArgReg = SP::D0; break;
879      }
880      Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
881                              SDOperand());
882      break;
883    }
884    case 5:
885      Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
886                              SDOperand());
887      Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
888      break;
889    }
890    return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
891  }
892  // Frame & Return address.  Currently unimplemented
893  case ISD::RETURNADDR:         break;
894  case ISD::FRAMEADDR:          break;
895  }
896  return SDOperand();
897}
898
899MachineBasicBlock *
900SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
901                                                 MachineBasicBlock *BB) {
902  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
903  unsigned BROpcode;
904  unsigned CC;
905  // Figure out the conditional branch opcode to use for this select_cc.
906  switch (MI->getOpcode()) {
907  default: assert(0 && "Unknown SELECT_CC!");
908  case SP::SELECT_CC_Int_ICC:
909  case SP::SELECT_CC_FP_ICC:
910  case SP::SELECT_CC_DFP_ICC:
911    BROpcode = SP::BCOND;
912    break;
913  case SP::SELECT_CC_Int_FCC:
914  case SP::SELECT_CC_FP_FCC:
915  case SP::SELECT_CC_DFP_FCC:
916    BROpcode = SP::FBCOND;
917    break;
918  }
919
920  CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
921
922  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
923  // control-flow pattern.  The incoming instruction knows the destination vreg
924  // to set, the condition code register to branch on, the true/false values to
925  // select between, and a branch opcode to use.
926  const BasicBlock *LLVM_BB = BB->getBasicBlock();
927  ilist<MachineBasicBlock>::iterator It = BB;
928  ++It;
929
930  //  thisMBB:
931  //  ...
932  //   TrueVal = ...
933  //   [f]bCC copy1MBB
934  //   fallthrough --> copy0MBB
935  MachineBasicBlock *thisMBB = BB;
936  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
937  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
938  BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
939  MachineFunction *F = BB->getParent();
940  F->getBasicBlockList().insert(It, copy0MBB);
941  F->getBasicBlockList().insert(It, sinkMBB);
942  // Update machine-CFG edges by first adding all successors of the current
943  // block to the new block which will contain the Phi node for the select.
944  for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
945      e = BB->succ_end(); i != e; ++i)
946    sinkMBB->addSuccessor(*i);
947  // Next, remove all successors of the current block, and add the true
948  // and fallthrough blocks as its successors.
949  while(!BB->succ_empty())
950    BB->removeSuccessor(BB->succ_begin());
951  BB->addSuccessor(copy0MBB);
952  BB->addSuccessor(sinkMBB);
953
954  //  copy0MBB:
955  //   %FalseValue = ...
956  //   # fallthrough to sinkMBB
957  BB = copy0MBB;
958
959  // Update machine-CFG edges
960  BB->addSuccessor(sinkMBB);
961
962  //  sinkMBB:
963  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
964  //  ...
965  BB = sinkMBB;
966  BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
967    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
968    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
969
970  delete MI;   // The pseudo instruction is gone now.
971  return BB;
972}
973
974//===----------------------------------------------------------------------===//
975// Instruction Selector Implementation
976//===----------------------------------------------------------------------===//
977
978//===--------------------------------------------------------------------===//
979/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
980/// instructions for SelectionDAG operations.
981///
982namespace {
983class SparcDAGToDAGISel : public SelectionDAGISel {
984  SparcTargetLowering Lowering;
985
986  /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
987  /// make the right decision when generating code for different targets.
988  const SparcSubtarget &Subtarget;
989public:
990  SparcDAGToDAGISel(TargetMachine &TM)
991    : SelectionDAGISel(Lowering), Lowering(TM),
992      Subtarget(TM.getSubtarget<SparcSubtarget>()) {
993  }
994
995  SDNode *Select(SDOperand Op);
996
997  // Complex Pattern Selectors.
998  bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2);
999  bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base,
1000                    SDOperand &Offset);
1001
1002  /// InstructionSelectBasicBlock - This callback is invoked by
1003  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1004  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
1005
1006  virtual const char *getPassName() const {
1007    return "SPARC DAG->DAG Pattern Instruction Selection";
1008  }
1009
1010  // Include the pieces autogenerated from the target description.
1011#include "SparcGenDAGISel.inc"
1012};
1013}  // end anonymous namespace
1014
1015/// InstructionSelectBasicBlock - This callback is invoked by
1016/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
1017void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
1018  DEBUG(BB->dump());
1019
1020  // Select target instructions for the DAG.
1021  DAG.setRoot(SelectRoot(DAG.getRoot()));
1022  DAG.RemoveDeadNodes();
1023
1024  // Emit machine code to BB.
1025  ScheduleAndEmitDAG(DAG);
1026}
1027
1028bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr,
1029                                     SDOperand &Base, SDOperand &Offset) {
1030  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1031    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1032    Offset = CurDAG->getTargetConstant(0, MVT::i32);
1033    return true;
1034  }
1035  if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1036      Addr.getOpcode() == ISD::TargetGlobalAddress)
1037    return false;  // direct calls.
1038
1039  if (Addr.getOpcode() == ISD::ADD) {
1040    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1041      if (Predicate_simm13(CN)) {
1042        if (FrameIndexSDNode *FIN =
1043                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1044          // Constant offset from frame ref.
1045          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1046        } else {
1047          Base = Addr.getOperand(0);
1048        }
1049        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1050        return true;
1051      }
1052    }
1053    if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1054      Base = Addr.getOperand(1);
1055      Offset = Addr.getOperand(0).getOperand(0);
1056      return true;
1057    }
1058    if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1059      Base = Addr.getOperand(0);
1060      Offset = Addr.getOperand(1).getOperand(0);
1061      return true;
1062    }
1063  }
1064  Base = Addr;
1065  Offset = CurDAG->getTargetConstant(0, MVT::i32);
1066  return true;
1067}
1068
1069bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr,
1070                                     SDOperand &R1,  SDOperand &R2) {
1071  if (Addr.getOpcode() == ISD::FrameIndex) return false;
1072  if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1073      Addr.getOpcode() == ISD::TargetGlobalAddress)
1074    return false;  // direct calls.
1075
1076  if (Addr.getOpcode() == ISD::ADD) {
1077    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1078        Predicate_simm13(Addr.getOperand(1).Val))
1079      return false;  // Let the reg+imm pattern catch this!
1080    if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1081        Addr.getOperand(1).getOpcode() == SPISD::Lo)
1082      return false;  // Let the reg+imm pattern catch this!
1083    R1 = Addr.getOperand(0);
1084    R2 = Addr.getOperand(1);
1085    return true;
1086  }
1087
1088  R1 = Addr;
1089  R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1090  return true;
1091}
1092
1093SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
1094  SDNode *N = Op.Val;
1095  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1096      N->getOpcode() < SPISD::FIRST_NUMBER)
1097    return NULL;   // Already selected.
1098
1099  switch (N->getOpcode()) {
1100  default: break;
1101  case ISD::SDIV:
1102  case ISD::UDIV: {
1103    // FIXME: should use a custom expander to expose the SRA to the dag.
1104    SDOperand DivLHS = N->getOperand(0);
1105    SDOperand DivRHS = N->getOperand(1);
1106    AddToISelQueue(DivLHS);
1107    AddToISelQueue(DivRHS);
1108
1109    // Set the Y register to the high-part.
1110    SDOperand TopPart;
1111    if (N->getOpcode() == ISD::SDIV) {
1112      TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1113                                   CurDAG->getTargetConstant(31, MVT::i32)), 0);
1114    } else {
1115      TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1116    }
1117    TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1118                                     CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1119
1120    // FIXME: Handle div by immediate.
1121    unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1122    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
1123                                TopPart);
1124  }
1125  case ISD::MULHU:
1126  case ISD::MULHS: {
1127    // FIXME: Handle mul by immediate.
1128    SDOperand MulLHS = N->getOperand(0);
1129    SDOperand MulRHS = N->getOperand(1);
1130    AddToISelQueue(MulLHS);
1131    AddToISelQueue(MulRHS);
1132    unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1133    SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1134                                        MulLHS, MulRHS);
1135    // The high part is in the Y register.
1136    return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1137    return NULL;
1138  }
1139  }
1140
1141  return SelectCode(Op);
1142}
1143
1144
1145/// createSparcISelDag - This pass converts a legalized DAG into a
1146/// SPARC-specific DAG, ready for instruction scheduling.
1147///
1148FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1149  return new SparcDAGToDAGISel(TM);
1150}
1151