SparcISelDAGToDAG.cpp revision 551bf3f80058a026b6a128dffd5530019e1df1b9
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the SPARC target. 11// 12//===----------------------------------------------------------------------===// 13 14#include "Sparc.h" 15#include "SparcTargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27#include <set> 28using namespace llvm; 29 30//===----------------------------------------------------------------------===// 31// TargetLowering Implementation 32//===----------------------------------------------------------------------===// 33 34namespace SPISD { 35 enum { 36 FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 37 CMPICC, // Compare two GPR operands, set icc. 38 CMPFCC, // Compare two FP operands, set fcc. 39 BRICC, // Branch to dest on icc condition 40 BRFCC, // Branch to dest on fcc condition 41 SELECT_ICC, // Select between two values using the current ICC flags. 42 SELECT_FCC, // Select between two values using the current FCC flags. 43 44 Hi, Lo, // Hi/Lo operations, typically on a global address. 45 46 FTOI, // FP to Int within a FP register. 47 ITOF, // Int to FP within a FP register. 48 49 CALL, // A call instruction. 50 RET_FLAG, // Return with a flag operand. 51 }; 52} 53 54/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 55/// condition. 56static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 57 switch (CC) { 58 default: assert(0 && "Unknown integer condition code!"); 59 case ISD::SETEQ: return SPCC::ICC_E; 60 case ISD::SETNE: return SPCC::ICC_NE; 61 case ISD::SETLT: return SPCC::ICC_L; 62 case ISD::SETGT: return SPCC::ICC_G; 63 case ISD::SETLE: return SPCC::ICC_LE; 64 case ISD::SETGE: return SPCC::ICC_GE; 65 case ISD::SETULT: return SPCC::ICC_CS; 66 case ISD::SETULE: return SPCC::ICC_LEU; 67 case ISD::SETUGT: return SPCC::ICC_GU; 68 case ISD::SETUGE: return SPCC::ICC_CC; 69 } 70} 71 72/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 73/// FCC condition. 74static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 75 switch (CC) { 76 default: assert(0 && "Unknown fp condition code!"); 77 case ISD::SETEQ: return SPCC::FCC_E; 78 case ISD::SETNE: return SPCC::FCC_NE; 79 case ISD::SETLT: return SPCC::FCC_L; 80 case ISD::SETGT: return SPCC::FCC_G; 81 case ISD::SETLE: return SPCC::FCC_LE; 82 case ISD::SETGE: return SPCC::FCC_GE; 83 case ISD::SETULT: return SPCC::FCC_UL; 84 case ISD::SETULE: return SPCC::FCC_ULE; 85 case ISD::SETUGT: return SPCC::FCC_UG; 86 case ISD::SETUGE: return SPCC::FCC_UGE; 87 case ISD::SETUO: return SPCC::FCC_U; 88 case ISD::SETO: return SPCC::FCC_O; 89 case ISD::SETONE: return SPCC::FCC_LG; 90 case ISD::SETUEQ: return SPCC::FCC_UE; 91 } 92} 93 94namespace { 95 class SparcTargetLowering : public TargetLowering { 96 int VarArgsFrameOffset; // Frame offset to start of varargs area. 97 public: 98 SparcTargetLowering(TargetMachine &TM); 99 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 100 101 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 102 /// in Mask are known to be either zero or one and return them in the 103 /// KnownZero/KnownOne bitsets. 104 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 105 uint64_t Mask, 106 uint64_t &KnownZero, 107 uint64_t &KnownOne, 108 unsigned Depth = 0) const; 109 110 virtual std::vector<SDOperand> 111 LowerArguments(Function &F, SelectionDAG &DAG); 112 virtual std::pair<SDOperand, SDOperand> 113 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 114 unsigned CC, 115 bool isTailCall, SDOperand Callee, ArgListTy &Args, 116 SelectionDAG &DAG); 117 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 118 MachineBasicBlock *MBB); 119 120 virtual const char *getTargetNodeName(unsigned Opcode) const; 121 }; 122} 123 124SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 125 : TargetLowering(TM) { 126 127 // Set up the register classes. 128 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 129 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 130 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 131 132 // Custom legalize GlobalAddress nodes into LO/HI parts. 133 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 134 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 135 136 // Sparc doesn't have sext_inreg, replace them with shl/sra 137 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 138 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 139 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 140 141 // Sparc has no REM operation. 142 setOperationAction(ISD::UREM, MVT::i32, Expand); 143 setOperationAction(ISD::SREM, MVT::i32, Expand); 144 145 // Custom expand fp<->sint 146 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 147 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 148 149 // Expand fp<->uint 150 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 151 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 152 153 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 154 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 155 156 // Turn FP extload into load/fextend 157 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 158 159 // Sparc has no select or setcc: expand to SELECT_CC. 160 setOperationAction(ISD::SELECT, MVT::i32, Expand); 161 setOperationAction(ISD::SELECT, MVT::f32, Expand); 162 setOperationAction(ISD::SELECT, MVT::f64, Expand); 163 setOperationAction(ISD::SETCC, MVT::i32, Expand); 164 setOperationAction(ISD::SETCC, MVT::f32, Expand); 165 setOperationAction(ISD::SETCC, MVT::f64, Expand); 166 167 // Sparc doesn't have BRCOND either, it has BR_CC. 168 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 169 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 170 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 171 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 172 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 173 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 174 175 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 176 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 177 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 178 179 // SPARC has no intrinsics for these particular operations. 180 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 181 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 182 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 183 184 setOperationAction(ISD::FSIN , MVT::f64, Expand); 185 setOperationAction(ISD::FCOS , MVT::f64, Expand); 186 setOperationAction(ISD::FSIN , MVT::f32, Expand); 187 setOperationAction(ISD::FCOS , MVT::f32, Expand); 188 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 189 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 190 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 191 setOperationAction(ISD::ROTL , MVT::i32, Expand); 192 setOperationAction(ISD::ROTR , MVT::i32, Expand); 193 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 194 195 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 196 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 197 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 198 199 // We don't have line number support yet. 200 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 201 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 202 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 203 204 // RET must be custom lowered, to meet ABI requirements 205 setOperationAction(ISD::RET , MVT::Other, Custom); 206 207 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 208 setOperationAction(ISD::VASTART , MVT::Other, Custom); 209 // VAARG needs to be lowered to not do unaligned accesses for doubles. 210 setOperationAction(ISD::VAARG , MVT::Other, Custom); 211 212 // Use the default implementation. 213 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 214 setOperationAction(ISD::VAEND , MVT::Other, Expand); 215 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 216 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 217 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 218 219 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 220 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 221 222 setStackPointerRegisterToSaveRestore(SP::O6); 223 224 if (TM.getSubtarget<SparcSubtarget>().isV9()) { 225 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 226 } 227 228 computeRegisterProperties(); 229} 230 231const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 232 switch (Opcode) { 233 default: return 0; 234 case SPISD::CMPICC: return "SPISD::CMPICC"; 235 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 236 case SPISD::BRICC: return "SPISD::BRICC"; 237 case SPISD::BRFCC: return "SPISD::BRFCC"; 238 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 239 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 240 case SPISD::Hi: return "SPISD::Hi"; 241 case SPISD::Lo: return "SPISD::Lo"; 242 case SPISD::FTOI: return "SPISD::FTOI"; 243 case SPISD::ITOF: return "SPISD::ITOF"; 244 case SPISD::CALL: return "SPISD::CALL"; 245 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 246 } 247} 248 249/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 250/// be zero. Op is expected to be a target specific node. Used by DAG 251/// combiner. 252void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 253 uint64_t Mask, 254 uint64_t &KnownZero, 255 uint64_t &KnownOne, 256 unsigned Depth) const { 257 uint64_t KnownZero2, KnownOne2; 258 KnownZero = KnownOne = 0; // Don't know anything. 259 260 switch (Op.getOpcode()) { 261 default: break; 262 case SPISD::SELECT_ICC: 263 case SPISD::SELECT_FCC: 264 ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1); 265 ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1); 266 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 267 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 268 269 // Only known if known in both the LHS and RHS. 270 KnownOne &= KnownOne2; 271 KnownZero &= KnownZero2; 272 break; 273 } 274} 275 276/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 277/// either one or two GPRs, including FP values. TODO: we should pass FP values 278/// in FP registers for fastcc functions. 279std::vector<SDOperand> 280SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 281 MachineFunction &MF = DAG.getMachineFunction(); 282 SSARegMap *RegMap = MF.getSSARegMap(); 283 std::vector<SDOperand> ArgValues; 284 285 static const unsigned ArgRegs[] = { 286 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 287 }; 288 289 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 290 unsigned ArgOffset = 68; 291 292 SDOperand Root = DAG.getRoot(); 293 std::vector<SDOperand> OutChains; 294 295 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 296 MVT::ValueType ObjectVT = getValueType(I->getType()); 297 298 switch (ObjectVT) { 299 default: assert(0 && "Unhandled argument type!"); 300 case MVT::i1: 301 case MVT::i8: 302 case MVT::i16: 303 case MVT::i32: 304 if (I->use_empty()) { // Argument is dead. 305 if (CurArgReg < ArgRegEnd) ++CurArgReg; 306 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 307 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 308 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 309 MF.addLiveIn(*CurArgReg++, VReg); 310 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 311 if (ObjectVT != MVT::i32) { 312 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 313 : ISD::AssertZext; 314 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 315 DAG.getValueType(ObjectVT)); 316 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 317 } 318 ArgValues.push_back(Arg); 319 } else { 320 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 321 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 322 SDOperand Load; 323 if (ObjectVT == MVT::i32) { 324 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 325 } else { 326 unsigned LoadOp = 327 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 328 329 // Sparc is big endian, so add an offset based on the ObjectVT. 330 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 331 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 332 DAG.getConstant(Offset, MVT::i32)); 333 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 334 DAG.getSrcValue(0), ObjectVT); 335 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 336 } 337 ArgValues.push_back(Load); 338 } 339 340 ArgOffset += 4; 341 break; 342 case MVT::f32: 343 if (I->use_empty()) { // Argument is dead. 344 if (CurArgReg < ArgRegEnd) ++CurArgReg; 345 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 346 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 347 // FP value is passed in an integer register. 348 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 349 MF.addLiveIn(*CurArgReg++, VReg); 350 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 351 352 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 353 ArgValues.push_back(Arg); 354 } else { 355 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 356 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 357 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0)); 358 ArgValues.push_back(Load); 359 } 360 ArgOffset += 4; 361 break; 362 363 case MVT::i64: 364 case MVT::f64: 365 if (I->use_empty()) { // Argument is dead. 366 if (CurArgReg < ArgRegEnd) ++CurArgReg; 367 if (CurArgReg < ArgRegEnd) ++CurArgReg; 368 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 369 } else if (/* FIXME: Apparently this isn't safe?? */ 370 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 371 ((CurArgReg-ArgRegs) & 1) == 0) { 372 // If this is a double argument and the whole thing lives on the stack, 373 // and the argument is aligned, load the double straight from the stack. 374 // We can't do a load in cases like void foo([6ints], int,double), 375 // because the double wouldn't be aligned! 376 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 377 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 378 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 379 DAG.getSrcValue(0))); 380 } else { 381 SDOperand HiVal; 382 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 383 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 384 MF.addLiveIn(*CurArgReg++, VRegHi); 385 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 386 } else { 387 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 388 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 389 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 390 } 391 392 SDOperand LoVal; 393 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 394 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 395 MF.addLiveIn(*CurArgReg++, VRegLo); 396 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 397 } else { 398 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 399 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 400 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 401 } 402 403 // Compose the two halves together into an i64 unit. 404 SDOperand WholeValue = 405 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 406 407 // If we want a double, do a bit convert. 408 if (ObjectVT == MVT::f64) 409 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 410 411 ArgValues.push_back(WholeValue); 412 } 413 ArgOffset += 8; 414 break; 415 } 416 } 417 418 // Store remaining ArgRegs to the stack if this is a varargs function. 419 if (F.getFunctionType()->isVarArg()) { 420 // Remember the vararg offset for the va_start implementation. 421 VarArgsFrameOffset = ArgOffset; 422 423 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 424 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 425 MF.addLiveIn(*CurArgReg, VReg); 426 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 427 428 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 429 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 430 431 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 432 Arg, FIPtr, DAG.getSrcValue(0))); 433 ArgOffset += 4; 434 } 435 } 436 437 if (!OutChains.empty()) 438 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 439 440 // Finally, inform the code generator which regs we return values in. 441 switch (getValueType(F.getReturnType())) { 442 default: assert(0 && "Unknown type!"); 443 case MVT::isVoid: break; 444 case MVT::i1: 445 case MVT::i8: 446 case MVT::i16: 447 case MVT::i32: 448 MF.addLiveOut(SP::I0); 449 break; 450 case MVT::i64: 451 MF.addLiveOut(SP::I0); 452 MF.addLiveOut(SP::I1); 453 break; 454 case MVT::f32: 455 MF.addLiveOut(SP::F0); 456 break; 457 case MVT::f64: 458 MF.addLiveOut(SP::D0); 459 break; 460 } 461 462 return ArgValues; 463} 464 465std::pair<SDOperand, SDOperand> 466SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 467 bool isVarArg, unsigned CC, 468 bool isTailCall, SDOperand Callee, 469 ArgListTy &Args, SelectionDAG &DAG) { 470 MachineFunction &MF = DAG.getMachineFunction(); 471 // Count the size of the outgoing arguments. 472 unsigned ArgsSize = 0; 473 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 474 switch (getValueType(Args[i].second)) { 475 default: assert(0 && "Unknown value type!"); 476 case MVT::i1: 477 case MVT::i8: 478 case MVT::i16: 479 case MVT::i32: 480 case MVT::f32: 481 ArgsSize += 4; 482 break; 483 case MVT::i64: 484 case MVT::f64: 485 ArgsSize += 8; 486 break; 487 } 488 } 489 if (ArgsSize > 4*6) 490 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 491 else 492 ArgsSize = 0; 493 494 // Keep stack frames 8-byte aligned. 495 ArgsSize = (ArgsSize+7) & ~7; 496 497 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 498 499 SDOperand StackPtr, NullSV; 500 std::vector<SDOperand> Stores; 501 std::vector<SDOperand> RegValuesToPass; 502 unsigned ArgOffset = 68; 503 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 504 SDOperand Val = Args[i].first; 505 MVT::ValueType ObjectVT = Val.getValueType(); 506 SDOperand ValToStore(0, 0); 507 unsigned ObjSize; 508 switch (ObjectVT) { 509 default: assert(0 && "Unhandled argument type!"); 510 case MVT::i1: 511 case MVT::i8: 512 case MVT::i16: 513 // Promote the integer to 32-bits. If the input type is signed, use a 514 // sign extend, otherwise use a zero extend. 515 if (Args[i].second->isSigned()) 516 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 517 else 518 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 519 // FALL THROUGH 520 case MVT::i32: 521 ObjSize = 4; 522 523 if (RegValuesToPass.size() >= 6) { 524 ValToStore = Val; 525 } else { 526 RegValuesToPass.push_back(Val); 527 } 528 break; 529 case MVT::f32: 530 ObjSize = 4; 531 if (RegValuesToPass.size() >= 6) { 532 ValToStore = Val; 533 } else { 534 // Convert this to a FP value in an int reg. 535 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 536 RegValuesToPass.push_back(Val); 537 } 538 break; 539 case MVT::f64: 540 ObjSize = 8; 541 // If we can store this directly into the outgoing slot, do so. We can 542 // do this when all ArgRegs are used and if the outgoing slot is aligned. 543 // FIXME: McGill/misr fails with this. 544 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 545 ValToStore = Val; 546 break; 547 } 548 549 // Otherwise, convert this to a FP value in int regs. 550 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 551 // FALL THROUGH 552 case MVT::i64: 553 ObjSize = 8; 554 if (RegValuesToPass.size() >= 6) { 555 ValToStore = Val; // Whole thing is passed in memory. 556 break; 557 } 558 559 // Split the value into top and bottom part. Top part goes in a reg. 560 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 561 DAG.getConstant(1, MVT::i32)); 562 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 563 DAG.getConstant(0, MVT::i32)); 564 RegValuesToPass.push_back(Hi); 565 566 if (RegValuesToPass.size() >= 6) { 567 ValToStore = Lo; 568 ArgOffset += 4; 569 ObjSize = 4; 570 } else { 571 RegValuesToPass.push_back(Lo); 572 } 573 break; 574 } 575 576 if (ValToStore.Val) { 577 if (!StackPtr.Val) { 578 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 579 NullSV = DAG.getSrcValue(NULL); 580 } 581 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 582 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 583 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 584 ValToStore, PtrOff, NullSV)); 585 } 586 ArgOffset += ObjSize; 587 } 588 589 // Emit all stores, make sure the occur before any copies into physregs. 590 if (!Stores.empty()) 591 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 592 593 static const unsigned ArgRegs[] = { 594 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 595 }; 596 597 // Build a sequence of copy-to-reg nodes chained together with token chain 598 // and flag operands which copy the outgoing args into O[0-5]. 599 SDOperand InFlag; 600 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 601 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 602 InFlag = Chain.getValue(1); 603 } 604 605 // If the callee is a GlobalAddress node (quite common, every direct call is) 606 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 607 // Likewise ExternalSymbol -> TargetExternalSymbol. 608 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 609 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 610 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 611 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 612 613 std::vector<MVT::ValueType> NodeTys; 614 NodeTys.push_back(MVT::Other); // Returns a chain 615 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 616 std::vector<SDOperand> Ops; 617 Ops.push_back(Chain); 618 Ops.push_back(Callee); 619 if (InFlag.Val) 620 Ops.push_back(InFlag); 621 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops); 622 InFlag = Chain.getValue(1); 623 624 MVT::ValueType RetTyVT = getValueType(RetTy); 625 SDOperand RetVal; 626 if (RetTyVT != MVT::isVoid) { 627 switch (RetTyVT) { 628 default: assert(0 && "Unknown value type to return!"); 629 case MVT::i1: 630 case MVT::i8: 631 case MVT::i16: 632 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 633 Chain = RetVal.getValue(1); 634 635 // Add a note to keep track of whether it is sign or zero extended. 636 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 637 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 638 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 639 break; 640 case MVT::i32: 641 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 642 Chain = RetVal.getValue(1); 643 break; 644 case MVT::f32: 645 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 646 Chain = RetVal.getValue(1); 647 break; 648 case MVT::f64: 649 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 650 Chain = RetVal.getValue(1); 651 break; 652 case MVT::i64: 653 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 654 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 655 Lo.getValue(2)); 656 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 657 Chain = Hi.getValue(1); 658 break; 659 } 660 } 661 662 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 663 DAG.getConstant(ArgsSize, getPointerTy())); 664 665 return std::make_pair(RetVal, Chain); 666} 667 668// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 669// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 670static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 671 ISD::CondCode CC, unsigned &SPCC) { 672 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 673 CC == ISD::SETNE && 674 ((LHS.getOpcode() == SPISD::SELECT_ICC && 675 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 676 (LHS.getOpcode() == SPISD::SELECT_FCC && 677 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 678 isa<ConstantSDNode>(LHS.getOperand(0)) && 679 isa<ConstantSDNode>(LHS.getOperand(1)) && 680 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 681 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 682 SDOperand CMPCC = LHS.getOperand(3); 683 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 684 LHS = CMPCC.getOperand(0); 685 RHS = CMPCC.getOperand(1); 686 } 687} 688 689 690SDOperand SparcTargetLowering:: 691LowerOperation(SDOperand Op, SelectionDAG &DAG) { 692 switch (Op.getOpcode()) { 693 default: assert(0 && "Should not custom lower this!"); 694 case ISD::GlobalAddress: { 695 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 696 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 697 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 698 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 699 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 700 } 701 case ISD::ConstantPool: { 702 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 703 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 704 cast<ConstantPoolSDNode>(Op)->getAlignment()); 705 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 706 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 707 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 708 } 709 case ISD::FP_TO_SINT: 710 // Convert the fp value to integer in an FP register. 711 assert(Op.getValueType() == MVT::i32); 712 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 713 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 714 case ISD::SINT_TO_FP: { 715 assert(Op.getOperand(0).getValueType() == MVT::i32); 716 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 717 // Convert the int value to FP in an FP register. 718 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 719 } 720 case ISD::BR_CC: { 721 SDOperand Chain = Op.getOperand(0); 722 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 723 SDOperand LHS = Op.getOperand(2); 724 SDOperand RHS = Op.getOperand(3); 725 SDOperand Dest = Op.getOperand(4); 726 unsigned Opc, SPCC = ~0U; 727 728 // If this is a br_cc of a "setcc", and if the setcc got lowered into 729 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 730 LookThroughSetCC(LHS, RHS, CC, SPCC); 731 732 // Get the condition flag. 733 SDOperand CompareFlag; 734 if (LHS.getValueType() == MVT::i32) { 735 std::vector<MVT::ValueType> VTs; 736 VTs.push_back(MVT::i32); 737 VTs.push_back(MVT::Flag); 738 std::vector<SDOperand> Ops; 739 Ops.push_back(LHS); 740 Ops.push_back(RHS); 741 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1); 742 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 743 Opc = SPISD::BRICC; 744 } else { 745 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 746 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 747 Opc = SPISD::BRFCC; 748 } 749 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 750 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 751 } 752 case ISD::SELECT_CC: { 753 SDOperand LHS = Op.getOperand(0); 754 SDOperand RHS = Op.getOperand(1); 755 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 756 SDOperand TrueVal = Op.getOperand(2); 757 SDOperand FalseVal = Op.getOperand(3); 758 unsigned Opc, SPCC = ~0U; 759 760 // If this is a select_cc of a "setcc", and if the setcc got lowered into 761 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 762 LookThroughSetCC(LHS, RHS, CC, SPCC); 763 764 SDOperand CompareFlag; 765 if (LHS.getValueType() == MVT::i32) { 766 std::vector<MVT::ValueType> VTs; 767 VTs.push_back(LHS.getValueType()); // subcc returns a value 768 VTs.push_back(MVT::Flag); 769 std::vector<SDOperand> Ops; 770 Ops.push_back(LHS); 771 Ops.push_back(RHS); 772 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1); 773 Opc = SPISD::SELECT_ICC; 774 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 775 } else { 776 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 777 Opc = SPISD::SELECT_FCC; 778 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 779 } 780 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 781 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 782 } 783 case ISD::VASTART: { 784 // vastart just stores the address of the VarArgsFrameIndex slot into the 785 // memory location argument. 786 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 787 DAG.getRegister(SP::I6, MVT::i32), 788 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 789 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset, 790 Op.getOperand(1), Op.getOperand(2)); 791 } 792 case ISD::VAARG: { 793 SDNode *Node = Op.Val; 794 MVT::ValueType VT = Node->getValueType(0); 795 SDOperand InChain = Node->getOperand(0); 796 SDOperand VAListPtr = Node->getOperand(1); 797 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, 798 Node->getOperand(2)); 799 // Increment the pointer, VAList, to the next vaarg 800 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 801 DAG.getConstant(MVT::getSizeInBits(VT)/8, 802 getPointerTy())); 803 // Store the incremented VAList to the legalized pointer 804 InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr, 805 VAListPtr, Node->getOperand(2)); 806 // Load the actual argument out of the pointer VAList, unless this is an 807 // f64 load. 808 if (VT != MVT::f64) { 809 return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0)); 810 } else { 811 // Otherwise, load it as i64, then do a bitconvert. 812 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0)); 813 std::vector<MVT::ValueType> Tys; 814 Tys.push_back(MVT::f64); 815 Tys.push_back(MVT::Other); 816 std::vector<SDOperand> Ops; 817 // Bit-Convert the value to f64. 818 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V)); 819 Ops.push_back(V.getValue(1)); 820 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 821 } 822 } 823 case ISD::DYNAMIC_STACKALLOC: { 824 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 825 SDOperand Size = Op.getOperand(1); // Legalize the size. 826 827 unsigned SPReg = SP::O6; 828 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 829 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 830 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 831 832 // The resultant pointer is actually 16 words from the bottom of the stack, 833 // to provide a register spill area. 834 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 835 DAG.getConstant(96, MVT::i32)); 836 std::vector<MVT::ValueType> Tys; 837 Tys.push_back(MVT::i32); 838 Tys.push_back(MVT::Other); 839 std::vector<SDOperand> Ops; 840 Ops.push_back(NewVal); 841 Ops.push_back(Chain); 842 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops); 843 } 844 case ISD::RET: { 845 SDOperand Copy; 846 847 switch(Op.getNumOperands()) { 848 default: 849 assert(0 && "Do not know how to return this many arguments!"); 850 abort(); 851 case 1: 852 return SDOperand(); // ret void is legal 853 case 2: { 854 unsigned ArgReg; 855 switch(Op.getOperand(1).getValueType()) { 856 default: assert(0 && "Unknown type to return!"); 857 case MVT::i32: ArgReg = SP::I0; break; 858 case MVT::f32: ArgReg = SP::F0; break; 859 case MVT::f64: ArgReg = SP::D0; break; 860 } 861 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 862 SDOperand()); 863 break; 864 } 865 case 3: 866 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2), 867 SDOperand()); 868 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 869 break; 870 } 871 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 872 } 873 } 874} 875 876MachineBasicBlock * 877SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 878 MachineBasicBlock *BB) { 879 unsigned BROpcode; 880 unsigned CC; 881 // Figure out the conditional branch opcode to use for this select_cc. 882 switch (MI->getOpcode()) { 883 default: assert(0 && "Unknown SELECT_CC!"); 884 case SP::SELECT_CC_Int_ICC: 885 case SP::SELECT_CC_FP_ICC: 886 case SP::SELECT_CC_DFP_ICC: 887 BROpcode = SP::BCOND; 888 break; 889 case SP::SELECT_CC_Int_FCC: 890 case SP::SELECT_CC_FP_FCC: 891 case SP::SELECT_CC_DFP_FCC: 892 BROpcode = SP::FBCOND; 893 break; 894 } 895 896 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue(); 897 898 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 899 // control-flow pattern. The incoming instruction knows the destination vreg 900 // to set, the condition code register to branch on, the true/false values to 901 // select between, and a branch opcode to use. 902 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 903 ilist<MachineBasicBlock>::iterator It = BB; 904 ++It; 905 906 // thisMBB: 907 // ... 908 // TrueVal = ... 909 // [f]bCC copy1MBB 910 // fallthrough --> copy0MBB 911 MachineBasicBlock *thisMBB = BB; 912 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 913 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 914 BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC); 915 MachineFunction *F = BB->getParent(); 916 F->getBasicBlockList().insert(It, copy0MBB); 917 F->getBasicBlockList().insert(It, sinkMBB); 918 // Update machine-CFG edges 919 BB->addSuccessor(copy0MBB); 920 BB->addSuccessor(sinkMBB); 921 922 // copy0MBB: 923 // %FalseValue = ... 924 // # fallthrough to sinkMBB 925 BB = copy0MBB; 926 927 // Update machine-CFG edges 928 BB->addSuccessor(sinkMBB); 929 930 // sinkMBB: 931 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 932 // ... 933 BB = sinkMBB; 934 BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg()) 935 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 936 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 937 938 delete MI; // The pseudo instruction is gone now. 939 return BB; 940} 941 942//===----------------------------------------------------------------------===// 943// Instruction Selector Implementation 944//===----------------------------------------------------------------------===// 945 946//===--------------------------------------------------------------------===// 947/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 948/// instructions for SelectionDAG operations. 949/// 950namespace { 951class SparcDAGToDAGISel : public SelectionDAGISel { 952 SparcTargetLowering Lowering; 953 954 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 955 /// make the right decision when generating code for different targets. 956 const SparcSubtarget &Subtarget; 957public: 958 SparcDAGToDAGISel(TargetMachine &TM) 959 : SelectionDAGISel(Lowering), Lowering(TM), 960 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 961 } 962 963 void Select(SDOperand &Result, SDOperand Op); 964 965 // Complex Pattern Selectors. 966 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 967 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 968 969 /// InstructionSelectBasicBlock - This callback is invoked by 970 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 971 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 972 973 virtual const char *getPassName() const { 974 return "SPARC DAG->DAG Pattern Instruction Selection"; 975 } 976 977 // Include the pieces autogenerated from the target description. 978#include "SparcGenDAGISel.inc" 979}; 980} // end anonymous namespace 981 982/// InstructionSelectBasicBlock - This callback is invoked by 983/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 984void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 985 DEBUG(BB->dump()); 986 987 // Select target instructions for the DAG. 988 DAG.setRoot(SelectRoot(DAG.getRoot())); 989 CodeGenMap.clear(); 990 DAG.RemoveDeadNodes(); 991 992 // Emit machine code to BB. 993 ScheduleAndEmitDAG(DAG); 994} 995 996bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 997 SDOperand &Offset) { 998 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 999 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1000 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1001 return true; 1002 } 1003 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1004 Addr.getOpcode() == ISD::TargetGlobalAddress) 1005 return false; // direct calls. 1006 1007 if (Addr.getOpcode() == ISD::ADD) { 1008 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 1009 if (Predicate_simm13(CN)) { 1010 if (FrameIndexSDNode *FIN = 1011 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 1012 // Constant offset from frame ref. 1013 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1014 } else { 1015 Base = Addr.getOperand(0); 1016 } 1017 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 1018 return true; 1019 } 1020 } 1021 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 1022 Base = Addr.getOperand(1); 1023 Offset = Addr.getOperand(0).getOperand(0); 1024 return true; 1025 } 1026 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 1027 Base = Addr.getOperand(0); 1028 Offset = Addr.getOperand(1).getOperand(0); 1029 return true; 1030 } 1031 } 1032 Base = Addr; 1033 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1034 return true; 1035} 1036 1037bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 1038 SDOperand &R2) { 1039 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1040 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1041 Addr.getOpcode() == ISD::TargetGlobalAddress) 1042 return false; // direct calls. 1043 1044 if (Addr.getOpcode() == ISD::ADD) { 1045 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1046 Predicate_simm13(Addr.getOperand(1).Val)) 1047 return false; // Let the reg+imm pattern catch this! 1048 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1049 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1050 return false; // Let the reg+imm pattern catch this! 1051 R1 = Addr.getOperand(0); 1052 R2 = Addr.getOperand(1); 1053 return true; 1054 } 1055 1056 R1 = Addr; 1057 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1058 return true; 1059} 1060 1061void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) { 1062 SDNode *N = Op.Val; 1063 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1064 N->getOpcode() < SPISD::FIRST_NUMBER) { 1065 Result = Op; 1066 return; // Already selected. 1067 } 1068 1069 // If this has already been converted, use it. 1070 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 1071 if (CGMI != CodeGenMap.end()) { 1072 Result = CGMI->second; 1073 return; 1074 } 1075 1076 switch (N->getOpcode()) { 1077 default: break; 1078 case ISD::SDIV: 1079 case ISD::UDIV: { 1080 // FIXME: should use a custom expander to expose the SRA to the dag. 1081 SDOperand DivLHS, DivRHS; 1082 Select(DivLHS, N->getOperand(0)); 1083 Select(DivRHS, N->getOperand(1)); 1084 1085 // Set the Y register to the high-part. 1086 SDOperand TopPart; 1087 if (N->getOpcode() == ISD::SDIV) { 1088 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1089 CurDAG->getTargetConstant(31, MVT::i32)), 0); 1090 } else { 1091 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1092 } 1093 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1094 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 1095 1096 // FIXME: Handle div by immediate. 1097 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1098 Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 1099 return; 1100 } 1101 case ISD::MULHU: 1102 case ISD::MULHS: { 1103 // FIXME: Handle mul by immediate. 1104 SDOperand MulLHS, MulRHS; 1105 Select(MulLHS, N->getOperand(0)); 1106 Select(MulRHS, N->getOperand(1)); 1107 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1108 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1109 MulLHS, MulRHS); 1110 // The high part is in the Y register. 1111 Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); 1112 return; 1113 } 1114 } 1115 1116 SelectCode(Result, Op); 1117} 1118 1119 1120/// createSparcISelDag - This pass converts a legalized DAG into a 1121/// SPARC-specific DAG, ready for instruction scheduling. 1122/// 1123FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1124 return new SparcDAGToDAGISel(TM); 1125} 1126