SparcISelDAGToDAG.cpp revision 6554beffe46033f654400d13c0ed6f7b602d8bf1
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 RET_FLAG, // Return with a flag operand. 50 }; 51} 52 53namespace { 54 class SparcV8TargetLowering : public TargetLowering { 55 int VarArgsFrameOffset; // Frame offset to start of varargs area. 56 public: 57 SparcV8TargetLowering(TargetMachine &TM); 58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 59 virtual std::vector<SDOperand> 60 LowerArguments(Function &F, SelectionDAG &DAG); 61 virtual std::pair<SDOperand, SDOperand> 62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 63 unsigned CC, 64 bool isTailCall, SDOperand Callee, ArgListTy &Args, 65 SelectionDAG &DAG); 66 67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, 68 SelectionDAG &DAG); 69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, 70 Value *VAListV, SelectionDAG &DAG); 71 virtual std::pair<SDOperand,SDOperand> 72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 73 const Type *ArgTy, SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 }; 80} 81 82SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 83 : TargetLowering(TM) { 84 85 // Set up the register classes. 86 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 87 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 88 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 89 90 // Custom legalize GlobalAddress nodes into LO/HI parts. 91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 92 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 93 94 // Sparc doesn't have sext_inreg, replace them with shl/sra 95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 98 99 // Sparc has no REM operation. 100 setOperationAction(ISD::UREM, MVT::i32, Expand); 101 setOperationAction(ISD::SREM, MVT::i32, Expand); 102 103 // Custom expand fp<->sint 104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 105 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 106 107 // Expand fp<->uint 108 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 109 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 110 111 // Turn FP extload into load/fextend 112 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 113 114 // Sparc has no select or setcc: expand to SELECT_CC. 115 setOperationAction(ISD::SELECT, MVT::i32, Expand); 116 setOperationAction(ISD::SELECT, MVT::f32, Expand); 117 setOperationAction(ISD::SELECT, MVT::f64, Expand); 118 setOperationAction(ISD::SETCC, MVT::i32, Expand); 119 setOperationAction(ISD::SETCC, MVT::f32, Expand); 120 setOperationAction(ISD::SETCC, MVT::f64, Expand); 121 122 // Sparc doesn't have BRCOND either, it has BR_CC. 123 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 124 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 125 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 126 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 127 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 128 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 129 130 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 131 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 132 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 133 134 // V8 has no intrinsics for these particular operations. 135 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 136 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 137 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 138 139 computeRegisterProperties(); 140} 141 142/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 143/// either one or two GPRs, including FP values. TODO: we should pass FP values 144/// in FP registers for fastcc functions. 145std::vector<SDOperand> 146SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 147 MachineFunction &MF = DAG.getMachineFunction(); 148 SSARegMap *RegMap = MF.getSSARegMap(); 149 std::vector<SDOperand> ArgValues; 150 151 static const unsigned ArgRegs[] = { 152 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 153 }; 154 155 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 156 unsigned ArgOffset = 68; 157 158 SDOperand Root = DAG.getRoot(); 159 std::vector<SDOperand> OutChains; 160 161 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 162 MVT::ValueType ObjectVT = getValueType(I->getType()); 163 164 switch (ObjectVT) { 165 default: assert(0 && "Unhandled argument type!"); 166 case MVT::i1: 167 case MVT::i8: 168 case MVT::i16: 169 case MVT::i32: 170 if (I->use_empty()) { // Argument is dead. 171 if (CurArgReg < ArgRegEnd) ++CurArgReg; 172 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 173 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 174 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 175 MF.addLiveIn(*CurArgReg++, VReg); 176 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 177 if (ObjectVT != MVT::i32) { 178 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 179 : ISD::AssertZext; 180 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 181 DAG.getValueType(ObjectVT)); 182 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 183 } 184 ArgValues.push_back(Arg); 185 } else { 186 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 187 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 188 SDOperand Load; 189 if (ObjectVT == MVT::i32) { 190 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 191 } else { 192 unsigned LoadOp = 193 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 194 195 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 196 DAG.getSrcValue(0), ObjectVT); 197 } 198 ArgValues.push_back(Load); 199 } 200 201 ArgOffset += 4; 202 break; 203 case MVT::f32: 204 if (I->use_empty()) { // Argument is dead. 205 if (CurArgReg < ArgRegEnd) ++CurArgReg; 206 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 207 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 208 // FP value is passed in an integer register. 209 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 210 MF.addLiveIn(*CurArgReg++, VReg); 211 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 212 213 // We use the stack space that is already reserved for this reg. 214 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 215 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 216 217 SDOperand SV = DAG.getSrcValue(0); 218 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root, 219 Arg, FIPtr, SV); 220 ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV)); 221 } 222 ArgOffset += 4; 223 break; 224 225 case MVT::i64: 226 case MVT::f64: 227 if (I->use_empty()) { // Argument is dead. 228 if (CurArgReg < ArgRegEnd) ++CurArgReg; 229 if (CurArgReg < ArgRegEnd) ++CurArgReg; 230 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 231 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 232 ((CurArgReg-ArgRegs) & 1) == 0) { 233 // If this is a double argument and the whole thing lives on the stack, 234 // and the argument is aligned, load the double straight from the stack. 235 // We can't do a load in cases like void foo([6ints], int,double), 236 // because the double wouldn't be aligned! 237 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 238 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 239 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 240 DAG.getSrcValue(0))); 241 } else { 242 SDOperand HiVal; 243 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 244 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 245 MF.addLiveIn(*CurArgReg++, VRegHi); 246 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 247 } else { 248 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 249 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 250 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 251 } 252 253 SDOperand LoVal; 254 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 255 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 256 MF.addLiveIn(*CurArgReg++, VRegLo); 257 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 258 } else { 259 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 260 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 261 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 262 } 263 264 // Compose the two halves together into an i64 unit. 265 SDOperand WholeValue = 266 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 267 268 if (ObjectVT == MVT::i64) { 269 // If we are emitting an i64, this is what we want. 270 ArgValues.push_back(WholeValue); 271 } else { 272 assert(ObjectVT == MVT::f64); 273 // Otherwise, emit a store to the stack and reload into FPR. 274 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); 275 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 276 SDOperand SV = DAG.getSrcValue(0); 277 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root, 278 WholeValue, FIPtr, SV); 279 ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV)); 280 } 281 } 282 ArgOffset += 8; 283 break; 284 } 285 } 286 287 // Store remaining ArgRegs to the stack if this is a varargs function. 288 if (F.getFunctionType()->isVarArg()) { 289 // Remember the vararg offset for the va_start implementation. 290 VarArgsFrameOffset = ArgOffset; 291 292 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 293 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 294 MF.addLiveIn(*CurArgReg, VReg); 295 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 296 297 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 298 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 299 300 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 301 Arg, FIPtr, DAG.getSrcValue(0))); 302 ArgOffset += 4; 303 } 304 } 305 306 if (!OutChains.empty()) 307 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 308 309 // Finally, inform the code generator which regs we return values in. 310 switch (getValueType(F.getReturnType())) { 311 default: assert(0 && "Unknown type!"); 312 case MVT::isVoid: break; 313 case MVT::i1: 314 case MVT::i8: 315 case MVT::i16: 316 case MVT::i32: 317 MF.addLiveOut(V8::I0); 318 break; 319 case MVT::i64: 320 MF.addLiveOut(V8::I0); 321 MF.addLiveOut(V8::I1); 322 break; 323 case MVT::f32: 324 MF.addLiveOut(V8::F0); 325 break; 326 case MVT::f64: 327 MF.addLiveOut(V8::D0); 328 break; 329 } 330 331 return ArgValues; 332} 333 334std::pair<SDOperand, SDOperand> 335SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 336 bool isVarArg, unsigned CC, 337 bool isTailCall, SDOperand Callee, 338 ArgListTy &Args, SelectionDAG &DAG) { 339 MachineFunction &MF = DAG.getMachineFunction(); 340 // Count the size of the outgoing arguments. 341 unsigned ArgsSize = 0; 342 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 343 switch (getValueType(Args[i].second)) { 344 default: assert(0 && "Unknown value type!"); 345 case MVT::i1: 346 case MVT::i8: 347 case MVT::i16: 348 case MVT::i32: 349 case MVT::f32: 350 ArgsSize += 4; 351 break; 352 case MVT::i64: 353 case MVT::f64: 354 ArgsSize += 8; 355 break; 356 } 357 } 358 if (ArgsSize > 4*6) 359 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 360 else 361 ArgsSize = 0; 362 363 // Keep stack frames 8-byte aligned. 364 ArgsSize = (ArgsSize+7) & ~7; 365 366 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 367 DAG.getConstant(ArgsSize, getPointerTy())); 368 369 SDOperand StackPtr, NullSV; 370 std::vector<SDOperand> Stores; 371 std::vector<SDOperand> RegValuesToPass; 372 unsigned ArgOffset = 68; 373 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 374 SDOperand Val = Args[i].first; 375 MVT::ValueType ObjectVT = Val.getValueType(); 376 SDOperand ValToStore; 377 unsigned ObjSize; 378 switch (ObjectVT) { 379 default: assert(0 && "Unhandled argument type!"); 380 case MVT::i1: 381 case MVT::i8: 382 case MVT::i16: 383 // Promote the integer to 32-bits. If the input type is signed, use a 384 // sign extend, otherwise use a zero extend. 385 if (Args[i].second->isSigned()) 386 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 387 else 388 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 389 // FALL THROUGH 390 case MVT::i32: 391 ObjSize = 4; 392 393 if (RegValuesToPass.size() >= 6) { 394 ValToStore = Val; 395 } else { 396 RegValuesToPass.push_back(Val); 397 } 398 break; 399 case MVT::f32: 400 ObjSize = 4; 401 if (RegValuesToPass.size() >= 6) { 402 ValToStore = Val; 403 } else { 404 // Convert this to a FP value in an int reg. 405 int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4); 406 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 407 SDOperand SV = DAG.getSrcValue(0); 408 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 409 Val, FIPtr, SV); 410 Val = DAG.getLoad(MVT::i32, Store, FIPtr, SV); 411 RegValuesToPass.push_back(Val); 412 } 413 break; 414 case MVT::f64: { 415 ObjSize = 8; 416 // If we can store this directly into the outgoing slot, do so. We can 417 // do this when all ArgRegs are used and if the outgoing slot is aligned. 418 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 419 ValToStore = Val; 420 break; 421 } 422 423 // Otherwise, convert this to a FP value in int regs. 424 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); 425 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 426 SDOperand SV = DAG.getSrcValue(0); 427 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 428 Val, FIPtr, SV); 429 Val = DAG.getLoad(MVT::i64, Store, FIPtr, SV); 430 } 431 // FALL THROUGH 432 case MVT::i64: 433 ObjSize = 8; 434 if (RegValuesToPass.size() >= 6) { 435 ValToStore = Val; // Whole thing is passed in memory. 436 break; 437 } 438 439 // Split the value into top and bottom part. Top part goes in a reg. 440 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 441 DAG.getConstant(1, MVT::i32)); 442 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 443 DAG.getConstant(0, MVT::i32)); 444 RegValuesToPass.push_back(Hi); 445 446 if (RegValuesToPass.size() >= 6) { 447 ValToStore = Lo; 448 } else { 449 RegValuesToPass.push_back(Lo); 450 } 451 break; 452 } 453 454 if (ValToStore.Val) { 455 if (!StackPtr.Val) { 456 StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(), V8::O6, MVT::i32); 457 NullSV = DAG.getSrcValue(NULL); 458 } 459 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 460 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 461 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 462 ValToStore, PtrOff, NullSV)); 463 } 464 ArgOffset += ObjSize; 465 } 466 467 // Emit all stores, make sure the occur before any copies into physregs. 468 if (!Stores.empty()) 469 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 470 471 static const unsigned ArgRegs[] = { 472 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 473 }; 474 475 // Build a sequence of copy-to-reg nodes chained together with token chain 476 // and flag operands which copy the outgoing args into O[0-5]. 477 SDOperand InFlag; 478 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 479 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 480 InFlag = Chain.getValue(1); 481 } 482 483 std::vector<MVT::ValueType> RetVals; 484 RetVals.push_back(MVT::Other); 485 RetVals.push_back(MVT::Flag); 486 487 // If the callee is a GlobalAddress node (quite common, every direct call is) 488 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 489 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 490 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 491 492 std::vector<MVT::ValueType> NodeTys; 493 NodeTys.push_back(MVT::Other); // Returns a chain 494 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 495 if (InFlag.Val) 496 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0); 497 else 498 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0); 499 InFlag = Chain.getValue(1); 500 501 MVT::ValueType RetTyVT = getValueType(RetTy); 502 SDOperand RetVal; 503 if (RetTyVT != MVT::isVoid) { 504 switch (RetTyVT) { 505 default: assert(0 && "Unknown value type to return!"); 506 case MVT::i1: 507 case MVT::i8: 508 case MVT::i16: 509 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 510 Chain = RetVal.getValue(1); 511 512 // Add a note to keep track of whether it is sign or zero extended. 513 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 514 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 515 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 516 break; 517 case MVT::i32: 518 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 519 Chain = RetVal.getValue(1); 520 break; 521 case MVT::f32: 522 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 523 Chain = RetVal.getValue(1); 524 break; 525 case MVT::f64: 526 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 527 Chain = RetVal.getValue(1); 528 break; 529 case MVT::i64: 530 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 531 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 532 Lo.getValue(2)); 533 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 534 Chain = Hi.getValue(1); 535 break; 536 } 537 } 538 539 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 540 DAG.getConstant(ArgsSize, getPointerTy())); 541 542 MVT::ValueType ActualRetTyVT = RetTyVT; 543 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 544 ActualRetTyVT = MVT::i32; // Promote result to i32. 545 546 return std::make_pair(RetVal, Chain); 547} 548 549SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 550 SelectionDAG &DAG) { 551 SDOperand Copy; 552 switch (Op.getValueType()) { 553 default: assert(0 && "Unknown type to return!"); 554 case MVT::i32: 555 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand()); 556 break; 557 case MVT::f32: 558 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand()); 559 break; 560 case MVT::f64: 561 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand()); 562 break; 563 case MVT::i64: 564 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 565 DAG.getConstant(1, MVT::i32)); 566 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 567 DAG.getConstant(0, MVT::i32)); 568 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand()); 569 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1)); 570 break; 571 } 572 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 573} 574 575SDOperand SparcV8TargetLowering:: 576LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, 577 SelectionDAG &DAG) { 578 579 assert(0 && "Unimp"); 580 abort(); 581} 582 583std::pair<SDOperand,SDOperand> SparcV8TargetLowering:: 584LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 585 const Type *ArgTy, SelectionDAG &DAG) { 586 assert(0 && "Unimp"); 587 abort(); 588} 589 590std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 591LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 592 SelectionDAG &DAG) { 593 assert(0 && "Unimp"); 594 abort(); 595} 596 597SDOperand SparcV8TargetLowering:: 598LowerOperation(SDOperand Op, SelectionDAG &DAG) { 599 switch (Op.getOpcode()) { 600 default: assert(0 && "Should not custom lower this!"); 601 case ISD::GlobalAddress: { 602 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 603 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 604 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 605 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 606 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 607 } 608 case ISD::ConstantPool: { 609 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 610 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 611 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 612 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 613 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 614 } 615 case ISD::FP_TO_SINT: { 616 // Convert the fp value to integer in an FP register. 617 Op = DAG.getNode(V8ISD::FTOI, Op.getOperand(0).getValueType(), 618 Op.getOperand(0)); 619 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8; 620 int FrameIdx = 621 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size); 622 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 623 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 624 Op, FI, DAG.getSrcValue(0)); 625 return DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0)); 626 } 627 case ISD::SINT_TO_FP: { 628 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8; 629 int FrameIdx = 630 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size); 631 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 632 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 633 Op.getOperand(0), FI, DAG.getSrcValue(0)); 634 635 Op = DAG.getLoad(Op.getValueType(), ST, FI, DAG.getSrcValue(0)); 636 637 // Convert the int value to FP in an FP register. 638 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op); 639 } 640 case ISD::BR_CC: { 641 SDOperand Chain = Op.getOperand(0); 642 SDOperand CC = Op.getOperand(1); 643 SDOperand LHS = Op.getOperand(2); 644 SDOperand RHS = Op.getOperand(3); 645 SDOperand Dest = Op.getOperand(4); 646 647 // Get the condition flag. 648 if (LHS.getValueType() == MVT::i32) { 649 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS); 650 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 651 } else { 652 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 653 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 654 } 655 } 656 case ISD::SELECT_CC: { 657 SDOperand LHS = Op.getOperand(0); 658 SDOperand RHS = Op.getOperand(1); 659 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 660 SDOperand TrueVal = Op.getOperand(2); 661 SDOperand FalseVal = Op.getOperand(3); 662 663 unsigned Opc; 664 Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC; 665 SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS); 666 667 Opc = LHS.getValueType() == MVT::i32 ? 668 V8ISD::SELECT_ICC : V8ISD::SELECT_FCC; 669 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 670 DAG.getConstant(CC, MVT::i32), CompareFlag); 671 } 672 } 673} 674 675MachineBasicBlock * 676SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 677 MachineBasicBlock *BB) { 678 unsigned BROpcode; 679 // Figure out the conditional branch opcode to use for this select_cc. 680 switch (MI->getOpcode()) { 681 default: assert(0 && "Unknown SELECT_CC!"); 682 case V8::SELECT_CC_Int_ICC: 683 case V8::SELECT_CC_FP_ICC: 684 case V8::SELECT_CC_DFP_ICC: 685 // Integer compare. 686 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 687 default: assert(0 && "Unknown integer condition code!"); 688 case ISD::SETEQ: BROpcode = V8::BE; break; 689 case ISD::SETNE: BROpcode = V8::BNE; break; 690 case ISD::SETLT: BROpcode = V8::BL; break; 691 case ISD::SETGT: BROpcode = V8::BG; break; 692 case ISD::SETLE: BROpcode = V8::BLE; break; 693 case ISD::SETGE: BROpcode = V8::BGE; break; 694 case ISD::SETULT: BROpcode = V8::BCS; break; 695 case ISD::SETULE: BROpcode = V8::BLEU; break; 696 case ISD::SETUGT: BROpcode = V8::BGU; break; 697 case ISD::SETUGE: BROpcode = V8::BCC; break; 698 } 699 break; 700 case V8::SELECT_CC_Int_FCC: 701 case V8::SELECT_CC_FP_FCC: 702 case V8::SELECT_CC_DFP_FCC: 703 // FP compare. 704 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 705 default: assert(0 && "Unknown fp condition code!"); 706 case ISD::SETEQ: BROpcode = V8::FBE; break; 707 case ISD::SETNE: BROpcode = V8::FBNE; break; 708 case ISD::SETLT: BROpcode = V8::FBL; break; 709 case ISD::SETGT: BROpcode = V8::FBG; break; 710 case ISD::SETLE: BROpcode = V8::FBLE; break; 711 case ISD::SETGE: BROpcode = V8::FBGE; break; 712 case ISD::SETULT: BROpcode = V8::FBUL; break; 713 case ISD::SETULE: BROpcode = V8::FBULE; break; 714 case ISD::SETUGT: BROpcode = V8::FBUG; break; 715 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 716 case ISD::SETUO: BROpcode = V8::FBU; break; 717 case ISD::SETO: BROpcode = V8::FBO; break; 718 case ISD::SETONE: BROpcode = V8::FBLG; break; 719 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 720 } 721 break; 722 } 723 724 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 725 // control-flow pattern. The incoming instruction knows the destination vreg 726 // to set, the condition code register to branch on, the true/false values to 727 // select between, and a branch opcode to use. 728 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 729 ilist<MachineBasicBlock>::iterator It = BB; 730 ++It; 731 732 // thisMBB: 733 // ... 734 // TrueVal = ... 735 // [f]bCC copy1MBB 736 // fallthrough --> copy0MBB 737 MachineBasicBlock *thisMBB = BB; 738 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 739 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 740 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 741 MachineFunction *F = BB->getParent(); 742 F->getBasicBlockList().insert(It, copy0MBB); 743 F->getBasicBlockList().insert(It, sinkMBB); 744 // Update machine-CFG edges 745 BB->addSuccessor(copy0MBB); 746 BB->addSuccessor(sinkMBB); 747 748 // copy0MBB: 749 // %FalseValue = ... 750 // # fallthrough to sinkMBB 751 BB = copy0MBB; 752 753 // Update machine-CFG edges 754 BB->addSuccessor(sinkMBB); 755 756 // sinkMBB: 757 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 758 // ... 759 BB = sinkMBB; 760 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 761 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 762 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 763 764 delete MI; // The pseudo instruction is gone now. 765 return BB; 766} 767 768//===----------------------------------------------------------------------===// 769// Instruction Selector Implementation 770//===----------------------------------------------------------------------===// 771 772//===--------------------------------------------------------------------===// 773/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine 774/// instructions for SelectionDAG operations. 775/// 776namespace { 777class SparcV8DAGToDAGISel : public SelectionDAGISel { 778 SparcV8TargetLowering V8Lowering; 779public: 780 SparcV8DAGToDAGISel(TargetMachine &TM) 781 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 782 783 SDOperand Select(SDOperand Op); 784 785 // Complex Pattern Selectors. 786 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 787 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 788 789 /// InstructionSelectBasicBlock - This callback is invoked by 790 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 791 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 792 793 virtual const char *getPassName() const { 794 return "PowerPC DAG->DAG Pattern Instruction Selection"; 795 } 796 797 // Include the pieces autogenerated from the target description. 798#include "SparcV8GenDAGISel.inc" 799}; 800} // end anonymous namespace 801 802/// InstructionSelectBasicBlock - This callback is invoked by 803/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 804void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 805 DEBUG(BB->dump()); 806 807 // Select target instructions for the DAG. 808 DAG.setRoot(Select(DAG.getRoot())); 809 CodeGenMap.clear(); 810 DAG.RemoveDeadNodes(); 811 812 // Emit machine code to BB. 813 ScheduleAndEmitDAG(DAG); 814} 815 816bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 817 SDOperand &Offset) { 818 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 819 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 820 Offset = CurDAG->getTargetConstant(0, MVT::i32); 821 return true; 822 } 823 824 if (Addr.getOpcode() == ISD::ADD) { 825 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 826 if (Predicate_simm13(CN)) { 827 if (FrameIndexSDNode *FIN = 828 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 829 // Constant offset from frame ref. 830 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 831 } else { 832 Base = Select(Addr.getOperand(0)); 833 } 834 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 835 return true; 836 } 837 } 838 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 839 Base = Select(Addr.getOperand(1)); 840 Offset = Addr.getOperand(0).getOperand(0); 841 return true; 842 } 843 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 844 Base = Select(Addr.getOperand(0)); 845 Offset = Addr.getOperand(1).getOperand(0); 846 return true; 847 } 848 } 849 Base = Select(Addr); 850 Offset = CurDAG->getTargetConstant(0, MVT::i32); 851 return true; 852} 853 854bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 855 SDOperand &R2) { 856 if (Addr.getOpcode() == ISD::FrameIndex) return false; 857 if (Addr.getOpcode() == ISD::ADD) { 858 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 859 Predicate_simm13(Addr.getOperand(1).Val)) 860 return false; // Let the reg+imm pattern catch this! 861 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 862 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 863 return false; // Let the reg+imm pattern catch this! 864 R1 = Select(Addr.getOperand(0)); 865 R2 = Select(Addr.getOperand(1)); 866 return true; 867 } 868 869 R1 = Select(Addr); 870 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 871 return true; 872} 873 874SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 875 SDNode *N = Op.Val; 876 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 877 N->getOpcode() < V8ISD::FIRST_NUMBER) 878 return Op; // Already selected. 879 // If this has already been converted, use it. 880 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 881 if (CGMI != CodeGenMap.end()) return CGMI->second; 882 883 switch (N->getOpcode()) { 884 default: break; 885 case ISD::FrameIndex: { 886 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 887 if (N->hasOneUse()) 888 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 889 CurDAG->getTargetFrameIndex(FI, MVT::i32), 890 CurDAG->getTargetConstant(0, MVT::i32)); 891 return CodeGenMap[Op] = 892 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 893 CurDAG->getTargetFrameIndex(FI, MVT::i32), 894 CurDAG->getTargetConstant(0, MVT::i32)); 895 } 896 case V8ISD::CMPICC: { 897 // FIXME: Handle compare with immediate. 898 SDOperand LHS = Select(N->getOperand(0)); 899 SDOperand RHS = Select(N->getOperand(1)); 900 SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 901 LHS, RHS); 902 return CodeGenMap[Op] = Result.getValue(1); 903 } 904 case ISD::ADD_PARTS: { 905 SDOperand LHSL = Select(N->getOperand(0)); 906 SDOperand LHSH = Select(N->getOperand(1)); 907 SDOperand RHSL = Select(N->getOperand(2)); 908 SDOperand RHSH = Select(N->getOperand(3)); 909 // FIXME, handle immediate RHS. 910 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 911 LHSL, RHSL); 912 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 913 Low.getValue(1)); 914 CodeGenMap[SDOperand(N, 0)] = Low; 915 CodeGenMap[SDOperand(N, 1)] = Hi; 916 return Op.ResNo ? Hi : Low; 917 } 918 case ISD::SUB_PARTS: { 919 SDOperand LHSL = Select(N->getOperand(0)); 920 SDOperand LHSH = Select(N->getOperand(1)); 921 SDOperand RHSL = Select(N->getOperand(2)); 922 SDOperand RHSH = Select(N->getOperand(3)); 923 // FIXME, handle immediate RHS. 924 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 925 LHSL, RHSL); 926 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 927 Low.getValue(1)); 928 CodeGenMap[SDOperand(N, 0)] = Low; 929 CodeGenMap[SDOperand(N, 1)] = Hi; 930 return Op.ResNo ? Hi : Low; 931 } 932 case ISD::SDIV: 933 case ISD::UDIV: { 934 // FIXME: should use a custom expander to expose the SRA to the dag. 935 SDOperand DivLHS = Select(N->getOperand(0)); 936 SDOperand DivRHS = Select(N->getOperand(1)); 937 938 // Set the Y register to the high-part. 939 SDOperand TopPart; 940 if (N->getOpcode() == ISD::SDIV) { 941 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 942 CurDAG->getTargetConstant(31, MVT::i32)); 943 } else { 944 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 945 } 946 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 947 CurDAG->getRegister(V8::G0, MVT::i32)); 948 949 // FIXME: Handle div by immediate. 950 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 951 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 952 } 953 case ISD::MULHU: 954 case ISD::MULHS: { 955 // FIXME: Handle mul by immediate. 956 SDOperand MulLHS = Select(N->getOperand(0)); 957 SDOperand MulRHS = Select(N->getOperand(1)); 958 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 959 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 960 MulLHS, MulRHS); 961 // The high part is in the Y register. 962 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 963 } 964 case ISD::CALL: 965 // FIXME: This is a workaround for a bug in tblgen. 966 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 967 // Emits: (CALL:void (tglobaladdr:i32):$dst) 968 // Pattern complexity = 2 cost = 1 969 SDOperand N1 = N->getOperand(1); 970 if (N1.getOpcode() != ISD::TargetGlobalAddress && 971 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 972 SDOperand InFlag = SDOperand(0, 0); 973 SDOperand Chain = N->getOperand(0); 974 SDOperand Tmp0 = N1; 975 Chain = Select(Chain); 976 SDOperand Result; 977 if (N->getNumOperands() == 3) { 978 InFlag = Select(N->getOperand(2)); 979 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 980 Chain, InFlag); 981 } else { 982 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 983 Chain); 984 } 985 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 986 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 987 return Result.getValue(Op.ResNo); 988 } 989 P47Fail:; 990 991 } 992 993 return SelectCode(Op); 994} 995 996 997/// createPPCISelDag - This pass converts a legalized DAG into a 998/// PowerPC-specific DAG, ready for instruction scheduling. 999/// 1000FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 1001 return new SparcV8DAGToDAGISel(TM); 1002} 1003