SparcISelDAGToDAG.cpp revision 6baaf915982cd420c4ce81123547314633234520
16ac915abcdb404a00d927fe6308a47fcf09d9519hkuang//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 26ac915abcdb404a00d927fe6308a47fcf09d9519hkuang// 36ac915abcdb404a00d927fe6308a47fcf09d9519hkuang// The LLVM Compiler Infrastructure 46ac915abcdb404a00d927fe6308a47fcf09d9519hkuang// 56ac915abcdb404a00d927fe6308a47fcf09d9519hkuang// This file is distributed under the University of Illinois Open Source 66ac915abcdb404a00d927fe6308a47fcf09d9519hkuang// License. See LICENSE.TXT for details. 76ac915abcdb404a00d927fe6308a47fcf09d9519hkuang// 86ac915abcdb404a00d927fe6308a47fcf09d9519hkuang//===----------------------------------------------------------------------===// 96ac915abcdb404a00d927fe6308a47fcf09d9519hkuang// 106ac915abcdb404a00d927fe6308a47fcf09d9519hkuang// This file defines an instruction selector for the SPARC target. 116ac915abcdb404a00d927fe6308a47fcf09d9519hkuang// 126ac915abcdb404a00d927fe6308a47fcf09d9519hkuang//===----------------------------------------------------------------------===// 136ac915abcdb404a00d927fe6308a47fcf09d9519hkuang 146ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "Sparc.h" 156ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "SparcTargetMachine.h" 166ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/DerivedTypes.h" 176ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/Function.h" 186ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/Intrinsics.h" 196ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/CodeGen/MachineFrameInfo.h" 206ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/CodeGen/MachineFunction.h" 216ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/CodeGen/MachineInstrBuilder.h" 226ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/CodeGen/MachineRegisterInfo.h" 236ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/CodeGen/SelectionDAG.h" 246ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/CodeGen/SelectionDAGISel.h" 256ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/Target/TargetLowering.h" 266ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/Support/Compiler.h" 276ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include "llvm/Support/Debug.h" 286ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include <queue> 296ac915abcdb404a00d927fe6308a47fcf09d9519hkuang#include <set> 306ac915abcdb404a00d927fe6308a47fcf09d9519hkuangusing namespace llvm; 316ac915abcdb404a00d927fe6308a47fcf09d9519hkuang 326ac915abcdb404a00d927fe6308a47fcf09d9519hkuang//===----------------------------------------------------------------------===// 336ac915abcdb404a00d927fe6308a47fcf09d9519hkuang// TargetLowering Implementation 346ac915abcdb404a00d927fe6308a47fcf09d9519hkuang//===----------------------------------------------------------------------===// 356ac915abcdb404a00d927fe6308a47fcf09d9519hkuang 366ac915abcdb404a00d927fe6308a47fcf09d9519hkuangnamespace SPISD { 376ac915abcdb404a00d927fe6308a47fcf09d9519hkuang enum { 386ac915abcdb404a00d927fe6308a47fcf09d9519hkuang FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 396ac915abcdb404a00d927fe6308a47fcf09d9519hkuang CMPICC, // Compare two GPR operands, set icc. 406ac915abcdb404a00d927fe6308a47fcf09d9519hkuang CMPFCC, // Compare two FP operands, set fcc. 416ac915abcdb404a00d927fe6308a47fcf09d9519hkuang BRICC, // Branch to dest on icc condition 426ac915abcdb404a00d927fe6308a47fcf09d9519hkuang BRFCC, // Branch to dest on fcc condition 436ac915abcdb404a00d927fe6308a47fcf09d9519hkuang SELECT_ICC, // Select between two values using the current ICC flags. 446ac915abcdb404a00d927fe6308a47fcf09d9519hkuang SELECT_FCC, // Select between two values using the current FCC flags. 456ac915abcdb404a00d927fe6308a47fcf09d9519hkuang 466ac915abcdb404a00d927fe6308a47fcf09d9519hkuang Hi, Lo, // Hi/Lo operations, typically on a global address. 476ac915abcdb404a00d927fe6308a47fcf09d9519hkuang 486ac915abcdb404a00d927fe6308a47fcf09d9519hkuang FTOI, // FP to Int within a FP register. 496ac915abcdb404a00d927fe6308a47fcf09d9519hkuang ITOF, // Int to FP within a FP register. 506ac915abcdb404a00d927fe6308a47fcf09d9519hkuang 516ac915abcdb404a00d927fe6308a47fcf09d9519hkuang CALL, // A call instruction. 526ac915abcdb404a00d927fe6308a47fcf09d9519hkuang RET_FLAG // Return with a flag operand. 536ac915abcdb404a00d927fe6308a47fcf09d9519hkuang }; 546ac915abcdb404a00d927fe6308a47fcf09d9519hkuang} 556ac915abcdb404a00d927fe6308a47fcf09d9519hkuang 566ac915abcdb404a00d927fe6308a47fcf09d9519hkuang/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 576ac915abcdb404a00d927fe6308a47fcf09d9519hkuang/// condition. 586ac915abcdb404a00d927fe6308a47fcf09d9519hkuangstatic SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 596ac915abcdb404a00d927fe6308a47fcf09d9519hkuang switch (CC) { 606ac915abcdb404a00d927fe6308a47fcf09d9519hkuang default: assert(0 && "Unknown integer condition code!"); 616ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETEQ: return SPCC::ICC_E; 626ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETNE: return SPCC::ICC_NE; 636ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETLT: return SPCC::ICC_L; 646ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETGT: return SPCC::ICC_G; 656ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETLE: return SPCC::ICC_LE; 666ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETGE: return SPCC::ICC_GE; 676ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETULT: return SPCC::ICC_CS; 686ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETULE: return SPCC::ICC_LEU; 696ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETUGT: return SPCC::ICC_GU; 706ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETUGE: return SPCC::ICC_CC; 716ac915abcdb404a00d927fe6308a47fcf09d9519hkuang } 726ac915abcdb404a00d927fe6308a47fcf09d9519hkuang} 736ac915abcdb404a00d927fe6308a47fcf09d9519hkuang 746ac915abcdb404a00d927fe6308a47fcf09d9519hkuang/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 756ac915abcdb404a00d927fe6308a47fcf09d9519hkuang/// FCC condition. 766ac915abcdb404a00d927fe6308a47fcf09d9519hkuangstatic SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 776ac915abcdb404a00d927fe6308a47fcf09d9519hkuang switch (CC) { 786ac915abcdb404a00d927fe6308a47fcf09d9519hkuang default: assert(0 && "Unknown fp condition code!"); 796ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETEQ: 806ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETOEQ: return SPCC::FCC_E; 816ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETNE: 826ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETUNE: return SPCC::FCC_NE; 836ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETLT: 846ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETOLT: return SPCC::FCC_L; 856ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETGT: 866ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETOGT: return SPCC::FCC_G; 876ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETLE: 886ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETOLE: return SPCC::FCC_LE; 896ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETGE: 906ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETOGE: return SPCC::FCC_GE; 916ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETULT: return SPCC::FCC_UL; 926ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETULE: return SPCC::FCC_ULE; 936ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETUGT: return SPCC::FCC_UG; 946ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETUGE: return SPCC::FCC_UGE; 956ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETUO: return SPCC::FCC_U; 966ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETO: return SPCC::FCC_O; 976ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETONE: return SPCC::FCC_LG; 986ac915abcdb404a00d927fe6308a47fcf09d9519hkuang case ISD::SETUEQ: return SPCC::FCC_UE; 996ac915abcdb404a00d927fe6308a47fcf09d9519hkuang } 1006ac915abcdb404a00d927fe6308a47fcf09d9519hkuang} 1016ac915abcdb404a00d927fe6308a47fcf09d9519hkuang 1026ac915abcdb404a00d927fe6308a47fcf09d9519hkuangnamespace { 1036ac915abcdb404a00d927fe6308a47fcf09d9519hkuang class SparcTargetLowering : public TargetLowering { 104 int VarArgsFrameOffset; // Frame offset to start of varargs area. 105 public: 106 SparcTargetLowering(TargetMachine &TM); 107 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 108 109 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 110 /// in Mask are known to be either zero or one and return them in the 111 /// KnownZero/KnownOne bitsets. 112 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 113 const APInt &Mask, 114 APInt &KnownZero, 115 APInt &KnownOne, 116 const SelectionDAG &DAG, 117 unsigned Depth = 0) const; 118 119 virtual std::vector<SDOperand> 120 LowerArguments(Function &F, SelectionDAG &DAG); 121 virtual std::pair<SDOperand, SDOperand> 122 LowerCallTo(SDOperand Chain, const Type *RetTy, 123 bool RetSExt, bool RetZExt, bool isVarArg, 124 unsigned CC, bool isTailCall, SDOperand Callee, 125 ArgListTy &Args, SelectionDAG &DAG); 126 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI, 127 MachineBasicBlock *MBB); 128 129 virtual const char *getTargetNodeName(unsigned Opcode) const; 130 }; 131} 132 133SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 134 : TargetLowering(TM) { 135 136 // Set up the register classes. 137 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 138 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 139 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 140 141 // Turn FP extload into load/fextend 142 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 143 // Sparc doesn't have i1 sign extending load 144 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote); 145 // Turn FP truncstore into trunc + store. 146 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 147 148 // Custom legalize GlobalAddress nodes into LO/HI parts. 149 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 150 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 151 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 152 153 // Sparc doesn't have sext_inreg, replace them with shl/sra 154 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 155 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 157 158 // Sparc has no REM or DIVREM operations. 159 setOperationAction(ISD::UREM, MVT::i32, Expand); 160 setOperationAction(ISD::SREM, MVT::i32, Expand); 161 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 162 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 163 164 // Custom expand fp<->sint 165 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 166 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 167 168 // Expand fp<->uint 169 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 170 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 171 172 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 173 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 174 175 // Sparc has no select or setcc: expand to SELECT_CC. 176 setOperationAction(ISD::SELECT, MVT::i32, Expand); 177 setOperationAction(ISD::SELECT, MVT::f32, Expand); 178 setOperationAction(ISD::SELECT, MVT::f64, Expand); 179 setOperationAction(ISD::SETCC, MVT::i32, Expand); 180 setOperationAction(ISD::SETCC, MVT::f32, Expand); 181 setOperationAction(ISD::SETCC, MVT::f64, Expand); 182 183 // Sparc doesn't have BRCOND either, it has BR_CC. 184 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 185 setOperationAction(ISD::BRIND, MVT::Other, Expand); 186 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 187 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 188 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 189 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 190 191 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 192 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 193 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 194 195 // SPARC has no intrinsics for these particular operations. 196 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 197 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 198 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 199 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 200 201 setOperationAction(ISD::FSIN , MVT::f64, Expand); 202 setOperationAction(ISD::FCOS , MVT::f64, Expand); 203 setOperationAction(ISD::FREM , MVT::f64, Expand); 204 setOperationAction(ISD::FSIN , MVT::f32, Expand); 205 setOperationAction(ISD::FCOS , MVT::f32, Expand); 206 setOperationAction(ISD::FREM , MVT::f32, Expand); 207 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 208 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 209 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 210 setOperationAction(ISD::ROTL , MVT::i32, Expand); 211 setOperationAction(ISD::ROTR , MVT::i32, Expand); 212 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 213 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 214 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 215 setOperationAction(ISD::FPOW , MVT::f64, Expand); 216 setOperationAction(ISD::FPOW , MVT::f32, Expand); 217 218 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 219 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 220 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 221 222 // FIXME: Sparc provides these multiplies, but we don't have them yet. 223 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 224 225 // We don't have line number support yet. 226 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 227 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 228 setOperationAction(ISD::LABEL, MVT::Other, Expand); 229 230 // RET must be custom lowered, to meet ABI requirements 231 setOperationAction(ISD::RET , MVT::Other, Custom); 232 233 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 234 setOperationAction(ISD::VASTART , MVT::Other, Custom); 235 // VAARG needs to be lowered to not do unaligned accesses for doubles. 236 setOperationAction(ISD::VAARG , MVT::Other, Custom); 237 238 // Use the default implementation. 239 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 240 setOperationAction(ISD::VAEND , MVT::Other, Expand); 241 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 242 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 243 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 244 245 // No debug info support yet. 246 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 247 setOperationAction(ISD::LABEL, MVT::Other, Expand); 248 setOperationAction(ISD::DECLARE, MVT::Other, Expand); 249 250 setStackPointerRegisterToSaveRestore(SP::O6); 251 252 if (TM.getSubtarget<SparcSubtarget>().isV9()) 253 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 254 255 computeRegisterProperties(); 256} 257 258const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 259 switch (Opcode) { 260 default: return 0; 261 case SPISD::CMPICC: return "SPISD::CMPICC"; 262 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 263 case SPISD::BRICC: return "SPISD::BRICC"; 264 case SPISD::BRFCC: return "SPISD::BRFCC"; 265 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 266 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 267 case SPISD::Hi: return "SPISD::Hi"; 268 case SPISD::Lo: return "SPISD::Lo"; 269 case SPISD::FTOI: return "SPISD::FTOI"; 270 case SPISD::ITOF: return "SPISD::ITOF"; 271 case SPISD::CALL: return "SPISD::CALL"; 272 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 273 } 274} 275 276/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 277/// be zero. Op is expected to be a target specific node. Used by DAG 278/// combiner. 279void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 280 const APInt &Mask, 281 APInt &KnownZero, 282 APInt &KnownOne, 283 const SelectionDAG &DAG, 284 unsigned Depth) const { 285 APInt KnownZero2, KnownOne2; 286 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 287 288 switch (Op.getOpcode()) { 289 default: break; 290 case SPISD::SELECT_ICC: 291 case SPISD::SELECT_FCC: 292 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 293 Depth+1); 294 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 295 Depth+1); 296 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 297 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 298 299 // Only known if known in both the LHS and RHS. 300 KnownOne &= KnownOne2; 301 KnownZero &= KnownZero2; 302 break; 303 } 304} 305 306/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 307/// either one or two GPRs, including FP values. TODO: we should pass FP values 308/// in FP registers for fastcc functions. 309std::vector<SDOperand> 310SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 311 MachineFunction &MF = DAG.getMachineFunction(); 312 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 313 std::vector<SDOperand> ArgValues; 314 315 static const unsigned ArgRegs[] = { 316 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 317 }; 318 319 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 320 unsigned ArgOffset = 68; 321 322 SDOperand Root = DAG.getRoot(); 323 std::vector<SDOperand> OutChains; 324 325 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 326 MVT::ValueType ObjectVT = getValueType(I->getType()); 327 328 switch (ObjectVT) { 329 default: assert(0 && "Unhandled argument type!"); 330 case MVT::i1: 331 case MVT::i8: 332 case MVT::i16: 333 case MVT::i32: 334 if (I->use_empty()) { // Argument is dead. 335 if (CurArgReg < ArgRegEnd) ++CurArgReg; 336 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 337 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 338 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 339 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 340 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 341 if (ObjectVT != MVT::i32) { 342 unsigned AssertOp = ISD::AssertSext; 343 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 344 DAG.getValueType(ObjectVT)); 345 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 346 } 347 ArgValues.push_back(Arg); 348 } else { 349 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 350 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 351 SDOperand Load; 352 if (ObjectVT == MVT::i32) { 353 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 354 } else { 355 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 356 357 // Sparc is big endian, so add an offset based on the ObjectVT. 358 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 359 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 360 DAG.getConstant(Offset, MVT::i32)); 361 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 362 NULL, 0, ObjectVT); 363 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 364 } 365 ArgValues.push_back(Load); 366 } 367 368 ArgOffset += 4; 369 break; 370 case MVT::f32: 371 if (I->use_empty()) { // Argument is dead. 372 if (CurArgReg < ArgRegEnd) ++CurArgReg; 373 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 374 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 375 // FP value is passed in an integer register. 376 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 377 MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); 378 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 379 380 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 381 ArgValues.push_back(Arg); 382 } else { 383 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 384 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 385 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); 386 ArgValues.push_back(Load); 387 } 388 ArgOffset += 4; 389 break; 390 391 case MVT::i64: 392 case MVT::f64: 393 if (I->use_empty()) { // Argument is dead. 394 if (CurArgReg < ArgRegEnd) ++CurArgReg; 395 if (CurArgReg < ArgRegEnd) ++CurArgReg; 396 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 397 } else if (/* FIXME: Apparently this isn't safe?? */ 398 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 399 ((CurArgReg-ArgRegs) & 1) == 0) { 400 // If this is a double argument and the whole thing lives on the stack, 401 // and the argument is aligned, load the double straight from the stack. 402 // We can't do a load in cases like void foo([6ints], int,double), 403 // because the double wouldn't be aligned! 404 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 405 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 406 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); 407 } else { 408 SDOperand HiVal; 409 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 410 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 411 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); 412 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 413 } else { 414 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 415 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 416 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 417 } 418 419 SDOperand LoVal; 420 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 421 unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 422 MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); 423 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 424 } else { 425 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 426 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 427 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 428 } 429 430 // Compose the two halves together into an i64 unit. 431 SDOperand WholeValue = 432 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 433 434 // If we want a double, do a bit convert. 435 if (ObjectVT == MVT::f64) 436 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 437 438 ArgValues.push_back(WholeValue); 439 } 440 ArgOffset += 8; 441 break; 442 } 443 } 444 445 // Store remaining ArgRegs to the stack if this is a varargs function. 446 if (F.getFunctionType()->isVarArg()) { 447 // Remember the vararg offset for the va_start implementation. 448 VarArgsFrameOffset = ArgOffset; 449 450 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 451 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 452 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 453 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 454 455 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 456 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 457 458 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); 459 ArgOffset += 4; 460 } 461 } 462 463 if (!OutChains.empty()) 464 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 465 &OutChains[0], OutChains.size())); 466 467 // Finally, inform the code generator which regs we return values in. 468 switch (getValueType(F.getReturnType())) { 469 default: assert(0 && "Unknown type!"); 470 case MVT::isVoid: break; 471 case MVT::i1: 472 case MVT::i8: 473 case MVT::i16: 474 case MVT::i32: 475 MF.getRegInfo().addLiveOut(SP::I0); 476 break; 477 case MVT::i64: 478 MF.getRegInfo().addLiveOut(SP::I0); 479 MF.getRegInfo().addLiveOut(SP::I1); 480 break; 481 case MVT::f32: 482 MF.getRegInfo().addLiveOut(SP::F0); 483 break; 484 case MVT::f64: 485 MF.getRegInfo().addLiveOut(SP::D0); 486 break; 487 } 488 489 return ArgValues; 490} 491 492std::pair<SDOperand, SDOperand> 493SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 494 bool RetSExt, bool RetZExt, bool isVarArg, 495 unsigned CC, bool isTailCall, SDOperand Callee, 496 ArgListTy &Args, SelectionDAG &DAG) { 497 // Count the size of the outgoing arguments. 498 unsigned ArgsSize = 0; 499 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 500 switch (getValueType(Args[i].Ty)) { 501 default: assert(0 && "Unknown value type!"); 502 case MVT::i1: 503 case MVT::i8: 504 case MVT::i16: 505 case MVT::i32: 506 case MVT::f32: 507 ArgsSize += 4; 508 break; 509 case MVT::i64: 510 case MVT::f64: 511 ArgsSize += 8; 512 break; 513 } 514 } 515 if (ArgsSize > 4*6) 516 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 517 else 518 ArgsSize = 0; 519 520 // Keep stack frames 8-byte aligned. 521 ArgsSize = (ArgsSize+7) & ~7; 522 523 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 524 525 SDOperand StackPtr; 526 std::vector<SDOperand> Stores; 527 std::vector<SDOperand> RegValuesToPass; 528 unsigned ArgOffset = 68; 529 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 530 SDOperand Val = Args[i].Node; 531 MVT::ValueType ObjectVT = Val.getValueType(); 532 SDOperand ValToStore(0, 0); 533 unsigned ObjSize; 534 switch (ObjectVT) { 535 default: assert(0 && "Unhandled argument type!"); 536 case MVT::i1: 537 case MVT::i8: 538 case MVT::i16: { 539 // Promote the integer to 32-bits. If the input type is signed, use a 540 // sign extend, otherwise use a zero extend. 541 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 542 if (Args[i].isSExt) 543 ExtendKind = ISD::SIGN_EXTEND; 544 else if (Args[i].isZExt) 545 ExtendKind = ISD::ZERO_EXTEND; 546 Val = DAG.getNode(ExtendKind, MVT::i32, Val); 547 // FALL THROUGH 548 } 549 case MVT::i32: 550 ObjSize = 4; 551 552 if (RegValuesToPass.size() >= 6) { 553 ValToStore = Val; 554 } else { 555 RegValuesToPass.push_back(Val); 556 } 557 break; 558 case MVT::f32: 559 ObjSize = 4; 560 if (RegValuesToPass.size() >= 6) { 561 ValToStore = Val; 562 } else { 563 // Convert this to a FP value in an int reg. 564 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 565 RegValuesToPass.push_back(Val); 566 } 567 break; 568 case MVT::f64: 569 ObjSize = 8; 570 // If we can store this directly into the outgoing slot, do so. We can 571 // do this when all ArgRegs are used and if the outgoing slot is aligned. 572 // FIXME: McGill/misr fails with this. 573 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 574 ValToStore = Val; 575 break; 576 } 577 578 // Otherwise, convert this to a FP value in int regs. 579 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 580 // FALL THROUGH 581 case MVT::i64: 582 ObjSize = 8; 583 if (RegValuesToPass.size() >= 6) { 584 ValToStore = Val; // Whole thing is passed in memory. 585 break; 586 } 587 588 // Split the value into top and bottom part. Top part goes in a reg. 589 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 590 DAG.getConstant(1, MVT::i32)); 591 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 592 DAG.getConstant(0, MVT::i32)); 593 RegValuesToPass.push_back(Hi); 594 595 if (RegValuesToPass.size() >= 6) { 596 ValToStore = Lo; 597 ArgOffset += 4; 598 ObjSize = 4; 599 } else { 600 RegValuesToPass.push_back(Lo); 601 } 602 break; 603 } 604 605 if (ValToStore.Val) { 606 if (!StackPtr.Val) { 607 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 608 } 609 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 610 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 611 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); 612 } 613 ArgOffset += ObjSize; 614 } 615 616 // Emit all stores, make sure the occur before any copies into physregs. 617 if (!Stores.empty()) 618 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); 619 620 static const unsigned ArgRegs[] = { 621 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 622 }; 623 624 // Build a sequence of copy-to-reg nodes chained together with token chain 625 // and flag operands which copy the outgoing args into O[0-5]. 626 SDOperand InFlag; 627 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 628 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 629 InFlag = Chain.getValue(1); 630 } 631 632 // If the callee is a GlobalAddress node (quite common, every direct call is) 633 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 634 // Likewise ExternalSymbol -> TargetExternalSymbol. 635 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 636 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 637 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 638 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 639 640 std::vector<MVT::ValueType> NodeTys; 641 NodeTys.push_back(MVT::Other); // Returns a chain 642 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 643 SDOperand Ops[] = { Chain, Callee, InFlag }; 644 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); 645 InFlag = Chain.getValue(1); 646 647 MVT::ValueType RetTyVT = getValueType(RetTy); 648 SDOperand RetVal; 649 if (RetTyVT != MVT::isVoid) { 650 switch (RetTyVT) { 651 default: assert(0 && "Unknown value type to return!"); 652 case MVT::i1: 653 case MVT::i8: 654 case MVT::i16: { 655 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 656 Chain = RetVal.getValue(1); 657 658 // Add a note to keep track of whether it is sign or zero extended. 659 ISD::NodeType AssertKind = ISD::DELETED_NODE; 660 if (RetSExt) 661 AssertKind = ISD::AssertSext; 662 else if (RetZExt) 663 AssertKind = ISD::AssertZext; 664 665 if (AssertKind != ISD::DELETED_NODE) 666 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal, 667 DAG.getValueType(RetTyVT)); 668 669 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 670 break; 671 } 672 case MVT::i32: 673 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 674 Chain = RetVal.getValue(1); 675 break; 676 case MVT::f32: 677 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 678 Chain = RetVal.getValue(1); 679 break; 680 case MVT::f64: 681 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 682 Chain = RetVal.getValue(1); 683 break; 684 case MVT::i64: 685 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 686 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 687 Lo.getValue(2)); 688 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 689 Chain = Hi.getValue(1); 690 break; 691 } 692 } 693 694 Chain = DAG.getCALLSEQ_END(Chain, 695 DAG.getConstant(ArgsSize, getPointerTy()), 696 DAG.getConstant(0, getPointerTy()), 697 SDOperand()); 698 return std::make_pair(RetVal, Chain); 699} 700 701// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 702// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 703static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 704 ISD::CondCode CC, unsigned &SPCC) { 705 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 706 CC == ISD::SETNE && 707 ((LHS.getOpcode() == SPISD::SELECT_ICC && 708 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 709 (LHS.getOpcode() == SPISD::SELECT_FCC && 710 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 711 isa<ConstantSDNode>(LHS.getOperand(0)) && 712 isa<ConstantSDNode>(LHS.getOperand(1)) && 713 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 714 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 715 SDOperand CMPCC = LHS.getOperand(3); 716 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 717 LHS = CMPCC.getOperand(0); 718 RHS = CMPCC.getOperand(1); 719 } 720} 721 722 723SDOperand SparcTargetLowering:: 724LowerOperation(SDOperand Op, SelectionDAG &DAG) { 725 switch (Op.getOpcode()) { 726 default: assert(0 && "Should not custom lower this!"); 727 case ISD::GlobalTLSAddress: 728 assert(0 && "TLS not implemented for Sparc."); 729 case ISD::GlobalAddress: { 730 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 731 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 732 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 733 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 734 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 735 } 736 case ISD::ConstantPool: { 737 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal(); 738 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 739 cast<ConstantPoolSDNode>(Op)->getAlignment()); 740 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 741 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 742 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 743 } 744 case ISD::FP_TO_SINT: 745 // Convert the fp value to integer in an FP register. 746 assert(Op.getValueType() == MVT::i32); 747 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 748 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 749 case ISD::SINT_TO_FP: { 750 assert(Op.getOperand(0).getValueType() == MVT::i32); 751 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 752 // Convert the int value to FP in an FP register. 753 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 754 } 755 case ISD::BR_CC: { 756 SDOperand Chain = Op.getOperand(0); 757 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 758 SDOperand LHS = Op.getOperand(2); 759 SDOperand RHS = Op.getOperand(3); 760 SDOperand Dest = Op.getOperand(4); 761 unsigned Opc, SPCC = ~0U; 762 763 // If this is a br_cc of a "setcc", and if the setcc got lowered into 764 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 765 LookThroughSetCC(LHS, RHS, CC, SPCC); 766 767 // Get the condition flag. 768 SDOperand CompareFlag; 769 if (LHS.getValueType() == MVT::i32) { 770 std::vector<MVT::ValueType> VTs; 771 VTs.push_back(MVT::i32); 772 VTs.push_back(MVT::Flag); 773 SDOperand Ops[2] = { LHS, RHS }; 774 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 775 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 776 Opc = SPISD::BRICC; 777 } else { 778 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 779 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 780 Opc = SPISD::BRFCC; 781 } 782 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 783 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 784 } 785 case ISD::SELECT_CC: { 786 SDOperand LHS = Op.getOperand(0); 787 SDOperand RHS = Op.getOperand(1); 788 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 789 SDOperand TrueVal = Op.getOperand(2); 790 SDOperand FalseVal = Op.getOperand(3); 791 unsigned Opc, SPCC = ~0U; 792 793 // If this is a select_cc of a "setcc", and if the setcc got lowered into 794 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 795 LookThroughSetCC(LHS, RHS, CC, SPCC); 796 797 SDOperand CompareFlag; 798 if (LHS.getValueType() == MVT::i32) { 799 std::vector<MVT::ValueType> VTs; 800 VTs.push_back(LHS.getValueType()); // subcc returns a value 801 VTs.push_back(MVT::Flag); 802 SDOperand Ops[2] = { LHS, RHS }; 803 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 804 Opc = SPISD::SELECT_ICC; 805 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 806 } else { 807 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 808 Opc = SPISD::SELECT_FCC; 809 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 810 } 811 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 812 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 813 } 814 case ISD::VASTART: { 815 // vastart just stores the address of the VarArgsFrameIndex slot into the 816 // memory location argument. 817 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 818 DAG.getRegister(SP::I6, MVT::i32), 819 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 820 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 821 return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0); 822 } 823 case ISD::VAARG: { 824 SDNode *Node = Op.Val; 825 MVT::ValueType VT = Node->getValueType(0); 826 SDOperand InChain = Node->getOperand(0); 827 SDOperand VAListPtr = Node->getOperand(1); 828 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 829 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, SV, 0); 830 // Increment the pointer, VAList, to the next vaarg 831 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 832 DAG.getConstant(MVT::getSizeInBits(VT)/8, 833 getPointerTy())); 834 // Store the incremented VAList to the legalized pointer 835 InChain = DAG.getStore(VAList.getValue(1), NextPtr, 836 VAListPtr, SV, 0); 837 // Load the actual argument out of the pointer VAList, unless this is an 838 // f64 load. 839 if (VT != MVT::f64) { 840 return DAG.getLoad(VT, InChain, VAList, NULL, 0); 841 } else { 842 // Otherwise, load it as i64, then do a bitconvert. 843 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); 844 std::vector<MVT::ValueType> Tys; 845 Tys.push_back(MVT::f64); 846 Tys.push_back(MVT::Other); 847 // Bit-Convert the value to f64. 848 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 849 V.getValue(1) }; 850 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 851 } 852 } 853 case ISD::DYNAMIC_STACKALLOC: { 854 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 855 SDOperand Size = Op.getOperand(1); // Legalize the size. 856 857 unsigned SPReg = SP::O6; 858 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 859 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 860 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 861 862 // The resultant pointer is actually 16 words from the bottom of the stack, 863 // to provide a register spill area. 864 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 865 DAG.getConstant(96, MVT::i32)); 866 std::vector<MVT::ValueType> Tys; 867 Tys.push_back(MVT::i32); 868 Tys.push_back(MVT::Other); 869 SDOperand Ops[2] = { NewVal, Chain }; 870 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 871 } 872 case ISD::RET: { 873 SDOperand Copy; 874 875 switch(Op.getNumOperands()) { 876 default: 877 assert(0 && "Do not know how to return this many arguments!"); 878 abort(); 879 case 1: 880 return SDOperand(); // ret void is legal 881 case 3: { 882 unsigned ArgReg; 883 switch(Op.getOperand(1).getValueType()) { 884 default: assert(0 && "Unknown type to return!"); 885 case MVT::i32: ArgReg = SP::I0; break; 886 case MVT::f32: ArgReg = SP::F0; break; 887 case MVT::f64: ArgReg = SP::D0; break; 888 } 889 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 890 SDOperand()); 891 break; 892 } 893 case 5: 894 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 895 SDOperand()); 896 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 897 break; 898 } 899 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 900 } 901 // Frame & Return address. Currently unimplemented 902 case ISD::RETURNADDR: break; 903 case ISD::FRAMEADDR: break; 904 } 905 return SDOperand(); 906} 907 908MachineBasicBlock * 909SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 910 MachineBasicBlock *BB) { 911 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 912 unsigned BROpcode; 913 unsigned CC; 914 // Figure out the conditional branch opcode to use for this select_cc. 915 switch (MI->getOpcode()) { 916 default: assert(0 && "Unknown SELECT_CC!"); 917 case SP::SELECT_CC_Int_ICC: 918 case SP::SELECT_CC_FP_ICC: 919 case SP::SELECT_CC_DFP_ICC: 920 BROpcode = SP::BCOND; 921 break; 922 case SP::SELECT_CC_Int_FCC: 923 case SP::SELECT_CC_FP_FCC: 924 case SP::SELECT_CC_DFP_FCC: 925 BROpcode = SP::FBCOND; 926 break; 927 } 928 929 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 930 931 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 932 // control-flow pattern. The incoming instruction knows the destination vreg 933 // to set, the condition code register to branch on, the true/false values to 934 // select between, and a branch opcode to use. 935 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 936 ilist<MachineBasicBlock>::iterator It = BB; 937 ++It; 938 939 // thisMBB: 940 // ... 941 // TrueVal = ... 942 // [f]bCC copy1MBB 943 // fallthrough --> copy0MBB 944 MachineBasicBlock *thisMBB = BB; 945 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 946 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 947 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 948 MachineFunction *F = BB->getParent(); 949 F->getBasicBlockList().insert(It, copy0MBB); 950 F->getBasicBlockList().insert(It, sinkMBB); 951 // Update machine-CFG edges by first adding all successors of the current 952 // block to the new block which will contain the Phi node for the select. 953 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 954 e = BB->succ_end(); i != e; ++i) 955 sinkMBB->addSuccessor(*i); 956 // Next, remove all successors of the current block, and add the true 957 // and fallthrough blocks as its successors. 958 while(!BB->succ_empty()) 959 BB->removeSuccessor(BB->succ_begin()); 960 BB->addSuccessor(copy0MBB); 961 BB->addSuccessor(sinkMBB); 962 963 // copy0MBB: 964 // %FalseValue = ... 965 // # fallthrough to sinkMBB 966 BB = copy0MBB; 967 968 // Update machine-CFG edges 969 BB->addSuccessor(sinkMBB); 970 971 // sinkMBB: 972 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 973 // ... 974 BB = sinkMBB; 975 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) 976 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 977 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 978 979 delete MI; // The pseudo instruction is gone now. 980 return BB; 981} 982 983//===----------------------------------------------------------------------===// 984// Instruction Selector Implementation 985//===----------------------------------------------------------------------===// 986 987//===--------------------------------------------------------------------===// 988/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 989/// instructions for SelectionDAG operations. 990/// 991namespace { 992class SparcDAGToDAGISel : public SelectionDAGISel { 993 SparcTargetLowering Lowering; 994 995 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 996 /// make the right decision when generating code for different targets. 997 const SparcSubtarget &Subtarget; 998public: 999 SparcDAGToDAGISel(TargetMachine &TM) 1000 : SelectionDAGISel(Lowering), Lowering(TM), 1001 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 1002 } 1003 1004 SDNode *Select(SDOperand Op); 1005 1006 // Complex Pattern Selectors. 1007 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2); 1008 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base, 1009 SDOperand &Offset); 1010 1011 /// InstructionSelectBasicBlock - This callback is invoked by 1012 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 1013 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 1014 1015 virtual const char *getPassName() const { 1016 return "SPARC DAG->DAG Pattern Instruction Selection"; 1017 } 1018 1019 // Include the pieces autogenerated from the target description. 1020#include "SparcGenDAGISel.inc" 1021}; 1022} // end anonymous namespace 1023 1024/// InstructionSelectBasicBlock - This callback is invoked by 1025/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 1026void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 1027 DEBUG(BB->dump()); 1028 1029 // Select target instructions for the DAG. 1030 DAG.setRoot(SelectRoot(DAG.getRoot())); 1031 DAG.RemoveDeadNodes(); 1032 1033 // Emit machine code to BB. 1034 ScheduleAndEmitDAG(DAG); 1035} 1036 1037bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr, 1038 SDOperand &Base, SDOperand &Offset) { 1039 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 1040 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1041 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1042 return true; 1043 } 1044 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1045 Addr.getOpcode() == ISD::TargetGlobalAddress) 1046 return false; // direct calls. 1047 1048 if (Addr.getOpcode() == ISD::ADD) { 1049 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 1050 if (Predicate_simm13(CN)) { 1051 if (FrameIndexSDNode *FIN = 1052 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 1053 // Constant offset from frame ref. 1054 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1055 } else { 1056 Base = Addr.getOperand(0); 1057 } 1058 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 1059 return true; 1060 } 1061 } 1062 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 1063 Base = Addr.getOperand(1); 1064 Offset = Addr.getOperand(0).getOperand(0); 1065 return true; 1066 } 1067 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 1068 Base = Addr.getOperand(0); 1069 Offset = Addr.getOperand(1).getOperand(0); 1070 return true; 1071 } 1072 } 1073 Base = Addr; 1074 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1075 return true; 1076} 1077 1078bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr, 1079 SDOperand &R1, SDOperand &R2) { 1080 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1081 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1082 Addr.getOpcode() == ISD::TargetGlobalAddress) 1083 return false; // direct calls. 1084 1085 if (Addr.getOpcode() == ISD::ADD) { 1086 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1087 Predicate_simm13(Addr.getOperand(1).Val)) 1088 return false; // Let the reg+imm pattern catch this! 1089 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1090 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1091 return false; // Let the reg+imm pattern catch this! 1092 R1 = Addr.getOperand(0); 1093 R2 = Addr.getOperand(1); 1094 return true; 1095 } 1096 1097 R1 = Addr; 1098 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1099 return true; 1100} 1101 1102SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { 1103 SDNode *N = Op.Val; 1104 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1105 N->getOpcode() < SPISD::FIRST_NUMBER) 1106 return NULL; // Already selected. 1107 1108 switch (N->getOpcode()) { 1109 default: break; 1110 case ISD::SDIV: 1111 case ISD::UDIV: { 1112 // FIXME: should use a custom expander to expose the SRA to the dag. 1113 SDOperand DivLHS = N->getOperand(0); 1114 SDOperand DivRHS = N->getOperand(1); 1115 AddToISelQueue(DivLHS); 1116 AddToISelQueue(DivRHS); 1117 1118 // Set the Y register to the high-part. 1119 SDOperand TopPart; 1120 if (N->getOpcode() == ISD::SDIV) { 1121 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1122 CurDAG->getTargetConstant(31, MVT::i32)), 0); 1123 } else { 1124 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1125 } 1126 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1127 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 1128 1129 // FIXME: Handle div by immediate. 1130 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1131 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 1132 TopPart); 1133 } 1134 case ISD::MULHU: 1135 case ISD::MULHS: { 1136 // FIXME: Handle mul by immediate. 1137 SDOperand MulLHS = N->getOperand(0); 1138 SDOperand MulRHS = N->getOperand(1); 1139 AddToISelQueue(MulLHS); 1140 AddToISelQueue(MulRHS); 1141 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1142 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1143 MulLHS, MulRHS); 1144 // The high part is in the Y register. 1145 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); 1146 return NULL; 1147 } 1148 } 1149 1150 return SelectCode(Op); 1151} 1152 1153 1154/// createSparcISelDag - This pass converts a legalized DAG into a 1155/// SPARC-specific DAG, ready for instruction scheduling. 1156/// 1157FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1158 return new SparcDAGToDAGISel(TM); 1159} 1160