SparcISelDAGToDAG.cpp revision 6c18b10ad4873ad7e1b1c1d589bcf844c46f4120 
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the V8 target
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8TargetMachine.h"
16#include "llvm/CodeGen/SelectionDAG.h"
17#include "llvm/CodeGen/SelectionDAGISel.h"
18#include "llvm/Target/TargetLowering.h"
19#include "llvm/Support/Debug.h"
20#include <iostream>
21using namespace llvm;
22
23//===----------------------------------------------------------------------===//
24// TargetLowering Implementation
25//===----------------------------------------------------------------------===//
26
27namespace {
28  class SparcV8TargetLowering : public TargetLowering {
29  public:
30    SparcV8TargetLowering(TargetMachine &TM);
31
32    virtual std::vector<SDOperand>
33      LowerArguments(Function &F, SelectionDAG &DAG);
34    virtual std::pair<SDOperand, SDOperand>
35      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
36                  unsigned CC,
37                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
38                  SelectionDAG &DAG);
39
40    virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
41                                    SelectionDAG &DAG);
42    virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
43                                   Value *VAListV, SelectionDAG &DAG);
44    virtual std::pair<SDOperand,SDOperand>
45      LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
46                 const Type *ArgTy, SelectionDAG &DAG);
47    virtual std::pair<SDOperand, SDOperand>
48      LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
49                              SelectionDAG &DAG);
50  };
51}
52
53SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
54  : TargetLowering(TM) {
55
56  // Set up the register classes.
57  addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
58  addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
59  addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
60
61  computeRegisterProperties();
62}
63
64std::vector<SDOperand>
65SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
66  assert(0 && "Unimp");
67  abort();
68}
69
70std::pair<SDOperand, SDOperand>
71SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
72                                   bool isVarArg, unsigned CC,
73                                   bool isTailCall, SDOperand Callee,
74                                   ArgListTy &Args, SelectionDAG &DAG) {
75  assert(0 && "Unimp");
76  abort();
77}
78
79SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
80                                               SelectionDAG &DAG) {
81  assert(0 && "Unimp");
82  abort();
83}
84
85SDOperand SparcV8TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
86                                              Value *VAListV, SelectionDAG &DAG) {
87  assert(0 && "Unimp");
88  abort();
89}
90
91std::pair<SDOperand,SDOperand>
92SparcV8TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
93                                  const Type *ArgTy, SelectionDAG &DAG) {
94  assert(0 && "Unimp");
95  abort();
96}
97
98std::pair<SDOperand, SDOperand>
99SparcV8TargetLowering::LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
100                                               SelectionDAG &DAG) {
101  assert(0 && "Unimp");
102  abort();
103}
104
105//===----------------------------------------------------------------------===//
106// Instruction Selector Implementation
107//===----------------------------------------------------------------------===//
108
109//===--------------------------------------------------------------------===//
110/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
111/// instructions for SelectionDAG operations.
112///
113namespace {
114class SparcV8DAGToDAGISel : public SelectionDAGISel {
115  SparcV8TargetLowering V8Lowering;
116public:
117  SparcV8DAGToDAGISel(TargetMachine &TM)
118    : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
119
120  SDOperand Select(SDOperand Op);
121
122  /// InstructionSelectBasicBlock - This callback is invoked by
123  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
124  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
125
126  virtual const char *getPassName() const {
127    return "PowerPC DAG->DAG Pattern Instruction Selection";
128  }
129
130  // Include the pieces autogenerated from the target description.
131#include "SparcV8GenDAGISel.inc"
132};
133}  // end anonymous namespace
134
135/// InstructionSelectBasicBlock - This callback is invoked by
136/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
137void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
138  DEBUG(BB->dump());
139
140  // Select target instructions for the DAG.
141  DAG.setRoot(Select(DAG.getRoot()));
142  CodeGenMap.clear();
143  DAG.RemoveDeadNodes();
144
145  // Emit machine code to BB.
146  ScheduleAndEmitDAG(DAG);
147}
148
149
150SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
151  SDNode *N = Op.Val;
152  if (N->getOpcode() >= ISD::BUILTIN_OP_END/* &&
153      N->getOpcode() < V8ISD::FIRST_NUMBER*/)
154    return Op;   // Already selected.
155                 // If this has already been converted, use it.
156  std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
157  if (CGMI != CodeGenMap.end()) return CGMI->second;
158
159  switch (N->getOpcode()) {
160  default: break;
161  }
162
163  return SelectCode(Op);
164}
165
166
167/// createPPCISelDag - This pass converts a legalized DAG into a
168/// PowerPC-specific DAG, ready for instruction scheduling.
169///
170FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
171  return new SparcV8DAGToDAGISel(TM);
172}
173