SparcISelDAGToDAG.cpp revision 7c423b4df11d64593c450df9f645a27e509aae14
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 RET_FLAG, // Return with a flag operand. 50 }; 51} 52 53namespace { 54 class SparcV8TargetLowering : public TargetLowering { 55 int VarArgsFrameOffset; // Frame offset to start of varargs area. 56 public: 57 SparcV8TargetLowering(TargetMachine &TM); 58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 59 virtual std::vector<SDOperand> 60 LowerArguments(Function &F, SelectionDAG &DAG); 61 virtual std::pair<SDOperand, SDOperand> 62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 63 unsigned CC, 64 bool isTailCall, SDOperand Callee, ArgListTy &Args, 65 SelectionDAG &DAG); 66 67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, 68 SelectionDAG &DAG); 69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, 70 Value *VAListV, SelectionDAG &DAG); 71 virtual std::pair<SDOperand,SDOperand> 72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 73 const Type *ArgTy, SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 }; 80} 81 82SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 83 : TargetLowering(TM) { 84 85 // Set up the register classes. 86 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 87 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 88 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 89 90 // Custom legalize GlobalAddress nodes into LO/HI parts. 91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 92 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 93 94 // Sparc doesn't have sext_inreg, replace them with shl/sra 95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 98 99 // Sparc has no REM operation. 100 setOperationAction(ISD::UREM, MVT::i32, Expand); 101 setOperationAction(ISD::SREM, MVT::i32, Expand); 102 103 // Custom expand fp<->sint 104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 105 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 106 107 // Expand fp<->uint 108 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 109 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 110 111 // Turn FP extload into load/fextend 112 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 113 114 // Sparc has no select or setcc: expand to SELECT_CC. 115 setOperationAction(ISD::SELECT, MVT::i32, Expand); 116 setOperationAction(ISD::SELECT, MVT::f32, Expand); 117 setOperationAction(ISD::SELECT, MVT::f64, Expand); 118 setOperationAction(ISD::SETCC, MVT::i32, Expand); 119 setOperationAction(ISD::SETCC, MVT::f32, Expand); 120 setOperationAction(ISD::SETCC, MVT::f64, Expand); 121 122 // Sparc doesn't have BRCOND either, it has BR_CC. 123 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 124 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 125 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 126 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 127 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 128 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 129 130 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 131 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 132 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 133 134 // V8 has no intrinsics for these particular operations. 135 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 136 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 137 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 138 139 setOperationAction(ISD::FSIN , MVT::f64, Expand); 140 setOperationAction(ISD::FCOS , MVT::f64, Expand); 141 setOperationAction(ISD::FSIN , MVT::f32, Expand); 142 setOperationAction(ISD::FCOS , MVT::f32, Expand); 143 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 144 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 145 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 146 147 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 148 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 149 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 150 computeRegisterProperties(); 151} 152 153/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 154/// either one or two GPRs, including FP values. TODO: we should pass FP values 155/// in FP registers for fastcc functions. 156std::vector<SDOperand> 157SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 158 MachineFunction &MF = DAG.getMachineFunction(); 159 SSARegMap *RegMap = MF.getSSARegMap(); 160 std::vector<SDOperand> ArgValues; 161 162 static const unsigned ArgRegs[] = { 163 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 164 }; 165 166 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 167 unsigned ArgOffset = 68; 168 169 SDOperand Root = DAG.getRoot(); 170 std::vector<SDOperand> OutChains; 171 172 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 173 MVT::ValueType ObjectVT = getValueType(I->getType()); 174 175 switch (ObjectVT) { 176 default: assert(0 && "Unhandled argument type!"); 177 case MVT::i1: 178 case MVT::i8: 179 case MVT::i16: 180 case MVT::i32: 181 if (I->use_empty()) { // Argument is dead. 182 if (CurArgReg < ArgRegEnd) ++CurArgReg; 183 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 184 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 185 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 186 MF.addLiveIn(*CurArgReg++, VReg); 187 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 188 if (ObjectVT != MVT::i32) { 189 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 190 : ISD::AssertZext; 191 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 192 DAG.getValueType(ObjectVT)); 193 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 194 } 195 ArgValues.push_back(Arg); 196 } else { 197 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 198 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 199 SDOperand Load; 200 if (ObjectVT == MVT::i32) { 201 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 202 } else { 203 unsigned LoadOp = 204 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 205 206 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 207 DAG.getSrcValue(0), ObjectVT); 208 } 209 ArgValues.push_back(Load); 210 } 211 212 ArgOffset += 4; 213 break; 214 case MVT::f32: 215 if (I->use_empty()) { // Argument is dead. 216 if (CurArgReg < ArgRegEnd) ++CurArgReg; 217 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 218 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 219 // FP value is passed in an integer register. 220 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 221 MF.addLiveIn(*CurArgReg++, VReg); 222 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 223 224 // We use the stack space that is already reserved for this reg. 225 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 226 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 227 228 SDOperand SV = DAG.getSrcValue(0); 229 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root, 230 Arg, FIPtr, SV); 231 ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV)); 232 } 233 ArgOffset += 4; 234 break; 235 236 case MVT::i64: 237 case MVT::f64: 238 if (I->use_empty()) { // Argument is dead. 239 if (CurArgReg < ArgRegEnd) ++CurArgReg; 240 if (CurArgReg < ArgRegEnd) ++CurArgReg; 241 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 242 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 243 ((CurArgReg-ArgRegs) & 1) == 0) { 244 // If this is a double argument and the whole thing lives on the stack, 245 // and the argument is aligned, load the double straight from the stack. 246 // We can't do a load in cases like void foo([6ints], int,double), 247 // because the double wouldn't be aligned! 248 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 249 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 250 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 251 DAG.getSrcValue(0))); 252 } else { 253 SDOperand HiVal; 254 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 255 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 256 MF.addLiveIn(*CurArgReg++, VRegHi); 257 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 258 } else { 259 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 260 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 261 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 262 } 263 264 SDOperand LoVal; 265 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 266 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 267 MF.addLiveIn(*CurArgReg++, VRegLo); 268 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 269 } else { 270 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 271 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 272 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 273 } 274 275 // Compose the two halves together into an i64 unit. 276 SDOperand WholeValue = 277 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 278 279 if (ObjectVT == MVT::i64) { 280 // If we are emitting an i64, this is what we want. 281 ArgValues.push_back(WholeValue); 282 } else { 283 assert(ObjectVT == MVT::f64); 284 // Otherwise, emit a store to the stack and reload into FPR. 285 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); 286 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 287 SDOperand SV = DAG.getSrcValue(0); 288 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root, 289 WholeValue, FIPtr, SV); 290 ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV)); 291 } 292 } 293 ArgOffset += 8; 294 break; 295 } 296 } 297 298 // Store remaining ArgRegs to the stack if this is a varargs function. 299 if (F.getFunctionType()->isVarArg()) { 300 // Remember the vararg offset for the va_start implementation. 301 VarArgsFrameOffset = ArgOffset; 302 303 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 304 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 305 MF.addLiveIn(*CurArgReg, VReg); 306 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 307 308 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 309 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 310 311 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 312 Arg, FIPtr, DAG.getSrcValue(0))); 313 ArgOffset += 4; 314 } 315 } 316 317 if (!OutChains.empty()) 318 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 319 320 // Finally, inform the code generator which regs we return values in. 321 switch (getValueType(F.getReturnType())) { 322 default: assert(0 && "Unknown type!"); 323 case MVT::isVoid: break; 324 case MVT::i1: 325 case MVT::i8: 326 case MVT::i16: 327 case MVT::i32: 328 MF.addLiveOut(V8::I0); 329 break; 330 case MVT::i64: 331 MF.addLiveOut(V8::I0); 332 MF.addLiveOut(V8::I1); 333 break; 334 case MVT::f32: 335 MF.addLiveOut(V8::F0); 336 break; 337 case MVT::f64: 338 MF.addLiveOut(V8::D0); 339 break; 340 } 341 342 return ArgValues; 343} 344 345std::pair<SDOperand, SDOperand> 346SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 347 bool isVarArg, unsigned CC, 348 bool isTailCall, SDOperand Callee, 349 ArgListTy &Args, SelectionDAG &DAG) { 350 MachineFunction &MF = DAG.getMachineFunction(); 351 // Count the size of the outgoing arguments. 352 unsigned ArgsSize = 0; 353 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 354 switch (getValueType(Args[i].second)) { 355 default: assert(0 && "Unknown value type!"); 356 case MVT::i1: 357 case MVT::i8: 358 case MVT::i16: 359 case MVT::i32: 360 case MVT::f32: 361 ArgsSize += 4; 362 break; 363 case MVT::i64: 364 case MVT::f64: 365 ArgsSize += 8; 366 break; 367 } 368 } 369 if (ArgsSize > 4*6) 370 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 371 else 372 ArgsSize = 0; 373 374 // Keep stack frames 8-byte aligned. 375 ArgsSize = (ArgsSize+7) & ~7; 376 377 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 378 DAG.getConstant(ArgsSize, getPointerTy())); 379 380 SDOperand StackPtr, NullSV; 381 std::vector<SDOperand> Stores; 382 std::vector<SDOperand> RegValuesToPass; 383 unsigned ArgOffset = 68; 384 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 385 SDOperand Val = Args[i].first; 386 MVT::ValueType ObjectVT = Val.getValueType(); 387 SDOperand ValToStore; 388 unsigned ObjSize; 389 switch (ObjectVT) { 390 default: assert(0 && "Unhandled argument type!"); 391 case MVT::i1: 392 case MVT::i8: 393 case MVT::i16: 394 // Promote the integer to 32-bits. If the input type is signed, use a 395 // sign extend, otherwise use a zero extend. 396 if (Args[i].second->isSigned()) 397 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 398 else 399 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 400 // FALL THROUGH 401 case MVT::i32: 402 ObjSize = 4; 403 404 if (RegValuesToPass.size() >= 6) { 405 ValToStore = Val; 406 } else { 407 RegValuesToPass.push_back(Val); 408 } 409 break; 410 case MVT::f32: 411 ObjSize = 4; 412 if (RegValuesToPass.size() >= 6) { 413 ValToStore = Val; 414 } else { 415 // Convert this to a FP value in an int reg. 416 int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4); 417 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 418 SDOperand SV = DAG.getSrcValue(0); 419 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 420 Val, FIPtr, SV); 421 Val = DAG.getLoad(MVT::i32, Store, FIPtr, SV); 422 RegValuesToPass.push_back(Val); 423 } 424 break; 425 case MVT::f64: { 426 ObjSize = 8; 427 // If we can store this directly into the outgoing slot, do so. We can 428 // do this when all ArgRegs are used and if the outgoing slot is aligned. 429 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 430 ValToStore = Val; 431 break; 432 } 433 434 // Otherwise, convert this to a FP value in int regs. 435 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); 436 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 437 SDOperand SV = DAG.getSrcValue(0); 438 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 439 Val, FIPtr, SV); 440 Val = DAG.getLoad(MVT::i64, Store, FIPtr, SV); 441 } 442 // FALL THROUGH 443 case MVT::i64: 444 ObjSize = 8; 445 if (RegValuesToPass.size() >= 6) { 446 ValToStore = Val; // Whole thing is passed in memory. 447 break; 448 } 449 450 // Split the value into top and bottom part. Top part goes in a reg. 451 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 452 DAG.getConstant(1, MVT::i32)); 453 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 454 DAG.getConstant(0, MVT::i32)); 455 RegValuesToPass.push_back(Hi); 456 457 if (RegValuesToPass.size() >= 6) { 458 ValToStore = Lo; 459 ArgOffset += 4; 460 ObjSize = 4; 461 } else { 462 RegValuesToPass.push_back(Lo); 463 } 464 break; 465 } 466 467 if (ValToStore.Val) { 468 if (!StackPtr.Val) { 469 StackPtr = DAG.getRegister(V8::O6, MVT::i32); 470 NullSV = DAG.getSrcValue(NULL); 471 } 472 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 473 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 474 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 475 ValToStore, PtrOff, NullSV)); 476 } 477 ArgOffset += ObjSize; 478 } 479 480 // Emit all stores, make sure the occur before any copies into physregs. 481 if (!Stores.empty()) 482 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 483 484 static const unsigned ArgRegs[] = { 485 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 486 }; 487 488 // Build a sequence of copy-to-reg nodes chained together with token chain 489 // and flag operands which copy the outgoing args into O[0-5]. 490 SDOperand InFlag; 491 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 492 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 493 InFlag = Chain.getValue(1); 494 } 495 496 std::vector<MVT::ValueType> RetVals; 497 RetVals.push_back(MVT::Other); 498 RetVals.push_back(MVT::Flag); 499 500 // If the callee is a GlobalAddress node (quite common, every direct call is) 501 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 502 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 503 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 504 505 std::vector<MVT::ValueType> NodeTys; 506 NodeTys.push_back(MVT::Other); // Returns a chain 507 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 508 if (InFlag.Val) 509 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0); 510 else 511 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0); 512 InFlag = Chain.getValue(1); 513 514 MVT::ValueType RetTyVT = getValueType(RetTy); 515 SDOperand RetVal; 516 if (RetTyVT != MVT::isVoid) { 517 switch (RetTyVT) { 518 default: assert(0 && "Unknown value type to return!"); 519 case MVT::i1: 520 case MVT::i8: 521 case MVT::i16: 522 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 523 Chain = RetVal.getValue(1); 524 525 // Add a note to keep track of whether it is sign or zero extended. 526 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 527 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 528 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 529 break; 530 case MVT::i32: 531 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 532 Chain = RetVal.getValue(1); 533 break; 534 case MVT::f32: 535 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 536 Chain = RetVal.getValue(1); 537 break; 538 case MVT::f64: 539 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 540 Chain = RetVal.getValue(1); 541 break; 542 case MVT::i64: 543 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag); 544 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 545 Lo.getValue(2)); 546 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 547 Chain = Hi.getValue(1); 548 break; 549 } 550 } 551 552 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 553 DAG.getConstant(ArgsSize, getPointerTy())); 554 555 MVT::ValueType ActualRetTyVT = RetTyVT; 556 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16) 557 ActualRetTyVT = MVT::i32; // Promote result to i32. 558 559 return std::make_pair(RetVal, Chain); 560} 561 562SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 563 SelectionDAG &DAG) { 564 SDOperand Copy; 565 switch (Op.getValueType()) { 566 default: assert(0 && "Unknown type to return!"); 567 case MVT::i32: 568 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand()); 569 break; 570 case MVT::f32: 571 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand()); 572 break; 573 case MVT::f64: 574 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand()); 575 break; 576 case MVT::i64: 577 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 578 DAG.getConstant(1, MVT::i32)); 579 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 580 DAG.getConstant(0, MVT::i32)); 581 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand()); 582 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1)); 583 break; 584 } 585 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 586} 587 588SDOperand SparcV8TargetLowering:: 589LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, 590 SelectionDAG &DAG) { 591 592 assert(0 && "Unimp"); 593 abort(); 594} 595 596std::pair<SDOperand,SDOperand> SparcV8TargetLowering:: 597LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 598 const Type *ArgTy, SelectionDAG &DAG) { 599 assert(0 && "Unimp"); 600 abort(); 601} 602 603std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 604LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 605 SelectionDAG &DAG) { 606 assert(0 && "Unimp"); 607 abort(); 608} 609 610SDOperand SparcV8TargetLowering:: 611LowerOperation(SDOperand Op, SelectionDAG &DAG) { 612 switch (Op.getOpcode()) { 613 default: assert(0 && "Should not custom lower this!"); 614 case ISD::GlobalAddress: { 615 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 616 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 617 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 618 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 619 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 620 } 621 case ISD::ConstantPool: { 622 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 623 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 624 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 625 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 626 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 627 } 628 case ISD::FP_TO_SINT: { 629 // Convert the fp value to integer in an FP register. 630 Op = DAG.getNode(V8ISD::FTOI, Op.getOperand(0).getValueType(), 631 Op.getOperand(0)); 632 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8; 633 int FrameIdx = 634 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size); 635 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 636 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 637 Op, FI, DAG.getSrcValue(0)); 638 return DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0)); 639 } 640 case ISD::SINT_TO_FP: { 641 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8; 642 int FrameIdx = 643 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size); 644 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 645 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 646 Op.getOperand(0), FI, DAG.getSrcValue(0)); 647 648 Op = DAG.getLoad(Op.getValueType(), ST, FI, DAG.getSrcValue(0)); 649 650 // Convert the int value to FP in an FP register. 651 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op); 652 } 653 case ISD::BR_CC: { 654 SDOperand Chain = Op.getOperand(0); 655 SDOperand CC = Op.getOperand(1); 656 SDOperand LHS = Op.getOperand(2); 657 SDOperand RHS = Op.getOperand(3); 658 SDOperand Dest = Op.getOperand(4); 659 660 // Get the condition flag. 661 if (LHS.getValueType() == MVT::i32) { 662 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS); 663 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 664 } else { 665 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 666 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 667 } 668 } 669 case ISD::SELECT_CC: { 670 SDOperand LHS = Op.getOperand(0); 671 SDOperand RHS = Op.getOperand(1); 672 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 673 SDOperand TrueVal = Op.getOperand(2); 674 SDOperand FalseVal = Op.getOperand(3); 675 676 unsigned Opc; 677 Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC; 678 SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS); 679 680 Opc = LHS.getValueType() == MVT::i32 ? 681 V8ISD::SELECT_ICC : V8ISD::SELECT_FCC; 682 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 683 DAG.getConstant(CC, MVT::i32), CompareFlag); 684 } 685 } 686} 687 688MachineBasicBlock * 689SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 690 MachineBasicBlock *BB) { 691 unsigned BROpcode; 692 // Figure out the conditional branch opcode to use for this select_cc. 693 switch (MI->getOpcode()) { 694 default: assert(0 && "Unknown SELECT_CC!"); 695 case V8::SELECT_CC_Int_ICC: 696 case V8::SELECT_CC_FP_ICC: 697 case V8::SELECT_CC_DFP_ICC: 698 // Integer compare. 699 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 700 default: assert(0 && "Unknown integer condition code!"); 701 case ISD::SETEQ: BROpcode = V8::BE; break; 702 case ISD::SETNE: BROpcode = V8::BNE; break; 703 case ISD::SETLT: BROpcode = V8::BL; break; 704 case ISD::SETGT: BROpcode = V8::BG; break; 705 case ISD::SETLE: BROpcode = V8::BLE; break; 706 case ISD::SETGE: BROpcode = V8::BGE; break; 707 case ISD::SETULT: BROpcode = V8::BCS; break; 708 case ISD::SETULE: BROpcode = V8::BLEU; break; 709 case ISD::SETUGT: BROpcode = V8::BGU; break; 710 case ISD::SETUGE: BROpcode = V8::BCC; break; 711 } 712 break; 713 case V8::SELECT_CC_Int_FCC: 714 case V8::SELECT_CC_FP_FCC: 715 case V8::SELECT_CC_DFP_FCC: 716 // FP compare. 717 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 718 default: assert(0 && "Unknown fp condition code!"); 719 case ISD::SETEQ: BROpcode = V8::FBE; break; 720 case ISD::SETNE: BROpcode = V8::FBNE; break; 721 case ISD::SETLT: BROpcode = V8::FBL; break; 722 case ISD::SETGT: BROpcode = V8::FBG; break; 723 case ISD::SETLE: BROpcode = V8::FBLE; break; 724 case ISD::SETGE: BROpcode = V8::FBGE; break; 725 case ISD::SETULT: BROpcode = V8::FBUL; break; 726 case ISD::SETULE: BROpcode = V8::FBULE; break; 727 case ISD::SETUGT: BROpcode = V8::FBUG; break; 728 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 729 case ISD::SETUO: BROpcode = V8::FBU; break; 730 case ISD::SETO: BROpcode = V8::FBO; break; 731 case ISD::SETONE: BROpcode = V8::FBLG; break; 732 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 733 } 734 break; 735 } 736 737 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 738 // control-flow pattern. The incoming instruction knows the destination vreg 739 // to set, the condition code register to branch on, the true/false values to 740 // select between, and a branch opcode to use. 741 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 742 ilist<MachineBasicBlock>::iterator It = BB; 743 ++It; 744 745 // thisMBB: 746 // ... 747 // TrueVal = ... 748 // [f]bCC copy1MBB 749 // fallthrough --> copy0MBB 750 MachineBasicBlock *thisMBB = BB; 751 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 752 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 753 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 754 MachineFunction *F = BB->getParent(); 755 F->getBasicBlockList().insert(It, copy0MBB); 756 F->getBasicBlockList().insert(It, sinkMBB); 757 // Update machine-CFG edges 758 BB->addSuccessor(copy0MBB); 759 BB->addSuccessor(sinkMBB); 760 761 // copy0MBB: 762 // %FalseValue = ... 763 // # fallthrough to sinkMBB 764 BB = copy0MBB; 765 766 // Update machine-CFG edges 767 BB->addSuccessor(sinkMBB); 768 769 // sinkMBB: 770 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 771 // ... 772 BB = sinkMBB; 773 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 774 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 775 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 776 777 delete MI; // The pseudo instruction is gone now. 778 return BB; 779} 780 781//===----------------------------------------------------------------------===// 782// Instruction Selector Implementation 783//===----------------------------------------------------------------------===// 784 785//===--------------------------------------------------------------------===// 786/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine 787/// instructions for SelectionDAG operations. 788/// 789namespace { 790class SparcV8DAGToDAGISel : public SelectionDAGISel { 791 SparcV8TargetLowering V8Lowering; 792public: 793 SparcV8DAGToDAGISel(TargetMachine &TM) 794 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 795 796 SDOperand Select(SDOperand Op); 797 798 // Complex Pattern Selectors. 799 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 800 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 801 802 /// InstructionSelectBasicBlock - This callback is invoked by 803 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 804 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 805 806 virtual const char *getPassName() const { 807 return "PowerPC DAG->DAG Pattern Instruction Selection"; 808 } 809 810 // Include the pieces autogenerated from the target description. 811#include "SparcV8GenDAGISel.inc" 812}; 813} // end anonymous namespace 814 815/// InstructionSelectBasicBlock - This callback is invoked by 816/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 817void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 818 DEBUG(BB->dump()); 819 820 // Select target instructions for the DAG. 821 DAG.setRoot(Select(DAG.getRoot())); 822 CodeGenMap.clear(); 823 DAG.RemoveDeadNodes(); 824 825 // Emit machine code to BB. 826 ScheduleAndEmitDAG(DAG); 827} 828 829bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 830 SDOperand &Offset) { 831 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 832 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 833 Offset = CurDAG->getTargetConstant(0, MVT::i32); 834 return true; 835 } 836 837 if (Addr.getOpcode() == ISD::ADD) { 838 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 839 if (Predicate_simm13(CN)) { 840 if (FrameIndexSDNode *FIN = 841 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 842 // Constant offset from frame ref. 843 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 844 } else { 845 Base = Select(Addr.getOperand(0)); 846 } 847 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 848 return true; 849 } 850 } 851 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 852 Base = Select(Addr.getOperand(1)); 853 Offset = Addr.getOperand(0).getOperand(0); 854 return true; 855 } 856 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 857 Base = Select(Addr.getOperand(0)); 858 Offset = Addr.getOperand(1).getOperand(0); 859 return true; 860 } 861 } 862 Base = Select(Addr); 863 Offset = CurDAG->getTargetConstant(0, MVT::i32); 864 return true; 865} 866 867bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 868 SDOperand &R2) { 869 if (Addr.getOpcode() == ISD::FrameIndex) return false; 870 if (Addr.getOpcode() == ISD::ADD) { 871 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 872 Predicate_simm13(Addr.getOperand(1).Val)) 873 return false; // Let the reg+imm pattern catch this! 874 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 875 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 876 return false; // Let the reg+imm pattern catch this! 877 R1 = Select(Addr.getOperand(0)); 878 R2 = Select(Addr.getOperand(1)); 879 return true; 880 } 881 882 R1 = Select(Addr); 883 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 884 return true; 885} 886 887SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 888 SDNode *N = Op.Val; 889 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 890 N->getOpcode() < V8ISD::FIRST_NUMBER) 891 return Op; // Already selected. 892 // If this has already been converted, use it. 893 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 894 if (CGMI != CodeGenMap.end()) return CGMI->second; 895 896 switch (N->getOpcode()) { 897 default: break; 898 case ISD::Register: return Op; 899 case ISD::FrameIndex: { 900 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 901 if (N->hasOneUse()) 902 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 903 CurDAG->getTargetFrameIndex(FI, MVT::i32), 904 CurDAG->getTargetConstant(0, MVT::i32)); 905 return CodeGenMap[Op] = 906 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 907 CurDAG->getTargetFrameIndex(FI, MVT::i32), 908 CurDAG->getTargetConstant(0, MVT::i32)); 909 } 910 case V8ISD::CMPICC: { 911 // FIXME: Handle compare with immediate. 912 SDOperand LHS = Select(N->getOperand(0)); 913 SDOperand RHS = Select(N->getOperand(1)); 914 SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 915 LHS, RHS); 916 return CodeGenMap[Op] = Result.getValue(1); 917 } 918 case ISD::ADD_PARTS: { 919 SDOperand LHSL = Select(N->getOperand(0)); 920 SDOperand LHSH = Select(N->getOperand(1)); 921 SDOperand RHSL = Select(N->getOperand(2)); 922 SDOperand RHSH = Select(N->getOperand(3)); 923 // FIXME, handle immediate RHS. 924 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 925 LHSL, RHSL); 926 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 927 Low.getValue(1)); 928 CodeGenMap[SDOperand(N, 0)] = Low; 929 CodeGenMap[SDOperand(N, 1)] = Hi; 930 return Op.ResNo ? Hi : Low; 931 } 932 case ISD::SUB_PARTS: { 933 SDOperand LHSL = Select(N->getOperand(0)); 934 SDOperand LHSH = Select(N->getOperand(1)); 935 SDOperand RHSL = Select(N->getOperand(2)); 936 SDOperand RHSH = Select(N->getOperand(3)); 937 // FIXME, handle immediate RHS. 938 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 939 LHSL, RHSL); 940 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 941 Low.getValue(1)); 942 CodeGenMap[SDOperand(N, 0)] = Low; 943 CodeGenMap[SDOperand(N, 1)] = Hi; 944 return Op.ResNo ? Hi : Low; 945 } 946 case ISD::SDIV: 947 case ISD::UDIV: { 948 // FIXME: should use a custom expander to expose the SRA to the dag. 949 SDOperand DivLHS = Select(N->getOperand(0)); 950 SDOperand DivRHS = Select(N->getOperand(1)); 951 952 // Set the Y register to the high-part. 953 SDOperand TopPart; 954 if (N->getOpcode() == ISD::SDIV) { 955 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 956 CurDAG->getTargetConstant(31, MVT::i32)); 957 } else { 958 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 959 } 960 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 961 CurDAG->getRegister(V8::G0, MVT::i32)); 962 963 // FIXME: Handle div by immediate. 964 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 965 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 966 } 967 case ISD::MULHU: 968 case ISD::MULHS: { 969 // FIXME: Handle mul by immediate. 970 SDOperand MulLHS = Select(N->getOperand(0)); 971 SDOperand MulRHS = Select(N->getOperand(1)); 972 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 973 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 974 MulLHS, MulRHS); 975 // The high part is in the Y register. 976 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 977 } 978 case ISD::CALL: 979 // FIXME: This is a workaround for a bug in tblgen. 980 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 981 // Emits: (CALL:void (tglobaladdr:i32):$dst) 982 // Pattern complexity = 2 cost = 1 983 SDOperand N1 = N->getOperand(1); 984 if (N1.getOpcode() != ISD::TargetGlobalAddress && 985 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 986 SDOperand InFlag = SDOperand(0, 0); 987 SDOperand Chain = N->getOperand(0); 988 SDOperand Tmp0 = N1; 989 Chain = Select(Chain); 990 SDOperand Result; 991 if (N->getNumOperands() == 3) { 992 InFlag = Select(N->getOperand(2)); 993 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 994 Chain, InFlag); 995 } else { 996 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 997 Chain); 998 } 999 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 1000 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 1001 return Result.getValue(Op.ResNo); 1002 } 1003 P47Fail:; 1004 1005 } 1006 1007 return SelectCode(Op); 1008} 1009 1010 1011/// createPPCISelDag - This pass converts a legalized DAG into a 1012/// PowerPC-specific DAG, ready for instruction scheduling. 1013/// 1014FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 1015 return new SparcV8DAGToDAGISel(TM); 1016} 1017