SparcISelDAGToDAG.cpp revision 7ec6a6e96eeacfa2c4d9d14df6254951f35539d3
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 RET_FLAG, // Return with a flag operand. 50 }; 51} 52 53namespace { 54 class SparcV8TargetLowering : public TargetLowering { 55 int VarArgsFrameOffset; // Frame offset to start of varargs area. 56 public: 57 SparcV8TargetLowering(TargetMachine &TM); 58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 59 virtual std::vector<SDOperand> 60 LowerArguments(Function &F, SelectionDAG &DAG); 61 virtual std::pair<SDOperand, SDOperand> 62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 63 unsigned CC, 64 bool isTailCall, SDOperand Callee, ArgListTy &Args, 65 SelectionDAG &DAG); 66 67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, 68 SelectionDAG &DAG); 69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, 70 Value *VAListV, SelectionDAG &DAG); 71 virtual std::pair<SDOperand,SDOperand> 72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 73 const Type *ArgTy, SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 }; 80} 81 82SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 83 : TargetLowering(TM) { 84 85 // Set up the register classes. 86 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 87 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 88 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 89 90 // Custom legalize GlobalAddress nodes into LO/HI parts. 91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 92 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 93 94 // Sparc doesn't have sext_inreg, replace them with shl/sra 95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 98 99 // Sparc has no REM operation. 100 setOperationAction(ISD::UREM, MVT::i32, Expand); 101 setOperationAction(ISD::SREM, MVT::i32, Expand); 102 103 // Custom expand fp<->sint 104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 105 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 106 107 // Expand fp<->uint 108 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 109 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 110 111 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 112 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 113 114 // Turn FP extload into load/fextend 115 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 116 117 // Sparc has no select or setcc: expand to SELECT_CC. 118 setOperationAction(ISD::SELECT, MVT::i32, Expand); 119 setOperationAction(ISD::SELECT, MVT::f32, Expand); 120 setOperationAction(ISD::SELECT, MVT::f64, Expand); 121 setOperationAction(ISD::SETCC, MVT::i32, Expand); 122 setOperationAction(ISD::SETCC, MVT::f32, Expand); 123 setOperationAction(ISD::SETCC, MVT::f64, Expand); 124 125 // Sparc doesn't have BRCOND either, it has BR_CC. 126 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 127 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 128 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 129 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 130 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 131 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 132 133 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 134 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 135 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 136 137 // V8 has no intrinsics for these particular operations. 138 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 139 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 140 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 141 142 setOperationAction(ISD::FSIN , MVT::f64, Expand); 143 setOperationAction(ISD::FCOS , MVT::f64, Expand); 144 setOperationAction(ISD::FSIN , MVT::f32, Expand); 145 setOperationAction(ISD::FCOS , MVT::f32, Expand); 146 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 147 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 148 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 149 150 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 151 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 152 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 153 154 // We don't have line number support yet. 155 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 156 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 157 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand); 158 159 computeRegisterProperties(); 160} 161 162/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 163/// either one or two GPRs, including FP values. TODO: we should pass FP values 164/// in FP registers for fastcc functions. 165std::vector<SDOperand> 166SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 167 MachineFunction &MF = DAG.getMachineFunction(); 168 SSARegMap *RegMap = MF.getSSARegMap(); 169 std::vector<SDOperand> ArgValues; 170 171 static const unsigned ArgRegs[] = { 172 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 173 }; 174 175 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 176 unsigned ArgOffset = 68; 177 178 SDOperand Root = DAG.getRoot(); 179 std::vector<SDOperand> OutChains; 180 181 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 182 MVT::ValueType ObjectVT = getValueType(I->getType()); 183 184 switch (ObjectVT) { 185 default: assert(0 && "Unhandled argument type!"); 186 case MVT::i1: 187 case MVT::i8: 188 case MVT::i16: 189 case MVT::i32: 190 if (I->use_empty()) { // Argument is dead. 191 if (CurArgReg < ArgRegEnd) ++CurArgReg; 192 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 193 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 194 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 195 MF.addLiveIn(*CurArgReg++, VReg); 196 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 197 if (ObjectVT != MVT::i32) { 198 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 199 : ISD::AssertZext; 200 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 201 DAG.getValueType(ObjectVT)); 202 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 203 } 204 ArgValues.push_back(Arg); 205 } else { 206 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 207 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 208 SDOperand Load; 209 if (ObjectVT == MVT::i32) { 210 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 211 } else { 212 unsigned LoadOp = 213 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 214 215 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 216 DAG.getSrcValue(0), ObjectVT); 217 } 218 ArgValues.push_back(Load); 219 } 220 221 ArgOffset += 4; 222 break; 223 case MVT::f32: 224 if (I->use_empty()) { // Argument is dead. 225 if (CurArgReg < ArgRegEnd) ++CurArgReg; 226 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 227 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 228 // FP value is passed in an integer register. 229 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 230 MF.addLiveIn(*CurArgReg++, VReg); 231 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 232 233 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 234 ArgValues.push_back(Arg); 235 } 236 ArgOffset += 4; 237 break; 238 239 case MVT::i64: 240 case MVT::f64: 241 if (I->use_empty()) { // Argument is dead. 242 if (CurArgReg < ArgRegEnd) ++CurArgReg; 243 if (CurArgReg < ArgRegEnd) ++CurArgReg; 244 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 245 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 246 ((CurArgReg-ArgRegs) & 1) == 0) { 247 // If this is a double argument and the whole thing lives on the stack, 248 // and the argument is aligned, load the double straight from the stack. 249 // We can't do a load in cases like void foo([6ints], int,double), 250 // because the double wouldn't be aligned! 251 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 252 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 253 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 254 DAG.getSrcValue(0))); 255 } else { 256 SDOperand HiVal; 257 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 258 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 259 MF.addLiveIn(*CurArgReg++, VRegHi); 260 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 261 } else { 262 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 263 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 264 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 265 } 266 267 SDOperand LoVal; 268 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 269 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 270 MF.addLiveIn(*CurArgReg++, VRegLo); 271 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 272 } else { 273 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 274 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 275 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 276 } 277 278 // Compose the two halves together into an i64 unit. 279 SDOperand WholeValue = 280 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 281 282 // If we want a double, do a bit convert. 283 if (ObjectVT == MVT::f64) 284 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 285 286 ArgValues.push_back(WholeValue); 287 } 288 ArgOffset += 8; 289 break; 290 } 291 } 292 293 // Store remaining ArgRegs to the stack if this is a varargs function. 294 if (F.getFunctionType()->isVarArg()) { 295 // Remember the vararg offset for the va_start implementation. 296 VarArgsFrameOffset = ArgOffset; 297 298 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 299 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 300 MF.addLiveIn(*CurArgReg, VReg); 301 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 302 303 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 304 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 305 306 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 307 Arg, FIPtr, DAG.getSrcValue(0))); 308 ArgOffset += 4; 309 } 310 } 311 312 if (!OutChains.empty()) 313 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 314 315 // Finally, inform the code generator which regs we return values in. 316 switch (getValueType(F.getReturnType())) { 317 default: assert(0 && "Unknown type!"); 318 case MVT::isVoid: break; 319 case MVT::i1: 320 case MVT::i8: 321 case MVT::i16: 322 case MVT::i32: 323 MF.addLiveOut(V8::I0); 324 break; 325 case MVT::i64: 326 MF.addLiveOut(V8::I0); 327 MF.addLiveOut(V8::I1); 328 break; 329 case MVT::f32: 330 MF.addLiveOut(V8::F0); 331 break; 332 case MVT::f64: 333 MF.addLiveOut(V8::D0); 334 break; 335 } 336 337 return ArgValues; 338} 339 340std::pair<SDOperand, SDOperand> 341SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 342 bool isVarArg, unsigned CC, 343 bool isTailCall, SDOperand Callee, 344 ArgListTy &Args, SelectionDAG &DAG) { 345 MachineFunction &MF = DAG.getMachineFunction(); 346 // Count the size of the outgoing arguments. 347 unsigned ArgsSize = 0; 348 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 349 switch (getValueType(Args[i].second)) { 350 default: assert(0 && "Unknown value type!"); 351 case MVT::i1: 352 case MVT::i8: 353 case MVT::i16: 354 case MVT::i32: 355 case MVT::f32: 356 ArgsSize += 4; 357 break; 358 case MVT::i64: 359 case MVT::f64: 360 ArgsSize += 8; 361 break; 362 } 363 } 364 if (ArgsSize > 4*6) 365 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 366 else 367 ArgsSize = 0; 368 369 // Keep stack frames 8-byte aligned. 370 ArgsSize = (ArgsSize+7) & ~7; 371 372 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 373 DAG.getConstant(ArgsSize, getPointerTy())); 374 375 SDOperand StackPtr, NullSV; 376 std::vector<SDOperand> Stores; 377 std::vector<SDOperand> RegValuesToPass; 378 unsigned ArgOffset = 68; 379 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 380 SDOperand Val = Args[i].first; 381 MVT::ValueType ObjectVT = Val.getValueType(); 382 SDOperand ValToStore(0, 0); 383 unsigned ObjSize; 384 switch (ObjectVT) { 385 default: assert(0 && "Unhandled argument type!"); 386 case MVT::i1: 387 case MVT::i8: 388 case MVT::i16: 389 // Promote the integer to 32-bits. If the input type is signed, use a 390 // sign extend, otherwise use a zero extend. 391 if (Args[i].second->isSigned()) 392 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 393 else 394 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 395 // FALL THROUGH 396 case MVT::i32: 397 ObjSize = 4; 398 399 if (RegValuesToPass.size() >= 6) { 400 ValToStore = Val; 401 } else { 402 RegValuesToPass.push_back(Val); 403 } 404 break; 405 case MVT::f32: 406 ObjSize = 4; 407 if (RegValuesToPass.size() >= 6) { 408 ValToStore = Val; 409 } else { 410 // Convert this to a FP value in an int reg. 411 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 412 RegValuesToPass.push_back(Val); 413 } 414 break; 415 case MVT::f64: 416 ObjSize = 8; 417 // If we can store this directly into the outgoing slot, do so. We can 418 // do this when all ArgRegs are used and if the outgoing slot is aligned. 419 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 420 ValToStore = Val; 421 break; 422 } 423 424 // Otherwise, convert this to a FP value in int regs. 425 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 426 // FALL THROUGH 427 case MVT::i64: 428 ObjSize = 8; 429 if (RegValuesToPass.size() >= 6) { 430 ValToStore = Val; // Whole thing is passed in memory. 431 break; 432 } 433 434 // Split the value into top and bottom part. Top part goes in a reg. 435 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 436 DAG.getConstant(1, MVT::i32)); 437 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 438 DAG.getConstant(0, MVT::i32)); 439 RegValuesToPass.push_back(Hi); 440 441 if (RegValuesToPass.size() >= 6) { 442 ValToStore = Lo; 443 ArgOffset += 4; 444 ObjSize = 4; 445 } else { 446 RegValuesToPass.push_back(Lo); 447 } 448 break; 449 } 450 451 if (ValToStore.Val) { 452 if (!StackPtr.Val) { 453 StackPtr = DAG.getRegister(V8::O6, MVT::i32); 454 NullSV = DAG.getSrcValue(NULL); 455 } 456 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 457 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 458 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 459 ValToStore, PtrOff, NullSV)); 460 } 461 ArgOffset += ObjSize; 462 } 463 464 // Emit all stores, make sure the occur before any copies into physregs. 465 if (!Stores.empty()) 466 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 467 468 static const unsigned ArgRegs[] = { 469 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 470 }; 471 472 // Build a sequence of copy-to-reg nodes chained together with token chain 473 // and flag operands which copy the outgoing args into O[0-5]. 474 SDOperand InFlag; 475 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 476 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 477 InFlag = Chain.getValue(1); 478 } 479 480 // If the callee is a GlobalAddress node (quite common, every direct call is) 481 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 482 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 483 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 484 485 std::vector<MVT::ValueType> NodeTys; 486 NodeTys.push_back(MVT::Other); // Returns a chain 487 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 488 if (InFlag.Val) 489 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0); 490 else 491 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0); 492 InFlag = Chain.getValue(1); 493 494 MVT::ValueType RetTyVT = getValueType(RetTy); 495 SDOperand RetVal; 496 if (RetTyVT != MVT::isVoid) { 497 switch (RetTyVT) { 498 default: assert(0 && "Unknown value type to return!"); 499 case MVT::i1: 500 case MVT::i8: 501 case MVT::i16: 502 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 503 Chain = RetVal.getValue(1); 504 505 // Add a note to keep track of whether it is sign or zero extended. 506 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 507 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 508 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 509 break; 510 case MVT::i32: 511 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 512 Chain = RetVal.getValue(1); 513 break; 514 case MVT::f32: 515 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 516 Chain = RetVal.getValue(1); 517 break; 518 case MVT::f64: 519 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 520 Chain = RetVal.getValue(1); 521 break; 522 case MVT::i64: 523 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag); 524 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 525 Lo.getValue(2)); 526 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 527 Chain = Hi.getValue(1); 528 break; 529 } 530 } 531 532 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 533 DAG.getConstant(ArgsSize, getPointerTy())); 534 535 return std::make_pair(RetVal, Chain); 536} 537 538SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 539 SelectionDAG &DAG) { 540 SDOperand Copy; 541 switch (Op.getValueType()) { 542 default: assert(0 && "Unknown type to return!"); 543 case MVT::i32: 544 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand()); 545 break; 546 case MVT::f32: 547 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand()); 548 break; 549 case MVT::f64: 550 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand()); 551 break; 552 case MVT::i64: 553 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 554 DAG.getConstant(1, MVT::i32)); 555 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 556 DAG.getConstant(0, MVT::i32)); 557 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand()); 558 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1)); 559 break; 560 } 561 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 562} 563 564SDOperand SparcV8TargetLowering:: 565LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, 566 SelectionDAG &DAG) { 567 568 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 569 DAG.getRegister(V8::I6, MVT::i32), 570 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 571 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Offset, 572 VAListP, DAG.getSrcValue(VAListV)); 573} 574 575std::pair<SDOperand,SDOperand> SparcV8TargetLowering:: 576LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 577 const Type *ArgTy, SelectionDAG &DAG) { 578 // Load the pointer out of the valist. 579 SDOperand Ptr = DAG.getLoad(MVT::i32, Chain, 580 VAListP, DAG.getSrcValue(VAListV)); 581 MVT::ValueType ArgVT = getValueType(ArgTy); 582 SDOperand Val = DAG.getLoad(ArgVT, Ptr.getValue(1), 583 Ptr, DAG.getSrcValue(NULL)); 584 // Increment the pointer. 585 Ptr = DAG.getNode(ISD::ADD, MVT::i32, Ptr, 586 DAG.getConstant(MVT::getSizeInBits(ArgVT)/8, MVT::i32)); 587 // Store it back to the valist. 588 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain, Ptr, 589 VAListP, DAG.getSrcValue(VAListV)); 590 return std::make_pair(Val, Chain); 591} 592 593std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 594LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 595 SelectionDAG &DAG) { 596 assert(0 && "Unimp"); 597 abort(); 598} 599 600SDOperand SparcV8TargetLowering:: 601LowerOperation(SDOperand Op, SelectionDAG &DAG) { 602 switch (Op.getOpcode()) { 603 default: assert(0 && "Should not custom lower this!"); 604 case ISD::GlobalAddress: { 605 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 606 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 607 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 608 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 609 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 610 } 611 case ISD::ConstantPool: { 612 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 613 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 614 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 615 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 616 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 617 } 618 case ISD::FP_TO_SINT: 619 // Convert the fp value to integer in an FP register. 620 assert(Op.getValueType() == MVT::i32); 621 Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0)); 622 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 623 case ISD::SINT_TO_FP: { 624 assert(Op.getOperand(0).getValueType() == MVT::i32); 625 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 626 // Convert the int value to FP in an FP register. 627 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp); 628 } 629 case ISD::BR_CC: { 630 SDOperand Chain = Op.getOperand(0); 631 SDOperand CC = Op.getOperand(1); 632 SDOperand LHS = Op.getOperand(2); 633 SDOperand RHS = Op.getOperand(3); 634 SDOperand Dest = Op.getOperand(4); 635 636 // Get the condition flag. 637 if (LHS.getValueType() == MVT::i32) { 638 std::vector<MVT::ValueType> VTs; 639 VTs.push_back(MVT::i32); 640 VTs.push_back(MVT::Flag); 641 std::vector<SDOperand> Ops; 642 Ops.push_back(LHS); 643 Ops.push_back(RHS); 644 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops); 645 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 646 } else { 647 std::vector<MVT::ValueType> VTs; 648 VTs.push_back(MVT::i32); 649 VTs.push_back(MVT::Flag); 650 std::vector<SDOperand> Ops; 651 Ops.push_back(LHS); 652 Ops.push_back(RHS); 653 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, VTs, Ops); 654 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 655 } 656 } 657 case ISD::SELECT_CC: { 658 SDOperand LHS = Op.getOperand(0); 659 SDOperand RHS = Op.getOperand(1); 660 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 661 SDOperand TrueVal = Op.getOperand(2); 662 SDOperand FalseVal = Op.getOperand(3); 663 664 unsigned Opc; 665 Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC; 666 std::vector<MVT::ValueType> VTs; 667 VTs.push_back(LHS.getValueType()); 668 VTs.push_back(MVT::Flag); 669 std::vector<SDOperand> Ops; 670 Ops.push_back(LHS); 671 Ops.push_back(RHS); 672 SDOperand CompareFlag = DAG.getNode(Opc, VTs, Ops).getValue(1); 673 674 Opc = LHS.getValueType() == MVT::i32 ? 675 V8ISD::SELECT_ICC : V8ISD::SELECT_FCC; 676 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 677 DAG.getConstant(CC, MVT::i32), CompareFlag); 678 } 679 } 680} 681 682MachineBasicBlock * 683SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 684 MachineBasicBlock *BB) { 685 unsigned BROpcode; 686 // Figure out the conditional branch opcode to use for this select_cc. 687 switch (MI->getOpcode()) { 688 default: assert(0 && "Unknown SELECT_CC!"); 689 case V8::SELECT_CC_Int_ICC: 690 case V8::SELECT_CC_FP_ICC: 691 case V8::SELECT_CC_DFP_ICC: 692 // Integer compare. 693 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 694 default: assert(0 && "Unknown integer condition code!"); 695 case ISD::SETEQ: BROpcode = V8::BE; break; 696 case ISD::SETNE: BROpcode = V8::BNE; break; 697 case ISD::SETLT: BROpcode = V8::BL; break; 698 case ISD::SETGT: BROpcode = V8::BG; break; 699 case ISD::SETLE: BROpcode = V8::BLE; break; 700 case ISD::SETGE: BROpcode = V8::BGE; break; 701 case ISD::SETULT: BROpcode = V8::BCS; break; 702 case ISD::SETULE: BROpcode = V8::BLEU; break; 703 case ISD::SETUGT: BROpcode = V8::BGU; break; 704 case ISD::SETUGE: BROpcode = V8::BCC; break; 705 } 706 break; 707 case V8::SELECT_CC_Int_FCC: 708 case V8::SELECT_CC_FP_FCC: 709 case V8::SELECT_CC_DFP_FCC: 710 // FP compare. 711 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 712 default: assert(0 && "Unknown fp condition code!"); 713 case ISD::SETEQ: BROpcode = V8::FBE; break; 714 case ISD::SETNE: BROpcode = V8::FBNE; break; 715 case ISD::SETLT: BROpcode = V8::FBL; break; 716 case ISD::SETGT: BROpcode = V8::FBG; break; 717 case ISD::SETLE: BROpcode = V8::FBLE; break; 718 case ISD::SETGE: BROpcode = V8::FBGE; break; 719 case ISD::SETULT: BROpcode = V8::FBUL; break; 720 case ISD::SETULE: BROpcode = V8::FBULE; break; 721 case ISD::SETUGT: BROpcode = V8::FBUG; break; 722 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 723 case ISD::SETUO: BROpcode = V8::FBU; break; 724 case ISD::SETO: BROpcode = V8::FBO; break; 725 case ISD::SETONE: BROpcode = V8::FBLG; break; 726 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 727 } 728 break; 729 } 730 731 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 732 // control-flow pattern. The incoming instruction knows the destination vreg 733 // to set, the condition code register to branch on, the true/false values to 734 // select between, and a branch opcode to use. 735 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 736 ilist<MachineBasicBlock>::iterator It = BB; 737 ++It; 738 739 // thisMBB: 740 // ... 741 // TrueVal = ... 742 // [f]bCC copy1MBB 743 // fallthrough --> copy0MBB 744 MachineBasicBlock *thisMBB = BB; 745 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 746 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 747 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 748 MachineFunction *F = BB->getParent(); 749 F->getBasicBlockList().insert(It, copy0MBB); 750 F->getBasicBlockList().insert(It, sinkMBB); 751 // Update machine-CFG edges 752 BB->addSuccessor(copy0MBB); 753 BB->addSuccessor(sinkMBB); 754 755 // copy0MBB: 756 // %FalseValue = ... 757 // # fallthrough to sinkMBB 758 BB = copy0MBB; 759 760 // Update machine-CFG edges 761 BB->addSuccessor(sinkMBB); 762 763 // sinkMBB: 764 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 765 // ... 766 BB = sinkMBB; 767 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 768 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 769 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 770 771 delete MI; // The pseudo instruction is gone now. 772 return BB; 773} 774 775//===----------------------------------------------------------------------===// 776// Instruction Selector Implementation 777//===----------------------------------------------------------------------===// 778 779//===--------------------------------------------------------------------===// 780/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine 781/// instructions for SelectionDAG operations. 782/// 783namespace { 784class SparcV8DAGToDAGISel : public SelectionDAGISel { 785 SparcV8TargetLowering V8Lowering; 786public: 787 SparcV8DAGToDAGISel(TargetMachine &TM) 788 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 789 790 SDOperand Select(SDOperand Op); 791 792 // Complex Pattern Selectors. 793 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 794 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 795 796 /// InstructionSelectBasicBlock - This callback is invoked by 797 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 798 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 799 800 virtual const char *getPassName() const { 801 return "PowerPC DAG->DAG Pattern Instruction Selection"; 802 } 803 804 // Include the pieces autogenerated from the target description. 805#include "SparcV8GenDAGISel.inc" 806}; 807} // end anonymous namespace 808 809/// InstructionSelectBasicBlock - This callback is invoked by 810/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 811void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 812 DEBUG(BB->dump()); 813 814 // Select target instructions for the DAG. 815 DAG.setRoot(Select(DAG.getRoot())); 816 CodeGenMap.clear(); 817 DAG.RemoveDeadNodes(); 818 819 // Emit machine code to BB. 820 ScheduleAndEmitDAG(DAG); 821} 822 823bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 824 SDOperand &Offset) { 825 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 826 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 827 Offset = CurDAG->getTargetConstant(0, MVT::i32); 828 return true; 829 } 830 831 if (Addr.getOpcode() == ISD::ADD) { 832 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 833 if (Predicate_simm13(CN)) { 834 if (FrameIndexSDNode *FIN = 835 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 836 // Constant offset from frame ref. 837 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 838 } else { 839 Base = Select(Addr.getOperand(0)); 840 } 841 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 842 return true; 843 } 844 } 845 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 846 Base = Select(Addr.getOperand(1)); 847 Offset = Addr.getOperand(0).getOperand(0); 848 return true; 849 } 850 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 851 Base = Select(Addr.getOperand(0)); 852 Offset = Addr.getOperand(1).getOperand(0); 853 return true; 854 } 855 } 856 Base = Select(Addr); 857 Offset = CurDAG->getTargetConstant(0, MVT::i32); 858 return true; 859} 860 861bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 862 SDOperand &R2) { 863 if (Addr.getOpcode() == ISD::FrameIndex) return false; 864 if (Addr.getOpcode() == ISD::ADD) { 865 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 866 Predicate_simm13(Addr.getOperand(1).Val)) 867 return false; // Let the reg+imm pattern catch this! 868 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 869 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 870 return false; // Let the reg+imm pattern catch this! 871 R1 = Select(Addr.getOperand(0)); 872 R2 = Select(Addr.getOperand(1)); 873 return true; 874 } 875 876 R1 = Select(Addr); 877 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 878 return true; 879} 880 881SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 882 SDNode *N = Op.Val; 883 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 884 N->getOpcode() < V8ISD::FIRST_NUMBER) 885 return Op; // Already selected. 886 // If this has already been converted, use it. 887 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 888 if (CGMI != CodeGenMap.end()) return CGMI->second; 889 890 switch (N->getOpcode()) { 891 default: break; 892 case ISD::FrameIndex: { 893 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 894 if (N->hasOneUse()) 895 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 896 CurDAG->getTargetFrameIndex(FI, MVT::i32), 897 CurDAG->getTargetConstant(0, MVT::i32)); 898 return CodeGenMap[Op] = 899 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 900 CurDAG->getTargetFrameIndex(FI, MVT::i32), 901 CurDAG->getTargetConstant(0, MVT::i32)); 902 } 903 case ISD::ADD_PARTS: { 904 SDOperand LHSL = Select(N->getOperand(0)); 905 SDOperand LHSH = Select(N->getOperand(1)); 906 SDOperand RHSL = Select(N->getOperand(2)); 907 SDOperand RHSH = Select(N->getOperand(3)); 908 // FIXME, handle immediate RHS. 909 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 910 LHSL, RHSL); 911 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 912 Low.getValue(1)); 913 CodeGenMap[SDOperand(N, 0)] = Low; 914 CodeGenMap[SDOperand(N, 1)] = Hi; 915 return Op.ResNo ? Hi : Low; 916 } 917 case ISD::SUB_PARTS: { 918 SDOperand LHSL = Select(N->getOperand(0)); 919 SDOperand LHSH = Select(N->getOperand(1)); 920 SDOperand RHSL = Select(N->getOperand(2)); 921 SDOperand RHSH = Select(N->getOperand(3)); 922 // FIXME, handle immediate RHS. 923 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 924 LHSL, RHSL); 925 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 926 Low.getValue(1)); 927 CodeGenMap[SDOperand(N, 0)] = Low; 928 CodeGenMap[SDOperand(N, 1)] = Hi; 929 return Op.ResNo ? Hi : Low; 930 } 931 case ISD::SDIV: 932 case ISD::UDIV: { 933 // FIXME: should use a custom expander to expose the SRA to the dag. 934 SDOperand DivLHS = Select(N->getOperand(0)); 935 SDOperand DivRHS = Select(N->getOperand(1)); 936 937 // Set the Y register to the high-part. 938 SDOperand TopPart; 939 if (N->getOpcode() == ISD::SDIV) { 940 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 941 CurDAG->getTargetConstant(31, MVT::i32)); 942 } else { 943 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 944 } 945 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 946 CurDAG->getRegister(V8::G0, MVT::i32)); 947 948 // FIXME: Handle div by immediate. 949 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 950 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 951 } 952 case ISD::MULHU: 953 case ISD::MULHS: { 954 // FIXME: Handle mul by immediate. 955 SDOperand MulLHS = Select(N->getOperand(0)); 956 SDOperand MulRHS = Select(N->getOperand(1)); 957 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 958 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 959 MulLHS, MulRHS); 960 // The high part is in the Y register. 961 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 962 } 963 case ISD::CALL: 964 // FIXME: This is a workaround for a bug in tblgen. 965 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 966 // Emits: (CALL:void (tglobaladdr:i32):$dst) 967 // Pattern complexity = 2 cost = 1 968 SDOperand N1 = N->getOperand(1); 969 if (N1.getOpcode() != ISD::TargetGlobalAddress && 970 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 971 SDOperand InFlag = SDOperand(0, 0); 972 SDOperand Chain = N->getOperand(0); 973 SDOperand Tmp0 = N1; 974 Chain = Select(Chain); 975 SDOperand Result; 976 if (N->getNumOperands() == 3) { 977 InFlag = Select(N->getOperand(2)); 978 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 979 Chain, InFlag); 980 } else { 981 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 982 Chain); 983 } 984 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 985 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 986 return Result.getValue(Op.ResNo); 987 } 988 P47Fail:; 989 990 } 991 992 return SelectCode(Op); 993} 994 995 996/// createPPCISelDag - This pass converts a legalized DAG into a 997/// PowerPC-specific DAG, ready for instruction scheduling. 998/// 999FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 1000 return new SparcV8DAGToDAGISel(TM); 1001} 1002