SparcISelDAGToDAG.cpp revision 8b2794aeff151be8cdbd44786c1d0f94f8f2e427 
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the SPARC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcTargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/Intrinsics.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/SelectionDAG.h"
23#include "llvm/CodeGen/SelectionDAGISel.h"
24#include "llvm/CodeGen/SSARegMap.h"
25#include "llvm/Target/TargetLowering.h"
26#include "llvm/Support/Debug.h"
27#include <iostream>
28#include <queue>
29#include <set>
30using namespace llvm;
31
32//===----------------------------------------------------------------------===//
33// TargetLowering Implementation
34//===----------------------------------------------------------------------===//
35
36namespace SPISD {
37  enum {
38    FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
39    CMPICC,      // Compare two GPR operands, set icc.
40    CMPFCC,      // Compare two FP operands, set fcc.
41    BRICC,       // Branch to dest on icc condition
42    BRFCC,       // Branch to dest on fcc condition
43    SELECT_ICC,  // Select between two values using the current ICC flags.
44    SELECT_FCC,  // Select between two values using the current FCC flags.
45
46    Hi, Lo,      // Hi/Lo operations, typically on a global address.
47
48    FTOI,        // FP to Int within a FP register.
49    ITOF,        // Int to FP within a FP register.
50
51    CALL,        // A call instruction.
52    RET_FLAG     // Return with a flag operand.
53  };
54}
55
56/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
57/// condition.
58static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
59  switch (CC) {
60  default: assert(0 && "Unknown integer condition code!");
61  case ISD::SETEQ:  return SPCC::ICC_E;
62  case ISD::SETNE:  return SPCC::ICC_NE;
63  case ISD::SETLT:  return SPCC::ICC_L;
64  case ISD::SETGT:  return SPCC::ICC_G;
65  case ISD::SETLE:  return SPCC::ICC_LE;
66  case ISD::SETGE:  return SPCC::ICC_GE;
67  case ISD::SETULT: return SPCC::ICC_CS;
68  case ISD::SETULE: return SPCC::ICC_LEU;
69  case ISD::SETUGT: return SPCC::ICC_GU;
70  case ISD::SETUGE: return SPCC::ICC_CC;
71  }
72}
73
74/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
75/// FCC condition.
76static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
77  switch (CC) {
78  default: assert(0 && "Unknown fp condition code!");
79  case ISD::SETEQ:
80  case ISD::SETOEQ: return SPCC::FCC_E;
81  case ISD::SETNE:
82  case ISD::SETUNE: return SPCC::FCC_NE;
83  case ISD::SETLT:
84  case ISD::SETOLT: return SPCC::FCC_L;
85  case ISD::SETGT:
86  case ISD::SETOGT: return SPCC::FCC_G;
87  case ISD::SETLE:
88  case ISD::SETOLE: return SPCC::FCC_LE;
89  case ISD::SETGE:
90  case ISD::SETOGE: return SPCC::FCC_GE;
91  case ISD::SETULT: return SPCC::FCC_UL;
92  case ISD::SETULE: return SPCC::FCC_ULE;
93  case ISD::SETUGT: return SPCC::FCC_UG;
94  case ISD::SETUGE: return SPCC::FCC_UGE;
95  case ISD::SETUO:  return SPCC::FCC_U;
96  case ISD::SETO:   return SPCC::FCC_O;
97  case ISD::SETONE: return SPCC::FCC_LG;
98  case ISD::SETUEQ: return SPCC::FCC_UE;
99  }
100}
101
102namespace {
103  class SparcTargetLowering : public TargetLowering {
104    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
105  public:
106    SparcTargetLowering(TargetMachine &TM);
107    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
108
109    /// computeMaskedBitsForTargetNode - Determine which of the bits specified
110    /// in Mask are known to be either zero or one and return them in the
111    /// KnownZero/KnownOne bitsets.
112    virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
113                                                uint64_t Mask,
114                                                uint64_t &KnownZero,
115                                                uint64_t &KnownOne,
116                                                unsigned Depth = 0) const;
117
118    virtual std::vector<SDOperand>
119      LowerArguments(Function &F, SelectionDAG &DAG);
120    virtual std::pair<SDOperand, SDOperand>
121      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
122                  unsigned CC,
123                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
124                  SelectionDAG &DAG);
125    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
126                                                       MachineBasicBlock *MBB);
127
128    virtual const char *getTargetNodeName(unsigned Opcode) const;
129  };
130}
131
132SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
133  : TargetLowering(TM) {
134
135  // Set up the register classes.
136  addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
137  addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
138  addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
139
140  // Turn FP extload into load/fextend
141  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
142
143  // Custom legalize GlobalAddress nodes into LO/HI parts.
144  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
145  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
146
147  // Sparc doesn't have sext_inreg, replace them with shl/sra
148  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
149  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
150  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
151
152  // Sparc has no REM operation.
153  setOperationAction(ISD::UREM, MVT::i32, Expand);
154  setOperationAction(ISD::SREM, MVT::i32, Expand);
155
156  // Custom expand fp<->sint
157  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
158  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
159
160  // Expand fp<->uint
161  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
162  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
163
164  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
165  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
166
167  // Sparc has no select or setcc: expand to SELECT_CC.
168  setOperationAction(ISD::SELECT, MVT::i32, Expand);
169  setOperationAction(ISD::SELECT, MVT::f32, Expand);
170  setOperationAction(ISD::SELECT, MVT::f64, Expand);
171  setOperationAction(ISD::SETCC, MVT::i32, Expand);
172  setOperationAction(ISD::SETCC, MVT::f32, Expand);
173  setOperationAction(ISD::SETCC, MVT::f64, Expand);
174
175  // Sparc doesn't have BRCOND either, it has BR_CC.
176  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
177  setOperationAction(ISD::BRIND, MVT::i32, Expand);
178  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
179  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
180  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
181
182  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
183  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
184  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
185
186  // SPARC has no intrinsics for these particular operations.
187  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
188  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
189  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
190
191  setOperationAction(ISD::FSIN , MVT::f64, Expand);
192  setOperationAction(ISD::FCOS , MVT::f64, Expand);
193  setOperationAction(ISD::FSIN , MVT::f32, Expand);
194  setOperationAction(ISD::FCOS , MVT::f32, Expand);
195  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
196  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
197  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
198  setOperationAction(ISD::ROTL , MVT::i32, Expand);
199  setOperationAction(ISD::ROTR , MVT::i32, Expand);
200  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
201  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
202  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
203
204  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
205  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
206  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
207
208  // We don't have line number support yet.
209  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
210  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
211  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
212
213  // RET must be custom lowered, to meet ABI requirements
214  setOperationAction(ISD::RET               , MVT::Other, Custom);
215
216  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
217  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
218  // VAARG needs to be lowered to not do unaligned accesses for doubles.
219  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
220
221  // Use the default implementation.
222  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
223  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
224  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
225  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
226  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
227
228  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
229  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
230
231  setStackPointerRegisterToSaveRestore(SP::O6);
232
233  if (TM.getSubtarget<SparcSubtarget>().isV9()) {
234    setOperationAction(ISD::CTPOP, MVT::i32, Legal);
235  }
236
237  computeRegisterProperties();
238}
239
240const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
241  switch (Opcode) {
242  default: return 0;
243  case SPISD::CMPICC:     return "SPISD::CMPICC";
244  case SPISD::CMPFCC:     return "SPISD::CMPFCC";
245  case SPISD::BRICC:      return "SPISD::BRICC";
246  case SPISD::BRFCC:      return "SPISD::BRFCC";
247  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
248  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
249  case SPISD::Hi:         return "SPISD::Hi";
250  case SPISD::Lo:         return "SPISD::Lo";
251  case SPISD::FTOI:       return "SPISD::FTOI";
252  case SPISD::ITOF:       return "SPISD::ITOF";
253  case SPISD::CALL:       return "SPISD::CALL";
254  case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
255  }
256}
257
258/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
259/// be zero. Op is expected to be a target specific node. Used by DAG
260/// combiner.
261void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
262                                                         uint64_t Mask,
263                                                         uint64_t &KnownZero,
264                                                         uint64_t &KnownOne,
265                                                         unsigned Depth) const {
266  uint64_t KnownZero2, KnownOne2;
267  KnownZero = KnownOne = 0;   // Don't know anything.
268
269  switch (Op.getOpcode()) {
270  default: break;
271  case SPISD::SELECT_ICC:
272  case SPISD::SELECT_FCC:
273    ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
274    ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
275    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
276    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
277
278    // Only known if known in both the LHS and RHS.
279    KnownOne &= KnownOne2;
280    KnownZero &= KnownZero2;
281    break;
282  }
283}
284
285/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
286/// either one or two GPRs, including FP values.  TODO: we should pass FP values
287/// in FP registers for fastcc functions.
288std::vector<SDOperand>
289SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
290  MachineFunction &MF = DAG.getMachineFunction();
291  SSARegMap *RegMap = MF.getSSARegMap();
292  std::vector<SDOperand> ArgValues;
293
294  static const unsigned ArgRegs[] = {
295    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
296  };
297
298  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
299  unsigned ArgOffset = 68;
300
301  SDOperand Root = DAG.getRoot();
302  std::vector<SDOperand> OutChains;
303
304  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
305    MVT::ValueType ObjectVT = getValueType(I->getType());
306
307    switch (ObjectVT) {
308    default: assert(0 && "Unhandled argument type!");
309    case MVT::i1:
310    case MVT::i8:
311    case MVT::i16:
312    case MVT::i32:
313      if (I->use_empty()) {                // Argument is dead.
314        if (CurArgReg < ArgRegEnd) ++CurArgReg;
315        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
316      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
317        unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
318        MF.addLiveIn(*CurArgReg++, VReg);
319        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
320        if (ObjectVT != MVT::i32) {
321          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
322                                                       : ISD::AssertZext;
323          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
324                            DAG.getValueType(ObjectVT));
325          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
326        }
327        ArgValues.push_back(Arg);
328      } else {
329        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
330        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
331        SDOperand Load;
332        if (ObjectVT == MVT::i32) {
333          Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
334        } else {
335          ISD::LoadExtType LoadOp =
336            I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
337
338          // Sparc is big endian, so add an offset based on the ObjectVT.
339          unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
340          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
341                              DAG.getConstant(Offset, MVT::i32));
342          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
343                                NULL, 0, ObjectVT);
344          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
345        }
346        ArgValues.push_back(Load);
347      }
348
349      ArgOffset += 4;
350      break;
351    case MVT::f32:
352      if (I->use_empty()) {                // Argument is dead.
353        if (CurArgReg < ArgRegEnd) ++CurArgReg;
354        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
355      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
356        // FP value is passed in an integer register.
357        unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
358        MF.addLiveIn(*CurArgReg++, VReg);
359        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
360
361        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
362        ArgValues.push_back(Arg);
363      } else {
364        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
365        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
366        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
367        ArgValues.push_back(Load);
368      }
369      ArgOffset += 4;
370      break;
371
372    case MVT::i64:
373    case MVT::f64:
374      if (I->use_empty()) {                // Argument is dead.
375        if (CurArgReg < ArgRegEnd) ++CurArgReg;
376        if (CurArgReg < ArgRegEnd) ++CurArgReg;
377        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
378      } else if (/* FIXME: Apparently this isn't safe?? */
379                 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
380                 ((CurArgReg-ArgRegs) & 1) == 0) {
381        // If this is a double argument and the whole thing lives on the stack,
382        // and the argument is aligned, load the double straight from the stack.
383        // We can't do a load in cases like void foo([6ints], int,double),
384        // because the double wouldn't be aligned!
385        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
386        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
387        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
388      } else {
389        SDOperand HiVal;
390        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
391          unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
392          MF.addLiveIn(*CurArgReg++, VRegHi);
393          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
394        } else {
395          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
396          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
397          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
398        }
399
400        SDOperand LoVal;
401        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
402          unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
403          MF.addLiveIn(*CurArgReg++, VRegLo);
404          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
405        } else {
406          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
407          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
408          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
409        }
410
411        // Compose the two halves together into an i64 unit.
412        SDOperand WholeValue =
413          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
414
415        // If we want a double, do a bit convert.
416        if (ObjectVT == MVT::f64)
417          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
418
419        ArgValues.push_back(WholeValue);
420      }
421      ArgOffset += 8;
422      break;
423    }
424  }
425
426  // Store remaining ArgRegs to the stack if this is a varargs function.
427  if (F.getFunctionType()->isVarArg()) {
428    // Remember the vararg offset for the va_start implementation.
429    VarArgsFrameOffset = ArgOffset;
430
431    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
432      unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
433      MF.addLiveIn(*CurArgReg, VReg);
434      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
435
436      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
437      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
438
439      OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
440      ArgOffset += 4;
441    }
442  }
443
444  if (!OutChains.empty())
445    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
446                            &OutChains[0], OutChains.size()));
447
448  // Finally, inform the code generator which regs we return values in.
449  switch (getValueType(F.getReturnType())) {
450  default: assert(0 && "Unknown type!");
451  case MVT::isVoid: break;
452  case MVT::i1:
453  case MVT::i8:
454  case MVT::i16:
455  case MVT::i32:
456    MF.addLiveOut(SP::I0);
457    break;
458  case MVT::i64:
459    MF.addLiveOut(SP::I0);
460    MF.addLiveOut(SP::I1);
461    break;
462  case MVT::f32:
463    MF.addLiveOut(SP::F0);
464    break;
465  case MVT::f64:
466    MF.addLiveOut(SP::D0);
467    break;
468  }
469
470  return ArgValues;
471}
472
473std::pair<SDOperand, SDOperand>
474SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
475                                 bool isVarArg, unsigned CC,
476                                 bool isTailCall, SDOperand Callee,
477                                 ArgListTy &Args, SelectionDAG &DAG) {
478  // Count the size of the outgoing arguments.
479  unsigned ArgsSize = 0;
480  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
481    switch (getValueType(Args[i].second)) {
482    default: assert(0 && "Unknown value type!");
483    case MVT::i1:
484    case MVT::i8:
485    case MVT::i16:
486    case MVT::i32:
487    case MVT::f32:
488      ArgsSize += 4;
489      break;
490    case MVT::i64:
491    case MVT::f64:
492      ArgsSize += 8;
493      break;
494    }
495  }
496  if (ArgsSize > 4*6)
497    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
498  else
499    ArgsSize = 0;
500
501  // Keep stack frames 8-byte aligned.
502  ArgsSize = (ArgsSize+7) & ~7;
503
504  Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
505
506  SDOperand StackPtr;
507  std::vector<SDOperand> Stores;
508  std::vector<SDOperand> RegValuesToPass;
509  unsigned ArgOffset = 68;
510  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
511    SDOperand Val = Args[i].first;
512    MVT::ValueType ObjectVT = Val.getValueType();
513    SDOperand ValToStore(0, 0);
514    unsigned ObjSize;
515    switch (ObjectVT) {
516    default: assert(0 && "Unhandled argument type!");
517    case MVT::i1:
518    case MVT::i8:
519    case MVT::i16:
520      // Promote the integer to 32-bits.  If the input type is signed, use a
521      // sign extend, otherwise use a zero extend.
522      if (Args[i].second->isSigned())
523        Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
524      else
525        Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
526      // FALL THROUGH
527    case MVT::i32:
528      ObjSize = 4;
529
530      if (RegValuesToPass.size() >= 6) {
531        ValToStore = Val;
532      } else {
533        RegValuesToPass.push_back(Val);
534      }
535      break;
536    case MVT::f32:
537      ObjSize = 4;
538      if (RegValuesToPass.size() >= 6) {
539        ValToStore = Val;
540      } else {
541        // Convert this to a FP value in an int reg.
542        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
543        RegValuesToPass.push_back(Val);
544      }
545      break;
546    case MVT::f64:
547      ObjSize = 8;
548      // If we can store this directly into the outgoing slot, do so.  We can
549      // do this when all ArgRegs are used and if the outgoing slot is aligned.
550      // FIXME: McGill/misr fails with this.
551      if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
552        ValToStore = Val;
553        break;
554      }
555
556      // Otherwise, convert this to a FP value in int regs.
557      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
558      // FALL THROUGH
559    case MVT::i64:
560      ObjSize = 8;
561      if (RegValuesToPass.size() >= 6) {
562        ValToStore = Val;    // Whole thing is passed in memory.
563        break;
564      }
565
566      // Split the value into top and bottom part.  Top part goes in a reg.
567      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
568                                 DAG.getConstant(1, MVT::i32));
569      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
570                                 DAG.getConstant(0, MVT::i32));
571      RegValuesToPass.push_back(Hi);
572
573      if (RegValuesToPass.size() >= 6) {
574        ValToStore = Lo;
575        ArgOffset += 4;
576        ObjSize = 4;
577      } else {
578        RegValuesToPass.push_back(Lo);
579      }
580      break;
581    }
582
583    if (ValToStore.Val) {
584      if (!StackPtr.Val) {
585        StackPtr = DAG.getRegister(SP::O6, MVT::i32);
586      }
587      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
588      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
589      Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
590    }
591    ArgOffset += ObjSize;
592  }
593
594  // Emit all stores, make sure the occur before any copies into physregs.
595  if (!Stores.empty())
596    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
597
598  static const unsigned ArgRegs[] = {
599    SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
600  };
601
602  // Build a sequence of copy-to-reg nodes chained together with token chain
603  // and flag operands which copy the outgoing args into O[0-5].
604  SDOperand InFlag;
605  for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
606    Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
607    InFlag = Chain.getValue(1);
608  }
609
610  // If the callee is a GlobalAddress node (quite common, every direct call is)
611  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
612  // Likewise ExternalSymbol -> TargetExternalSymbol.
613  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
614    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
615  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
616    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
617
618  std::vector<MVT::ValueType> NodeTys;
619  NodeTys.push_back(MVT::Other);   // Returns a chain
620  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
621  SDOperand Ops[] = { Chain, Callee, InFlag };
622  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
623  InFlag = Chain.getValue(1);
624
625  MVT::ValueType RetTyVT = getValueType(RetTy);
626  SDOperand RetVal;
627  if (RetTyVT != MVT::isVoid) {
628    switch (RetTyVT) {
629    default: assert(0 && "Unknown value type to return!");
630    case MVT::i1:
631    case MVT::i8:
632    case MVT::i16:
633      RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
634      Chain = RetVal.getValue(1);
635
636      // Add a note to keep track of whether it is sign or zero extended.
637      RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
638                           MVT::i32, RetVal, DAG.getValueType(RetTyVT));
639      RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
640      break;
641    case MVT::i32:
642      RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
643      Chain = RetVal.getValue(1);
644      break;
645    case MVT::f32:
646      RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
647      Chain = RetVal.getValue(1);
648      break;
649    case MVT::f64:
650      RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
651      Chain = RetVal.getValue(1);
652      break;
653    case MVT::i64:
654      SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
655      SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
656                                        Lo.getValue(2));
657      RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
658      Chain = Hi.getValue(1);
659      break;
660    }
661  }
662
663  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
664                      DAG.getConstant(ArgsSize, getPointerTy()));
665
666  return std::make_pair(RetVal, Chain);
667}
668
669// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
670// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
671static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
672                             ISD::CondCode CC, unsigned &SPCC) {
673  if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
674      CC == ISD::SETNE &&
675      ((LHS.getOpcode() == SPISD::SELECT_ICC &&
676        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
677       (LHS.getOpcode() == SPISD::SELECT_FCC &&
678        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
679      isa<ConstantSDNode>(LHS.getOperand(0)) &&
680      isa<ConstantSDNode>(LHS.getOperand(1)) &&
681      cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
682      cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
683    SDOperand CMPCC = LHS.getOperand(3);
684    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
685    LHS = CMPCC.getOperand(0);
686    RHS = CMPCC.getOperand(1);
687  }
688}
689
690
691SDOperand SparcTargetLowering::
692LowerOperation(SDOperand Op, SelectionDAG &DAG) {
693  switch (Op.getOpcode()) {
694  default: assert(0 && "Should not custom lower this!");
695  case ISD::GlobalAddress: {
696    GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
697    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
698    SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
699    SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
700    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
701  }
702  case ISD::ConstantPool: {
703    Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal();
704    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
705                                  cast<ConstantPoolSDNode>(Op)->getAlignment());
706    SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
707    SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
708    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
709  }
710  case ISD::FP_TO_SINT:
711    // Convert the fp value to integer in an FP register.
712    assert(Op.getValueType() == MVT::i32);
713    Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
714    return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
715  case ISD::SINT_TO_FP: {
716    assert(Op.getOperand(0).getValueType() == MVT::i32);
717    SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
718    // Convert the int value to FP in an FP register.
719    return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
720  }
721  case ISD::BR_CC: {
722    SDOperand Chain = Op.getOperand(0);
723    ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
724    SDOperand LHS = Op.getOperand(2);
725    SDOperand RHS = Op.getOperand(3);
726    SDOperand Dest = Op.getOperand(4);
727    unsigned Opc, SPCC = ~0U;
728
729    // If this is a br_cc of a "setcc", and if the setcc got lowered into
730    // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
731    LookThroughSetCC(LHS, RHS, CC, SPCC);
732
733    // Get the condition flag.
734    SDOperand CompareFlag;
735    if (LHS.getValueType() == MVT::i32) {
736      std::vector<MVT::ValueType> VTs;
737      VTs.push_back(MVT::i32);
738      VTs.push_back(MVT::Flag);
739      SDOperand Ops[2] = { LHS, RHS };
740      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
741      if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
742      Opc = SPISD::BRICC;
743    } else {
744      CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
745      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
746      Opc = SPISD::BRFCC;
747    }
748    return DAG.getNode(Opc, MVT::Other, Chain, Dest,
749                       DAG.getConstant(SPCC, MVT::i32), CompareFlag);
750  }
751  case ISD::SELECT_CC: {
752    SDOperand LHS = Op.getOperand(0);
753    SDOperand RHS = Op.getOperand(1);
754    ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
755    SDOperand TrueVal = Op.getOperand(2);
756    SDOperand FalseVal = Op.getOperand(3);
757    unsigned Opc, SPCC = ~0U;
758
759    // If this is a select_cc of a "setcc", and if the setcc got lowered into
760    // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
761    LookThroughSetCC(LHS, RHS, CC, SPCC);
762
763    SDOperand CompareFlag;
764    if (LHS.getValueType() == MVT::i32) {
765      std::vector<MVT::ValueType> VTs;
766      VTs.push_back(LHS.getValueType());   // subcc returns a value
767      VTs.push_back(MVT::Flag);
768      SDOperand Ops[2] = { LHS, RHS };
769      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
770      Opc = SPISD::SELECT_ICC;
771      if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
772    } else {
773      CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
774      Opc = SPISD::SELECT_FCC;
775      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
776    }
777    return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
778                       DAG.getConstant(SPCC, MVT::i32), CompareFlag);
779  }
780  case ISD::VASTART: {
781    // vastart just stores the address of the VarArgsFrameIndex slot into the
782    // memory location argument.
783    SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
784                                   DAG.getRegister(SP::I6, MVT::i32),
785                                DAG.getConstant(VarArgsFrameOffset, MVT::i32));
786    SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
787    return DAG.getStore(Op.getOperand(0), Offset,
788                        Op.getOperand(1), SV->getValue(), SV->getOffset());
789  }
790  case ISD::VAARG: {
791    SDNode *Node = Op.Val;
792    MVT::ValueType VT = Node->getValueType(0);
793    SDOperand InChain = Node->getOperand(0);
794    SDOperand VAListPtr = Node->getOperand(1);
795    SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
796    SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
797                                   SV->getValue(), SV->getOffset());
798    // Increment the pointer, VAList, to the next vaarg
799    SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
800                                    DAG.getConstant(MVT::getSizeInBits(VT)/8,
801                                                    getPointerTy()));
802    // Store the incremented VAList to the legalized pointer
803    InChain = DAG.getStore(VAList.getValue(1), NextPtr,
804                           VAListPtr, SV->getValue(), SV->getOffset());
805    // Load the actual argument out of the pointer VAList, unless this is an
806    // f64 load.
807    if (VT != MVT::f64) {
808      return DAG.getLoad(VT, InChain, VAList, NULL, 0);
809    } else {
810      // Otherwise, load it as i64, then do a bitconvert.
811      SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
812      std::vector<MVT::ValueType> Tys;
813      Tys.push_back(MVT::f64);
814      Tys.push_back(MVT::Other);
815      // Bit-Convert the value to f64.
816      SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
817                           V.getValue(1) };
818      return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
819    }
820  }
821  case ISD::DYNAMIC_STACKALLOC: {
822    SDOperand Chain = Op.getOperand(0);  // Legalize the chain.
823    SDOperand Size  = Op.getOperand(1);  // Legalize the size.
824
825    unsigned SPReg = SP::O6;
826    SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
827    SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);    // Value
828    Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP);      // Output chain
829
830    // The resultant pointer is actually 16 words from the bottom of the stack,
831    // to provide a register spill area.
832    SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
833                                   DAG.getConstant(96, MVT::i32));
834    std::vector<MVT::ValueType> Tys;
835    Tys.push_back(MVT::i32);
836    Tys.push_back(MVT::Other);
837    SDOperand Ops[2] = { NewVal, Chain };
838    return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
839  }
840  case ISD::RET: {
841    SDOperand Copy;
842
843    switch(Op.getNumOperands()) {
844    default:
845      assert(0 && "Do not know how to return this many arguments!");
846      abort();
847    case 1:
848      return SDOperand(); // ret void is legal
849    case 3: {
850      unsigned ArgReg;
851      switch(Op.getOperand(1).getValueType()) {
852      default: assert(0 && "Unknown type to return!");
853      case MVT::i32: ArgReg = SP::I0; break;
854      case MVT::f32: ArgReg = SP::F0; break;
855      case MVT::f64: ArgReg = SP::D0; break;
856      }
857      Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
858                              SDOperand());
859      break;
860    }
861    case 5:
862      Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
863                              SDOperand());
864      Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
865      break;
866    }
867    return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
868  }
869  }
870}
871
872MachineBasicBlock *
873SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
874                                             MachineBasicBlock *BB) {
875  unsigned BROpcode;
876  unsigned CC;
877  // Figure out the conditional branch opcode to use for this select_cc.
878  switch (MI->getOpcode()) {
879  default: assert(0 && "Unknown SELECT_CC!");
880  case SP::SELECT_CC_Int_ICC:
881  case SP::SELECT_CC_FP_ICC:
882  case SP::SELECT_CC_DFP_ICC:
883    BROpcode = SP::BCOND;
884    break;
885  case SP::SELECT_CC_Int_FCC:
886  case SP::SELECT_CC_FP_FCC:
887  case SP::SELECT_CC_DFP_FCC:
888    BROpcode = SP::FBCOND;
889    break;
890  }
891
892  CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
893
894  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
895  // control-flow pattern.  The incoming instruction knows the destination vreg
896  // to set, the condition code register to branch on, the true/false values to
897  // select between, and a branch opcode to use.
898  const BasicBlock *LLVM_BB = BB->getBasicBlock();
899  ilist<MachineBasicBlock>::iterator It = BB;
900  ++It;
901
902  //  thisMBB:
903  //  ...
904  //   TrueVal = ...
905  //   [f]bCC copy1MBB
906  //   fallthrough --> copy0MBB
907  MachineBasicBlock *thisMBB = BB;
908  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
909  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
910  BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC);
911  MachineFunction *F = BB->getParent();
912  F->getBasicBlockList().insert(It, copy0MBB);
913  F->getBasicBlockList().insert(It, sinkMBB);
914  // Update machine-CFG edges by first adding all successors of the current
915  // block to the new block which will contain the Phi node for the select.
916  for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
917      e = BB->succ_end(); i != e; ++i)
918    sinkMBB->addSuccessor(*i);
919  // Next, remove all successors of the current block, and add the true
920  // and fallthrough blocks as its successors.
921  while(!BB->succ_empty())
922    BB->removeSuccessor(BB->succ_begin());
923  BB->addSuccessor(copy0MBB);
924  BB->addSuccessor(sinkMBB);
925
926  //  copy0MBB:
927  //   %FalseValue = ...
928  //   # fallthrough to sinkMBB
929  BB = copy0MBB;
930
931  // Update machine-CFG edges
932  BB->addSuccessor(sinkMBB);
933
934  //  sinkMBB:
935  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
936  //  ...
937  BB = sinkMBB;
938  BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg())
939    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
940    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
941
942  delete MI;   // The pseudo instruction is gone now.
943  return BB;
944}
945
946//===----------------------------------------------------------------------===//
947// Instruction Selector Implementation
948//===----------------------------------------------------------------------===//
949
950//===--------------------------------------------------------------------===//
951/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
952/// instructions for SelectionDAG operations.
953///
954namespace {
955class SparcDAGToDAGISel : public SelectionDAGISel {
956  SparcTargetLowering Lowering;
957
958  /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
959  /// make the right decision when generating code for different targets.
960  const SparcSubtarget &Subtarget;
961public:
962  SparcDAGToDAGISel(TargetMachine &TM)
963    : SelectionDAGISel(Lowering), Lowering(TM),
964      Subtarget(TM.getSubtarget<SparcSubtarget>()) {
965  }
966
967  SDNode *Select(SDOperand Op);
968
969  // Complex Pattern Selectors.
970  bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
971  bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
972
973  /// InstructionSelectBasicBlock - This callback is invoked by
974  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
975  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
976
977  virtual const char *getPassName() const {
978    return "SPARC DAG->DAG Pattern Instruction Selection";
979  }
980
981  // Include the pieces autogenerated from the target description.
982#include "SparcGenDAGISel.inc"
983};
984}  // end anonymous namespace
985
986/// InstructionSelectBasicBlock - This callback is invoked by
987/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
988void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
989  DEBUG(BB->dump());
990
991  // Select target instructions for the DAG.
992  DAG.setRoot(SelectRoot(DAG.getRoot()));
993  DAG.RemoveDeadNodes();
994
995  // Emit machine code to BB.
996  ScheduleAndEmitDAG(DAG);
997}
998
999bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
1000                                     SDOperand &Offset) {
1001  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1002    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1003    Offset = CurDAG->getTargetConstant(0, MVT::i32);
1004    return true;
1005  }
1006  if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1007      Addr.getOpcode() == ISD::TargetGlobalAddress)
1008    return false;  // direct calls.
1009
1010  if (Addr.getOpcode() == ISD::ADD) {
1011    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1012      if (Predicate_simm13(CN)) {
1013        if (FrameIndexSDNode *FIN =
1014                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1015          // Constant offset from frame ref.
1016          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1017        } else {
1018          Base = Addr.getOperand(0);
1019        }
1020        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1021        return true;
1022      }
1023    }
1024    if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1025      Base = Addr.getOperand(1);
1026      Offset = Addr.getOperand(0).getOperand(0);
1027      return true;
1028    }
1029    if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1030      Base = Addr.getOperand(0);
1031      Offset = Addr.getOperand(1).getOperand(0);
1032      return true;
1033    }
1034  }
1035  Base = Addr;
1036  Offset = CurDAG->getTargetConstant(0, MVT::i32);
1037  return true;
1038}
1039
1040bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
1041                                     SDOperand &R2) {
1042  if (Addr.getOpcode() == ISD::FrameIndex) return false;
1043  if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1044      Addr.getOpcode() == ISD::TargetGlobalAddress)
1045    return false;  // direct calls.
1046
1047  if (Addr.getOpcode() == ISD::ADD) {
1048    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1049        Predicate_simm13(Addr.getOperand(1).Val))
1050      return false;  // Let the reg+imm pattern catch this!
1051    if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1052        Addr.getOperand(1).getOpcode() == SPISD::Lo)
1053      return false;  // Let the reg+imm pattern catch this!
1054    R1 = Addr.getOperand(0);
1055    R2 = Addr.getOperand(1);
1056    return true;
1057  }
1058
1059  R1 = Addr;
1060  R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1061  return true;
1062}
1063
1064SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
1065  SDNode *N = Op.Val;
1066  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1067      N->getOpcode() < SPISD::FIRST_NUMBER)
1068    return NULL;   // Already selected.
1069
1070  switch (N->getOpcode()) {
1071  default: break;
1072  case ISD::SDIV:
1073  case ISD::UDIV: {
1074    // FIXME: should use a custom expander to expose the SRA to the dag.
1075    SDOperand DivLHS = N->getOperand(0);
1076    SDOperand DivRHS = N->getOperand(1);
1077    AddToISelQueue(DivLHS);
1078    AddToISelQueue(DivRHS);
1079
1080    // Set the Y register to the high-part.
1081    SDOperand TopPart;
1082    if (N->getOpcode() == ISD::SDIV) {
1083      TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1084                                   CurDAG->getTargetConstant(31, MVT::i32)), 0);
1085    } else {
1086      TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1087    }
1088    TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1089                                     CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1090
1091    // FIXME: Handle div by immediate.
1092    unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1093    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
1094                                TopPart);
1095  }
1096  case ISD::MULHU:
1097  case ISD::MULHS: {
1098    // FIXME: Handle mul by immediate.
1099    SDOperand MulLHS = N->getOperand(0);
1100    SDOperand MulRHS = N->getOperand(1);
1101    AddToISelQueue(MulLHS);
1102    AddToISelQueue(MulRHS);
1103    unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1104    SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1105                                        MulLHS, MulRHS);
1106    // The high part is in the Y register.
1107    return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1108    return NULL;
1109  }
1110  }
1111
1112  return SelectCode(Op);
1113}
1114
1115
1116/// createSparcISelDag - This pass converts a legalized DAG into a
1117/// SPARC-specific DAG, ready for instruction scheduling.
1118///
1119FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1120  return new SparcDAGToDAGISel(TM);
1121}
1122