SparcISelDAGToDAG.cpp revision 8dc4b59b857fdffe79dca0a3a8516ddf942d5466
1ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===// 2ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown// 3ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown// The LLVM Compiler Infrastructure 4ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown// 5ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown// This file was developed by Chris Lattner and is distributed under 6ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown// the University of Illinois Open Source License. See LICENSE.TXT for details. 7ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown// 8ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown//===----------------------------------------------------------------------===// 9ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown// 10ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown// This file defines an instruction selector for the SPARC target. 11ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown// 12ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown//===----------------------------------------------------------------------===// 13ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 14ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "Sparc.h" 15ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "SparcTargetMachine.h" 16ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "llvm/DerivedTypes.h" 17ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "llvm/Function.h" 18ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "llvm/Intrinsics.h" 19ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "llvm/CodeGen/MachineFrameInfo.h" 20ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "llvm/CodeGen/MachineFunction.h" 21ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "llvm/CodeGen/MachineInstrBuilder.h" 22ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "llvm/CodeGen/SelectionDAG.h" 23ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "llvm/CodeGen/SelectionDAGISel.h" 24ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "llvm/CodeGen/SSARegMap.h" 25ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "llvm/Target/TargetLowering.h" 26ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include "llvm/Support/Debug.h" 27ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include <queue> 28ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown#include <set> 29ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownusing namespace llvm; 30ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 31ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown//===----------------------------------------------------------------------===// 32ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown// TargetLowering Implementation 33ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown//===----------------------------------------------------------------------===// 34ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 35ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownnamespace SPISD { 36ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown enum { 37ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END, 38ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown CMPICC, // Compare two GPR operands, set icc. 39ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown CMPFCC, // Compare two FP operands, set fcc. 40ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown BRICC, // Branch to dest on icc condition 41ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown BRFCC, // Branch to dest on fcc condition 42ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown SELECT_ICC, // Select between two values using the current ICC flags. 43ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown SELECT_FCC, // Select between two values using the current FCC flags. 44ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 45ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown Hi, Lo, // Hi/Lo operations, typically on a global address. 46ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 47ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown FTOI, // FP to Int within a FP register. 48ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown ITOF, // Int to FP within a FP register. 49ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 50ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown CALL, // A call instruction. 51ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown RET_FLAG // Return with a flag operand. 52ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown }; 53ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown} 54ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 55ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 56ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/// condition. 57ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownstatic SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 58ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown switch (CC) { 59ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown default: assert(0 && "Unknown integer condition code!"); 60ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETEQ: return SPCC::ICC_E; 61ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETNE: return SPCC::ICC_NE; 62ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETLT: return SPCC::ICC_L; 63ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETGT: return SPCC::ICC_G; 64ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETLE: return SPCC::ICC_LE; 65ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETGE: return SPCC::ICC_GE; 66ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETULT: return SPCC::ICC_CS; 67ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETULE: return SPCC::ICC_LEU; 68ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETUGT: return SPCC::ICC_GU; 69ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETUGE: return SPCC::ICC_CC; 70ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 71ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown} 72ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 73ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 74ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown/// FCC condition. 75ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownstatic SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 76ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown switch (CC) { 77ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown default: assert(0 && "Unknown fp condition code!"); 78ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETEQ: 79ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETOEQ: return SPCC::FCC_E; 80ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETNE: 81ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETUNE: return SPCC::FCC_NE; 82ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETLT: 83ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETOLT: return SPCC::FCC_L; 84ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETGT: 85ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETOGT: return SPCC::FCC_G; 86ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETLE: 87ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETOLE: return SPCC::FCC_LE; 88ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETGE: 89ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETOGE: return SPCC::FCC_GE; 90ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETULT: return SPCC::FCC_UL; 91ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETULE: return SPCC::FCC_ULE; 92ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETUGT: return SPCC::FCC_UG; 93ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETUGE: return SPCC::FCC_UGE; 94ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETUO: return SPCC::FCC_U; 95ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETO: return SPCC::FCC_O; 96ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETONE: return SPCC::FCC_LG; 97ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown case ISD::SETUEQ: return SPCC::FCC_UE; 98ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown } 99ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown} 100ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown 101ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brownnamespace { 102ed07e00d438c74b7a23c01bfffde77e3968305e4Jeff Brown class SparcTargetLowering : public TargetLowering { 103 int VarArgsFrameOffset; // Frame offset to start of varargs area. 104 public: 105 SparcTargetLowering(TargetMachine &TM); 106 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 107 108 /// computeMaskedBitsForTargetNode - Determine which of the bits specified 109 /// in Mask are known to be either zero or one and return them in the 110 /// KnownZero/KnownOne bitsets. 111 virtual void computeMaskedBitsForTargetNode(const SDOperand Op, 112 uint64_t Mask, 113 uint64_t &KnownZero, 114 uint64_t &KnownOne, 115 const SelectionDAG &DAG, 116 unsigned Depth = 0) const; 117 118 virtual std::vector<SDOperand> 119 LowerArguments(Function &F, SelectionDAG &DAG); 120 virtual std::pair<SDOperand, SDOperand> 121 LowerCallTo(SDOperand Chain, const Type *RetTy, bool RetTyIsSigned, 122 bool isVarArg, unsigned CC, bool isTailCall, SDOperand Callee, 123 ArgListTy &Args, SelectionDAG &DAG); 124 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 125 MachineBasicBlock *MBB); 126 127 virtual const char *getTargetNodeName(unsigned Opcode) const; 128 }; 129} 130 131SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 132 : TargetLowering(TM) { 133 134 // Set up the register classes. 135 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 136 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 137 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 138 139 // Turn FP extload into load/fextend 140 setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand); 141 142 // Custom legalize GlobalAddress nodes into LO/HI parts. 143 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 144 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 145 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 146 147 // Sparc doesn't have sext_inreg, replace them with shl/sra 148 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 149 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 151 152 // Sparc has no REM operation. 153 setOperationAction(ISD::UREM, MVT::i32, Expand); 154 setOperationAction(ISD::SREM, MVT::i32, Expand); 155 156 // Custom expand fp<->sint 157 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 158 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 159 160 // Expand fp<->uint 161 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 162 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 163 164 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); 165 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); 166 167 // Sparc has no select or setcc: expand to SELECT_CC. 168 setOperationAction(ISD::SELECT, MVT::i32, Expand); 169 setOperationAction(ISD::SELECT, MVT::f32, Expand); 170 setOperationAction(ISD::SELECT, MVT::f64, Expand); 171 setOperationAction(ISD::SETCC, MVT::i32, Expand); 172 setOperationAction(ISD::SETCC, MVT::f32, Expand); 173 setOperationAction(ISD::SETCC, MVT::f64, Expand); 174 175 // Sparc doesn't have BRCOND either, it has BR_CC. 176 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 177 setOperationAction(ISD::BRIND, MVT::Other, Expand); 178 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 179 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 180 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 181 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 182 183 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 184 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 185 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 186 187 // SPARC has no intrinsics for these particular operations. 188 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 189 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 190 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 191 192 setOperationAction(ISD::FSIN , MVT::f64, Expand); 193 setOperationAction(ISD::FCOS , MVT::f64, Expand); 194 setOperationAction(ISD::FREM , MVT::f64, Expand); 195 setOperationAction(ISD::FSIN , MVT::f32, Expand); 196 setOperationAction(ISD::FCOS , MVT::f32, Expand); 197 setOperationAction(ISD::FREM , MVT::f32, Expand); 198 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 199 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 200 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 201 setOperationAction(ISD::ROTL , MVT::i32, Expand); 202 setOperationAction(ISD::ROTR , MVT::i32, Expand); 203 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 204 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 205 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 206 207 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 208 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 209 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 210 211 // We don't have line number support yet. 212 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 213 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 214 setOperationAction(ISD::LABEL, MVT::Other, Expand); 215 216 // RET must be custom lowered, to meet ABI requirements 217 setOperationAction(ISD::RET , MVT::Other, Custom); 218 219 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 220 setOperationAction(ISD::VASTART , MVT::Other, Custom); 221 // VAARG needs to be lowered to not do unaligned accesses for doubles. 222 setOperationAction(ISD::VAARG , MVT::Other, Custom); 223 224 // Use the default implementation. 225 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 226 setOperationAction(ISD::VAEND , MVT::Other, Expand); 227 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 228 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 229 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 230 231 setOperationAction(ISD::ConstantFP, MVT::f64, Expand); 232 setOperationAction(ISD::ConstantFP, MVT::f32, Expand); 233 234 setStackPointerRegisterToSaveRestore(SP::O6); 235 236 if (TM.getSubtarget<SparcSubtarget>().isV9()) { 237 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 238 } 239 240 computeRegisterProperties(); 241} 242 243const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 244 switch (Opcode) { 245 default: return 0; 246 case SPISD::CMPICC: return "SPISD::CMPICC"; 247 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 248 case SPISD::BRICC: return "SPISD::BRICC"; 249 case SPISD::BRFCC: return "SPISD::BRFCC"; 250 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 251 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 252 case SPISD::Hi: return "SPISD::Hi"; 253 case SPISD::Lo: return "SPISD::Lo"; 254 case SPISD::FTOI: return "SPISD::FTOI"; 255 case SPISD::ITOF: return "SPISD::ITOF"; 256 case SPISD::CALL: return "SPISD::CALL"; 257 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 258 } 259} 260 261/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 262/// be zero. Op is expected to be a target specific node. Used by DAG 263/// combiner. 264void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op, 265 uint64_t Mask, 266 uint64_t &KnownZero, 267 uint64_t &KnownOne, 268 const SelectionDAG &DAG, 269 unsigned Depth) const { 270 uint64_t KnownZero2, KnownOne2; 271 KnownZero = KnownOne = 0; // Don't know anything. 272 273 switch (Op.getOpcode()) { 274 default: break; 275 case SPISD::SELECT_ICC: 276 case SPISD::SELECT_FCC: 277 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 278 Depth+1); 279 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 280 Depth+1); 281 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 282 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 283 284 // Only known if known in both the LHS and RHS. 285 KnownOne &= KnownOne2; 286 KnownZero &= KnownZero2; 287 break; 288 } 289} 290 291/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 292/// either one or two GPRs, including FP values. TODO: we should pass FP values 293/// in FP registers for fastcc functions. 294std::vector<SDOperand> 295SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 296 MachineFunction &MF = DAG.getMachineFunction(); 297 SSARegMap *RegMap = MF.getSSARegMap(); 298 std::vector<SDOperand> ArgValues; 299 300 static const unsigned ArgRegs[] = { 301 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 302 }; 303 304 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 305 unsigned ArgOffset = 68; 306 307 SDOperand Root = DAG.getRoot(); 308 std::vector<SDOperand> OutChains; 309 310 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 311 MVT::ValueType ObjectVT = getValueType(I->getType()); 312 313 switch (ObjectVT) { 314 default: assert(0 && "Unhandled argument type!"); 315 case MVT::i1: 316 case MVT::i8: 317 case MVT::i16: 318 case MVT::i32: 319 if (I->use_empty()) { // Argument is dead. 320 if (CurArgReg < ArgRegEnd) ++CurArgReg; 321 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 322 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 323 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 324 MF.addLiveIn(*CurArgReg++, VReg); 325 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 326 if (ObjectVT != MVT::i32) { 327 unsigned AssertOp = ISD::AssertSext; 328 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 329 DAG.getValueType(ObjectVT)); 330 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 331 } 332 ArgValues.push_back(Arg); 333 } else { 334 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 335 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 336 SDOperand Load; 337 if (ObjectVT == MVT::i32) { 338 Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 339 } else { 340 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 341 342 // Sparc is big endian, so add an offset based on the ObjectVT. 343 unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8); 344 FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr, 345 DAG.getConstant(Offset, MVT::i32)); 346 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 347 NULL, 0, ObjectVT); 348 Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load); 349 } 350 ArgValues.push_back(Load); 351 } 352 353 ArgOffset += 4; 354 break; 355 case MVT::f32: 356 if (I->use_empty()) { // Argument is dead. 357 if (CurArgReg < ArgRegEnd) ++CurArgReg; 358 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 359 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 360 // FP value is passed in an integer register. 361 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 362 MF.addLiveIn(*CurArgReg++, VReg); 363 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 364 365 Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg); 366 ArgValues.push_back(Arg); 367 } else { 368 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 369 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 370 SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0); 371 ArgValues.push_back(Load); 372 } 373 ArgOffset += 4; 374 break; 375 376 case MVT::i64: 377 case MVT::f64: 378 if (I->use_empty()) { // Argument is dead. 379 if (CurArgReg < ArgRegEnd) ++CurArgReg; 380 if (CurArgReg < ArgRegEnd) ++CurArgReg; 381 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 382 } else if (/* FIXME: Apparently this isn't safe?? */ 383 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 384 ((CurArgReg-ArgRegs) & 1) == 0) { 385 // If this is a double argument and the whole thing lives on the stack, 386 // and the argument is aligned, load the double straight from the stack. 387 // We can't do a load in cases like void foo([6ints], int,double), 388 // because the double wouldn't be aligned! 389 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 390 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 391 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0)); 392 } else { 393 SDOperand HiVal; 394 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 395 unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 396 MF.addLiveIn(*CurArgReg++, VRegHi); 397 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 398 } else { 399 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 400 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 401 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 402 } 403 404 SDOperand LoVal; 405 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 406 unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 407 MF.addLiveIn(*CurArgReg++, VRegLo); 408 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 409 } else { 410 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 411 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 412 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0); 413 } 414 415 // Compose the two halves together into an i64 unit. 416 SDOperand WholeValue = 417 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 418 419 // If we want a double, do a bit convert. 420 if (ObjectVT == MVT::f64) 421 WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue); 422 423 ArgValues.push_back(WholeValue); 424 } 425 ArgOffset += 8; 426 break; 427 } 428 } 429 430 // Store remaining ArgRegs to the stack if this is a varargs function. 431 if (F.getFunctionType()->isVarArg()) { 432 // Remember the vararg offset for the va_start implementation. 433 VarArgsFrameOffset = ArgOffset; 434 435 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 436 unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass); 437 MF.addLiveIn(*CurArgReg, VReg); 438 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 439 440 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 441 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 442 443 OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0)); 444 ArgOffset += 4; 445 } 446 } 447 448 if (!OutChains.empty()) 449 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, 450 &OutChains[0], OutChains.size())); 451 452 // Finally, inform the code generator which regs we return values in. 453 switch (getValueType(F.getReturnType())) { 454 default: assert(0 && "Unknown type!"); 455 case MVT::isVoid: break; 456 case MVT::i1: 457 case MVT::i8: 458 case MVT::i16: 459 case MVT::i32: 460 MF.addLiveOut(SP::I0); 461 break; 462 case MVT::i64: 463 MF.addLiveOut(SP::I0); 464 MF.addLiveOut(SP::I1); 465 break; 466 case MVT::f32: 467 MF.addLiveOut(SP::F0); 468 break; 469 case MVT::f64: 470 MF.addLiveOut(SP::D0); 471 break; 472 } 473 474 return ArgValues; 475} 476 477std::pair<SDOperand, SDOperand> 478SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 479 bool RetTyIsSigned, bool isVarArg, unsigned CC, 480 bool isTailCall, SDOperand Callee, 481 ArgListTy &Args, SelectionDAG &DAG) { 482 // Count the size of the outgoing arguments. 483 unsigned ArgsSize = 0; 484 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 485 switch (getValueType(Args[i].Ty)) { 486 default: assert(0 && "Unknown value type!"); 487 case MVT::i1: 488 case MVT::i8: 489 case MVT::i16: 490 case MVT::i32: 491 case MVT::f32: 492 ArgsSize += 4; 493 break; 494 case MVT::i64: 495 case MVT::f64: 496 ArgsSize += 8; 497 break; 498 } 499 } 500 if (ArgsSize > 4*6) 501 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 502 else 503 ArgsSize = 0; 504 505 // Keep stack frames 8-byte aligned. 506 ArgsSize = (ArgsSize+7) & ~7; 507 508 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy())); 509 510 SDOperand StackPtr; 511 std::vector<SDOperand> Stores; 512 std::vector<SDOperand> RegValuesToPass; 513 unsigned ArgOffset = 68; 514 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 515 SDOperand Val = Args[i].Node; 516 MVT::ValueType ObjectVT = Val.getValueType(); 517 SDOperand ValToStore(0, 0); 518 unsigned ObjSize; 519 switch (ObjectVT) { 520 default: assert(0 && "Unhandled argument type!"); 521 case MVT::i1: 522 case MVT::i8: 523 case MVT::i16: { 524 // Promote the integer to 32-bits. If the input type is signed, use a 525 // sign extend, otherwise use a zero extend. 526 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 527 if (Args[i].isSExt) 528 ExtendKind = ISD::SIGN_EXTEND; 529 else if (Args[i].isZExt) 530 ExtendKind = ISD::ZERO_EXTEND; 531 Val = DAG.getNode(ExtendKind, MVT::i32, Val); 532 // FALL THROUGH 533 } 534 case MVT::i32: 535 ObjSize = 4; 536 537 if (RegValuesToPass.size() >= 6) { 538 ValToStore = Val; 539 } else { 540 RegValuesToPass.push_back(Val); 541 } 542 break; 543 case MVT::f32: 544 ObjSize = 4; 545 if (RegValuesToPass.size() >= 6) { 546 ValToStore = Val; 547 } else { 548 // Convert this to a FP value in an int reg. 549 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val); 550 RegValuesToPass.push_back(Val); 551 } 552 break; 553 case MVT::f64: 554 ObjSize = 8; 555 // If we can store this directly into the outgoing slot, do so. We can 556 // do this when all ArgRegs are used and if the outgoing slot is aligned. 557 // FIXME: McGill/misr fails with this. 558 if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 559 ValToStore = Val; 560 break; 561 } 562 563 // Otherwise, convert this to a FP value in int regs. 564 Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val); 565 // FALL THROUGH 566 case MVT::i64: 567 ObjSize = 8; 568 if (RegValuesToPass.size() >= 6) { 569 ValToStore = Val; // Whole thing is passed in memory. 570 break; 571 } 572 573 // Split the value into top and bottom part. Top part goes in a reg. 574 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 575 DAG.getConstant(1, MVT::i32)); 576 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val, 577 DAG.getConstant(0, MVT::i32)); 578 RegValuesToPass.push_back(Hi); 579 580 if (RegValuesToPass.size() >= 6) { 581 ValToStore = Lo; 582 ArgOffset += 4; 583 ObjSize = 4; 584 } else { 585 RegValuesToPass.push_back(Lo); 586 } 587 break; 588 } 589 590 if (ValToStore.Val) { 591 if (!StackPtr.Val) { 592 StackPtr = DAG.getRegister(SP::O6, MVT::i32); 593 } 594 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 595 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 596 Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0)); 597 } 598 ArgOffset += ObjSize; 599 } 600 601 // Emit all stores, make sure the occur before any copies into physregs. 602 if (!Stores.empty()) 603 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size()); 604 605 static const unsigned ArgRegs[] = { 606 SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5 607 }; 608 609 // Build a sequence of copy-to-reg nodes chained together with token chain 610 // and flag operands which copy the outgoing args into O[0-5]. 611 SDOperand InFlag; 612 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 613 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 614 InFlag = Chain.getValue(1); 615 } 616 617 // If the callee is a GlobalAddress node (quite common, every direct call is) 618 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 619 // Likewise ExternalSymbol -> TargetExternalSymbol. 620 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 621 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 622 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 623 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 624 625 std::vector<MVT::ValueType> NodeTys; 626 NodeTys.push_back(MVT::Other); // Returns a chain 627 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 628 SDOperand Ops[] = { Chain, Callee, InFlag }; 629 Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2); 630 InFlag = Chain.getValue(1); 631 632 MVT::ValueType RetTyVT = getValueType(RetTy); 633 SDOperand RetVal; 634 if (RetTyVT != MVT::isVoid) { 635 switch (RetTyVT) { 636 default: assert(0 && "Unknown value type to return!"); 637 case MVT::i1: 638 case MVT::i8: 639 case MVT::i16: { 640 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 641 Chain = RetVal.getValue(1); 642 643 // Add a note to keep track of whether it is sign or zero extended. 644 ISD::NodeType AssertKind = ISD::AssertZext; 645 if (RetTyIsSigned) 646 AssertKind = ISD::AssertSext; 647 RetVal = DAG.getNode(AssertKind, MVT::i32, RetVal, 648 DAG.getValueType(RetTyVT)); 649 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 650 break; 651 } 652 case MVT::i32: 653 RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag); 654 Chain = RetVal.getValue(1); 655 break; 656 case MVT::f32: 657 RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag); 658 Chain = RetVal.getValue(1); 659 break; 660 case MVT::f64: 661 RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag); 662 Chain = RetVal.getValue(1); 663 break; 664 case MVT::i64: 665 SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag); 666 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32, 667 Lo.getValue(2)); 668 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 669 Chain = Hi.getValue(1); 670 break; 671 } 672 } 673 674 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 675 DAG.getConstant(ArgsSize, getPointerTy())); 676 677 return std::make_pair(RetVal, Chain); 678} 679 680// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 681// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 682static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS, 683 ISD::CondCode CC, unsigned &SPCC) { 684 if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 && 685 CC == ISD::SETNE && 686 ((LHS.getOpcode() == SPISD::SELECT_ICC && 687 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 688 (LHS.getOpcode() == SPISD::SELECT_FCC && 689 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 690 isa<ConstantSDNode>(LHS.getOperand(0)) && 691 isa<ConstantSDNode>(LHS.getOperand(1)) && 692 cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 && 693 cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) { 694 SDOperand CMPCC = LHS.getOperand(3); 695 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue(); 696 LHS = CMPCC.getOperand(0); 697 RHS = CMPCC.getOperand(1); 698 } 699} 700 701 702SDOperand SparcTargetLowering:: 703LowerOperation(SDOperand Op, SelectionDAG &DAG) { 704 switch (Op.getOpcode()) { 705 default: assert(0 && "Should not custom lower this!"); 706 case ISD::GlobalTLSAddress: 707 assert(0 && "TLS not implemented for Sparc."); 708 case ISD::GlobalAddress: { 709 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 710 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 711 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA); 712 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA); 713 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 714 } 715 case ISD::ConstantPool: { 716 Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal(); 717 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32, 718 cast<ConstantPoolSDNode>(Op)->getAlignment()); 719 SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP); 720 SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP); 721 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 722 } 723 case ISD::FP_TO_SINT: 724 // Convert the fp value to integer in an FP register. 725 assert(Op.getValueType() == MVT::i32); 726 Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0)); 727 return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op); 728 case ISD::SINT_TO_FP: { 729 assert(Op.getOperand(0).getValueType() == MVT::i32); 730 SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0)); 731 // Convert the int value to FP in an FP register. 732 return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp); 733 } 734 case ISD::BR_CC: { 735 SDOperand Chain = Op.getOperand(0); 736 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 737 SDOperand LHS = Op.getOperand(2); 738 SDOperand RHS = Op.getOperand(3); 739 SDOperand Dest = Op.getOperand(4); 740 unsigned Opc, SPCC = ~0U; 741 742 // If this is a br_cc of a "setcc", and if the setcc got lowered into 743 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 744 LookThroughSetCC(LHS, RHS, CC, SPCC); 745 746 // Get the condition flag. 747 SDOperand CompareFlag; 748 if (LHS.getValueType() == MVT::i32) { 749 std::vector<MVT::ValueType> VTs; 750 VTs.push_back(MVT::i32); 751 VTs.push_back(MVT::Flag); 752 SDOperand Ops[2] = { LHS, RHS }; 753 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 754 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 755 Opc = SPISD::BRICC; 756 } else { 757 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 758 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 759 Opc = SPISD::BRFCC; 760 } 761 return DAG.getNode(Opc, MVT::Other, Chain, Dest, 762 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 763 } 764 case ISD::SELECT_CC: { 765 SDOperand LHS = Op.getOperand(0); 766 SDOperand RHS = Op.getOperand(1); 767 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 768 SDOperand TrueVal = Op.getOperand(2); 769 SDOperand FalseVal = Op.getOperand(3); 770 unsigned Opc, SPCC = ~0U; 771 772 // If this is a select_cc of a "setcc", and if the setcc got lowered into 773 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 774 LookThroughSetCC(LHS, RHS, CC, SPCC); 775 776 SDOperand CompareFlag; 777 if (LHS.getValueType() == MVT::i32) { 778 std::vector<MVT::ValueType> VTs; 779 VTs.push_back(LHS.getValueType()); // subcc returns a value 780 VTs.push_back(MVT::Flag); 781 SDOperand Ops[2] = { LHS, RHS }; 782 CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1); 783 Opc = SPISD::SELECT_ICC; 784 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 785 } else { 786 CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS); 787 Opc = SPISD::SELECT_FCC; 788 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 789 } 790 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 791 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 792 } 793 case ISD::VASTART: { 794 // vastart just stores the address of the VarArgsFrameIndex slot into the 795 // memory location argument. 796 SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32, 797 DAG.getRegister(SP::I6, MVT::i32), 798 DAG.getConstant(VarArgsFrameOffset, MVT::i32)); 799 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2)); 800 return DAG.getStore(Op.getOperand(0), Offset, 801 Op.getOperand(1), SV->getValue(), SV->getOffset()); 802 } 803 case ISD::VAARG: { 804 SDNode *Node = Op.Val; 805 MVT::ValueType VT = Node->getValueType(0); 806 SDOperand InChain = Node->getOperand(0); 807 SDOperand VAListPtr = Node->getOperand(1); 808 SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2)); 809 SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr, 810 SV->getValue(), SV->getOffset()); 811 // Increment the pointer, VAList, to the next vaarg 812 SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 813 DAG.getConstant(MVT::getSizeInBits(VT)/8, 814 getPointerTy())); 815 // Store the incremented VAList to the legalized pointer 816 InChain = DAG.getStore(VAList.getValue(1), NextPtr, 817 VAListPtr, SV->getValue(), SV->getOffset()); 818 // Load the actual argument out of the pointer VAList, unless this is an 819 // f64 load. 820 if (VT != MVT::f64) { 821 return DAG.getLoad(VT, InChain, VAList, NULL, 0); 822 } else { 823 // Otherwise, load it as i64, then do a bitconvert. 824 SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0); 825 std::vector<MVT::ValueType> Tys; 826 Tys.push_back(MVT::f64); 827 Tys.push_back(MVT::Other); 828 // Bit-Convert the value to f64. 829 SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V), 830 V.getValue(1) }; 831 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 832 } 833 } 834 case ISD::DYNAMIC_STACKALLOC: { 835 SDOperand Chain = Op.getOperand(0); // Legalize the chain. 836 SDOperand Size = Op.getOperand(1); // Legalize the size. 837 838 unsigned SPReg = SP::O6; 839 SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32); 840 SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size); // Value 841 Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP); // Output chain 842 843 // The resultant pointer is actually 16 words from the bottom of the stack, 844 // to provide a register spill area. 845 SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP, 846 DAG.getConstant(96, MVT::i32)); 847 std::vector<MVT::ValueType> Tys; 848 Tys.push_back(MVT::i32); 849 Tys.push_back(MVT::Other); 850 SDOperand Ops[2] = { NewVal, Chain }; 851 return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2); 852 } 853 case ISD::RET: { 854 SDOperand Copy; 855 856 switch(Op.getNumOperands()) { 857 default: 858 assert(0 && "Do not know how to return this many arguments!"); 859 abort(); 860 case 1: 861 return SDOperand(); // ret void is legal 862 case 3: { 863 unsigned ArgReg; 864 switch(Op.getOperand(1).getValueType()) { 865 default: assert(0 && "Unknown type to return!"); 866 case MVT::i32: ArgReg = SP::I0; break; 867 case MVT::f32: ArgReg = SP::F0; break; 868 case MVT::f64: ArgReg = SP::D0; break; 869 } 870 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1), 871 SDOperand()); 872 break; 873 } 874 case 5: 875 Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3), 876 SDOperand()); 877 Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1)); 878 break; 879 } 880 return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 881 } 882 // Frame & Return address. Currently unimplemented 883 case ISD::RETURNADDR: break; 884 case ISD::FRAMEADDR: break; 885 } 886 return SDOperand(); 887} 888 889MachineBasicBlock * 890SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 891 MachineBasicBlock *BB) { 892 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 893 unsigned BROpcode; 894 unsigned CC; 895 // Figure out the conditional branch opcode to use for this select_cc. 896 switch (MI->getOpcode()) { 897 default: assert(0 && "Unknown SELECT_CC!"); 898 case SP::SELECT_CC_Int_ICC: 899 case SP::SELECT_CC_FP_ICC: 900 case SP::SELECT_CC_DFP_ICC: 901 BROpcode = SP::BCOND; 902 break; 903 case SP::SELECT_CC_Int_FCC: 904 case SP::SELECT_CC_FP_FCC: 905 case SP::SELECT_CC_DFP_FCC: 906 BROpcode = SP::FBCOND; 907 break; 908 } 909 910 CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue(); 911 912 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 913 // control-flow pattern. The incoming instruction knows the destination vreg 914 // to set, the condition code register to branch on, the true/false values to 915 // select between, and a branch opcode to use. 916 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 917 ilist<MachineBasicBlock>::iterator It = BB; 918 ++It; 919 920 // thisMBB: 921 // ... 922 // TrueVal = ... 923 // [f]bCC copy1MBB 924 // fallthrough --> copy0MBB 925 MachineBasicBlock *thisMBB = BB; 926 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 927 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 928 BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 929 MachineFunction *F = BB->getParent(); 930 F->getBasicBlockList().insert(It, copy0MBB); 931 F->getBasicBlockList().insert(It, sinkMBB); 932 // Update machine-CFG edges by first adding all successors of the current 933 // block to the new block which will contain the Phi node for the select. 934 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(), 935 e = BB->succ_end(); i != e; ++i) 936 sinkMBB->addSuccessor(*i); 937 // Next, remove all successors of the current block, and add the true 938 // and fallthrough blocks as its successors. 939 while(!BB->succ_empty()) 940 BB->removeSuccessor(BB->succ_begin()); 941 BB->addSuccessor(copy0MBB); 942 BB->addSuccessor(sinkMBB); 943 944 // copy0MBB: 945 // %FalseValue = ... 946 // # fallthrough to sinkMBB 947 BB = copy0MBB; 948 949 // Update machine-CFG edges 950 BB->addSuccessor(sinkMBB); 951 952 // sinkMBB: 953 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 954 // ... 955 BB = sinkMBB; 956 BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg()) 957 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 958 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 959 960 delete MI; // The pseudo instruction is gone now. 961 return BB; 962} 963 964//===----------------------------------------------------------------------===// 965// Instruction Selector Implementation 966//===----------------------------------------------------------------------===// 967 968//===--------------------------------------------------------------------===// 969/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine 970/// instructions for SelectionDAG operations. 971/// 972namespace { 973class SparcDAGToDAGISel : public SelectionDAGISel { 974 SparcTargetLowering Lowering; 975 976 /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can 977 /// make the right decision when generating code for different targets. 978 const SparcSubtarget &Subtarget; 979public: 980 SparcDAGToDAGISel(TargetMachine &TM) 981 : SelectionDAGISel(Lowering), Lowering(TM), 982 Subtarget(TM.getSubtarget<SparcSubtarget>()) { 983 } 984 985 SDNode *Select(SDOperand Op); 986 987 // Complex Pattern Selectors. 988 bool SelectADDRrr(SDOperand Op, SDOperand N, SDOperand &R1, SDOperand &R2); 989 bool SelectADDRri(SDOperand Op, SDOperand N, SDOperand &Base, 990 SDOperand &Offset); 991 992 /// InstructionSelectBasicBlock - This callback is invoked by 993 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 994 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 995 996 virtual const char *getPassName() const { 997 return "SPARC DAG->DAG Pattern Instruction Selection"; 998 } 999 1000 // Include the pieces autogenerated from the target description. 1001#include "SparcGenDAGISel.inc" 1002}; 1003} // end anonymous namespace 1004 1005/// InstructionSelectBasicBlock - This callback is invoked by 1006/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 1007void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 1008 DEBUG(BB->dump()); 1009 1010 // Select target instructions for the DAG. 1011 DAG.setRoot(SelectRoot(DAG.getRoot())); 1012 DAG.RemoveDeadNodes(); 1013 1014 // Emit machine code to BB. 1015 ScheduleAndEmitDAG(DAG); 1016} 1017 1018bool SparcDAGToDAGISel::SelectADDRri(SDOperand Op, SDOperand Addr, 1019 SDOperand &Base, SDOperand &Offset) { 1020 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 1021 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1022 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1023 return true; 1024 } 1025 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1026 Addr.getOpcode() == ISD::TargetGlobalAddress) 1027 return false; // direct calls. 1028 1029 if (Addr.getOpcode() == ISD::ADD) { 1030 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 1031 if (Predicate_simm13(CN)) { 1032 if (FrameIndexSDNode *FIN = 1033 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 1034 // Constant offset from frame ref. 1035 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 1036 } else { 1037 Base = Addr.getOperand(0); 1038 } 1039 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 1040 return true; 1041 } 1042 } 1043 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { 1044 Base = Addr.getOperand(1); 1045 Offset = Addr.getOperand(0).getOperand(0); 1046 return true; 1047 } 1048 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { 1049 Base = Addr.getOperand(0); 1050 Offset = Addr.getOperand(1).getOperand(0); 1051 return true; 1052 } 1053 } 1054 Base = Addr; 1055 Offset = CurDAG->getTargetConstant(0, MVT::i32); 1056 return true; 1057} 1058 1059bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Op, SDOperand Addr, 1060 SDOperand &R1, SDOperand &R2) { 1061 if (Addr.getOpcode() == ISD::FrameIndex) return false; 1062 if (Addr.getOpcode() == ISD::TargetExternalSymbol || 1063 Addr.getOpcode() == ISD::TargetGlobalAddress) 1064 return false; // direct calls. 1065 1066 if (Addr.getOpcode() == ISD::ADD) { 1067 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 1068 Predicate_simm13(Addr.getOperand(1).Val)) 1069 return false; // Let the reg+imm pattern catch this! 1070 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || 1071 Addr.getOperand(1).getOpcode() == SPISD::Lo) 1072 return false; // Let the reg+imm pattern catch this! 1073 R1 = Addr.getOperand(0); 1074 R2 = Addr.getOperand(1); 1075 return true; 1076 } 1077 1078 R1 = Addr; 1079 R2 = CurDAG->getRegister(SP::G0, MVT::i32); 1080 return true; 1081} 1082 1083SDNode *SparcDAGToDAGISel::Select(SDOperand Op) { 1084 SDNode *N = Op.Val; 1085 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 1086 N->getOpcode() < SPISD::FIRST_NUMBER) 1087 return NULL; // Already selected. 1088 1089 switch (N->getOpcode()) { 1090 default: break; 1091 case ISD::SDIV: 1092 case ISD::UDIV: { 1093 // FIXME: should use a custom expander to expose the SRA to the dag. 1094 SDOperand DivLHS = N->getOperand(0); 1095 SDOperand DivRHS = N->getOperand(1); 1096 AddToISelQueue(DivLHS); 1097 AddToISelQueue(DivRHS); 1098 1099 // Set the Y register to the high-part. 1100 SDOperand TopPart; 1101 if (N->getOpcode() == ISD::SDIV) { 1102 TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS, 1103 CurDAG->getTargetConstant(31, MVT::i32)), 0); 1104 } else { 1105 TopPart = CurDAG->getRegister(SP::G0, MVT::i32); 1106 } 1107 TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart, 1108 CurDAG->getRegister(SP::G0, MVT::i32)), 0); 1109 1110 // FIXME: Handle div by immediate. 1111 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; 1112 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, 1113 TopPart); 1114 } 1115 case ISD::MULHU: 1116 case ISD::MULHS: { 1117 // FIXME: Handle mul by immediate. 1118 SDOperand MulLHS = N->getOperand(0); 1119 SDOperand MulRHS = N->getOperand(1); 1120 AddToISelQueue(MulLHS); 1121 AddToISelQueue(MulRHS); 1122 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; 1123 SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 1124 MulLHS, MulRHS); 1125 // The high part is in the Y register. 1126 return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1)); 1127 return NULL; 1128 } 1129 } 1130 1131 return SelectCode(Op); 1132} 1133 1134 1135/// createSparcISelDag - This pass converts a legalized DAG into a 1136/// SPARC-specific DAG, ready for instruction scheduling. 1137/// 1138FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) { 1139 return new SparcDAGToDAGISel(TM); 1140} 1141