SparcISelDAGToDAG.cpp revision 9601a86a644fa036168ff173d3539550b2e9206e 
1//===-- SparcISelDAGToDAG.cpp - A dag to dag inst selector for Sparc ------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the SPARC target.
11//
12//===----------------------------------------------------------------------===//
13
14#include "Sparc.h"
15#include "SparcTargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/SelectionDAGISel.h"
23#include "llvm/CodeGen/SSARegMap.h"
24#include "llvm/Target/TargetLowering.h"
25#include "llvm/Support/Debug.h"
26#include <iostream>
27#include <set>
28using namespace llvm;
29
30//===----------------------------------------------------------------------===//
31// TargetLowering Implementation
32//===----------------------------------------------------------------------===//
33
34namespace SPISD {
35  enum {
36    FIRST_NUMBER = ISD::BUILTIN_OP_END+SP::INSTRUCTION_LIST_END,
37    CMPICC,      // Compare two GPR operands, set icc.
38    CMPFCC,      // Compare two FP operands, set fcc.
39    BRICC,       // Branch to dest on icc condition
40    BRFCC,       // Branch to dest on fcc condition
41    SELECT_ICC,  // Select between two values using the current ICC flags.
42    SELECT_FCC,  // Select between two values using the current FCC flags.
43
44    Hi, Lo,      // Hi/Lo operations, typically on a global address.
45
46    FTOI,        // FP to Int within a FP register.
47    ITOF,        // Int to FP within a FP register.
48
49    CALL,        // A call instruction.
50    RET_FLAG,    // Return with a flag operand.
51  };
52}
53
54/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
55/// condition.
56static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
57  switch (CC) {
58  default: assert(0 && "Unknown integer condition code!");
59  case ISD::SETEQ:  return SPCC::ICC_E;
60  case ISD::SETNE:  return SPCC::ICC_NE;
61  case ISD::SETLT:  return SPCC::ICC_L;
62  case ISD::SETGT:  return SPCC::ICC_G;
63  case ISD::SETLE:  return SPCC::ICC_LE;
64  case ISD::SETGE:  return SPCC::ICC_GE;
65  case ISD::SETULT: return SPCC::ICC_CS;
66  case ISD::SETULE: return SPCC::ICC_LEU;
67  case ISD::SETUGT: return SPCC::ICC_GU;
68  case ISD::SETUGE: return SPCC::ICC_CC;
69  }
70}
71
72/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
73/// FCC condition.
74static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
75  switch (CC) {
76  default: assert(0 && "Unknown fp condition code!");
77  case ISD::SETEQ:  return SPCC::FCC_E;
78  case ISD::SETNE:  return SPCC::FCC_NE;
79  case ISD::SETLT:  return SPCC::FCC_L;
80  case ISD::SETGT:  return SPCC::FCC_G;
81  case ISD::SETLE:  return SPCC::FCC_LE;
82  case ISD::SETGE:  return SPCC::FCC_GE;
83  case ISD::SETULT: return SPCC::FCC_UL;
84  case ISD::SETULE: return SPCC::FCC_ULE;
85  case ISD::SETUGT: return SPCC::FCC_UG;
86  case ISD::SETUGE: return SPCC::FCC_UGE;
87  case ISD::SETUO:  return SPCC::FCC_U;
88  case ISD::SETO:   return SPCC::FCC_O;
89  case ISD::SETONE: return SPCC::FCC_LG;
90  case ISD::SETUEQ: return SPCC::FCC_UE;
91  }
92}
93
94namespace {
95  class SparcTargetLowering : public TargetLowering {
96    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
97  public:
98    SparcTargetLowering(TargetMachine &TM);
99    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
100
101    /// computeMaskedBitsForTargetNode - Determine which of the bits specified
102    /// in Mask are known to be either zero or one and return them in the
103    /// KnownZero/KnownOne bitsets.
104    virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
105                                                uint64_t Mask,
106                                                uint64_t &KnownZero,
107                                                uint64_t &KnownOne,
108                                                unsigned Depth = 0) const;
109
110    virtual std::vector<SDOperand>
111      LowerArguments(Function &F, SelectionDAG &DAG);
112    virtual std::pair<SDOperand, SDOperand>
113      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
114                  unsigned CC,
115                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
116                  SelectionDAG &DAG);
117    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
118                                                       MachineBasicBlock *MBB);
119
120    virtual const char *getTargetNodeName(unsigned Opcode) const;
121  };
122}
123
124SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
125  : TargetLowering(TM) {
126
127  // Set up the register classes.
128  addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
129  addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
130  addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
131
132  // Custom legalize GlobalAddress nodes into LO/HI parts.
133  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
134  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
135
136  // Sparc doesn't have sext_inreg, replace them with shl/sra
137  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
138  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
139  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
140
141  // Sparc has no REM operation.
142  setOperationAction(ISD::UREM, MVT::i32, Expand);
143  setOperationAction(ISD::SREM, MVT::i32, Expand);
144
145  // Custom expand fp<->sint
146  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
147  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
148
149  // Expand fp<->uint
150  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
151  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
152
153  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
154  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
155
156  // Turn FP extload into load/fextend
157  setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
158
159  // Sparc has no select or setcc: expand to SELECT_CC.
160  setOperationAction(ISD::SELECT, MVT::i32, Expand);
161  setOperationAction(ISD::SELECT, MVT::f32, Expand);
162  setOperationAction(ISD::SELECT, MVT::f64, Expand);
163  setOperationAction(ISD::SETCC, MVT::i32, Expand);
164  setOperationAction(ISD::SETCC, MVT::f32, Expand);
165  setOperationAction(ISD::SETCC, MVT::f64, Expand);
166
167  // Sparc doesn't have BRCOND either, it has BR_CC.
168  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
169  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
170  setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
171  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
172  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
173  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
174
175  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
176  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
177  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
178
179  // SPARC has no intrinsics for these particular operations.
180  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
181  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
182  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
183
184  setOperationAction(ISD::FSIN , MVT::f64, Expand);
185  setOperationAction(ISD::FCOS , MVT::f64, Expand);
186  setOperationAction(ISD::FSIN , MVT::f32, Expand);
187  setOperationAction(ISD::FCOS , MVT::f32, Expand);
188  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
189  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
190  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
191  setOperationAction(ISD::ROTL , MVT::i32, Expand);
192  setOperationAction(ISD::ROTR , MVT::i32, Expand);
193  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
194  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
195  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196
197  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
198  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
199  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
200
201  // We don't have line number support yet.
202  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
203  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
204  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
205
206  // RET must be custom lowered, to meet ABI requirements
207  setOperationAction(ISD::RET               , MVT::Other, Custom);
208
209  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
210  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
211  // VAARG needs to be lowered to not do unaligned accesses for doubles.
212  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
213
214  // Use the default implementation.
215  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
216  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
217  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
218  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
219  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
220
221  setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
222  setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
223
224  setStackPointerRegisterToSaveRestore(SP::O6);
225
226  if (TM.getSubtarget<SparcSubtarget>().isV9()) {
227    setOperationAction(ISD::CTPOP, MVT::i32, Legal);
228  }
229
230  computeRegisterProperties();
231}
232
233const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
234  switch (Opcode) {
235  default: return 0;
236  case SPISD::CMPICC:     return "SPISD::CMPICC";
237  case SPISD::CMPFCC:     return "SPISD::CMPFCC";
238  case SPISD::BRICC:      return "SPISD::BRICC";
239  case SPISD::BRFCC:      return "SPISD::BRFCC";
240  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
241  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
242  case SPISD::Hi:         return "SPISD::Hi";
243  case SPISD::Lo:         return "SPISD::Lo";
244  case SPISD::FTOI:       return "SPISD::FTOI";
245  case SPISD::ITOF:       return "SPISD::ITOF";
246  case SPISD::CALL:       return "SPISD::CALL";
247  case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
248  }
249}
250
251/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
252/// be zero. Op is expected to be a target specific node. Used by DAG
253/// combiner.
254void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
255                                                         uint64_t Mask,
256                                                         uint64_t &KnownZero,
257                                                         uint64_t &KnownOne,
258                                                         unsigned Depth) const {
259  uint64_t KnownZero2, KnownOne2;
260  KnownZero = KnownOne = 0;   // Don't know anything.
261
262  switch (Op.getOpcode()) {
263  default: break;
264  case SPISD::SELECT_ICC:
265  case SPISD::SELECT_FCC:
266    ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, Depth+1);
267    ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, Depth+1);
268    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
269    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
270
271    // Only known if known in both the LHS and RHS.
272    KnownOne &= KnownOne2;
273    KnownZero &= KnownZero2;
274    break;
275  }
276}
277
278/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
279/// either one or two GPRs, including FP values.  TODO: we should pass FP values
280/// in FP registers for fastcc functions.
281std::vector<SDOperand>
282SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
283  MachineFunction &MF = DAG.getMachineFunction();
284  SSARegMap *RegMap = MF.getSSARegMap();
285  std::vector<SDOperand> ArgValues;
286
287  static const unsigned ArgRegs[] = {
288    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
289  };
290
291  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
292  unsigned ArgOffset = 68;
293
294  SDOperand Root = DAG.getRoot();
295  std::vector<SDOperand> OutChains;
296
297  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
298    MVT::ValueType ObjectVT = getValueType(I->getType());
299
300    switch (ObjectVT) {
301    default: assert(0 && "Unhandled argument type!");
302    case MVT::i1:
303    case MVT::i8:
304    case MVT::i16:
305    case MVT::i32:
306      if (I->use_empty()) {                // Argument is dead.
307        if (CurArgReg < ArgRegEnd) ++CurArgReg;
308        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
309      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
310        unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
311        MF.addLiveIn(*CurArgReg++, VReg);
312        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
313        if (ObjectVT != MVT::i32) {
314          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
315                                                       : ISD::AssertZext;
316          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
317                            DAG.getValueType(ObjectVT));
318          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
319        }
320        ArgValues.push_back(Arg);
321      } else {
322        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
323        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
324        SDOperand Load;
325        if (ObjectVT == MVT::i32) {
326          Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
327        } else {
328          unsigned LoadOp =
329            I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
330
331          // Sparc is big endian, so add an offset based on the ObjectVT.
332          unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
333          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
334                              DAG.getConstant(Offset, MVT::i32));
335          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
336                                DAG.getSrcValue(0), ObjectVT);
337          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
338        }
339        ArgValues.push_back(Load);
340      }
341
342      ArgOffset += 4;
343      break;
344    case MVT::f32:
345      if (I->use_empty()) {                // Argument is dead.
346        if (CurArgReg < ArgRegEnd) ++CurArgReg;
347        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
348      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
349        // FP value is passed in an integer register.
350        unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
351        MF.addLiveIn(*CurArgReg++, VReg);
352        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
353
354        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
355        ArgValues.push_back(Arg);
356      } else {
357        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
358        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
359        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
360        ArgValues.push_back(Load);
361      }
362      ArgOffset += 4;
363      break;
364
365    case MVT::i64:
366    case MVT::f64:
367      if (I->use_empty()) {                // Argument is dead.
368        if (CurArgReg < ArgRegEnd) ++CurArgReg;
369        if (CurArgReg < ArgRegEnd) ++CurArgReg;
370        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
371      } else if (/* FIXME: Apparently this isn't safe?? */
372                 0 && CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
373                 ((CurArgReg-ArgRegs) & 1) == 0) {
374        // If this is a double argument and the whole thing lives on the stack,
375        // and the argument is aligned, load the double straight from the stack.
376        // We can't do a load in cases like void foo([6ints], int,double),
377        // because the double wouldn't be aligned!
378        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
379        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
380        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
381                                        DAG.getSrcValue(0)));
382      } else {
383        SDOperand HiVal;
384        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
385          unsigned VRegHi = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
386          MF.addLiveIn(*CurArgReg++, VRegHi);
387          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
388        } else {
389          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
390          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
391          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
392        }
393
394        SDOperand LoVal;
395        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
396          unsigned VRegLo = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
397          MF.addLiveIn(*CurArgReg++, VRegLo);
398          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
399        } else {
400          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
401          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
402          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
403        }
404
405        // Compose the two halves together into an i64 unit.
406        SDOperand WholeValue =
407          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
408
409        // If we want a double, do a bit convert.
410        if (ObjectVT == MVT::f64)
411          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
412
413        ArgValues.push_back(WholeValue);
414      }
415      ArgOffset += 8;
416      break;
417    }
418  }
419
420  // Store remaining ArgRegs to the stack if this is a varargs function.
421  if (F.getFunctionType()->isVarArg()) {
422    // Remember the vararg offset for the va_start implementation.
423    VarArgsFrameOffset = ArgOffset;
424
425    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
426      unsigned VReg = RegMap->createVirtualRegister(&SP::IntRegsRegClass);
427      MF.addLiveIn(*CurArgReg, VReg);
428      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
429
430      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
431      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
432
433      OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
434                                      Arg, FIPtr, DAG.getSrcValue(0)));
435      ArgOffset += 4;
436    }
437  }
438
439  if (!OutChains.empty())
440    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
441
442  // Finally, inform the code generator which regs we return values in.
443  switch (getValueType(F.getReturnType())) {
444  default: assert(0 && "Unknown type!");
445  case MVT::isVoid: break;
446  case MVT::i1:
447  case MVT::i8:
448  case MVT::i16:
449  case MVT::i32:
450    MF.addLiveOut(SP::I0);
451    break;
452  case MVT::i64:
453    MF.addLiveOut(SP::I0);
454    MF.addLiveOut(SP::I1);
455    break;
456  case MVT::f32:
457    MF.addLiveOut(SP::F0);
458    break;
459  case MVT::f64:
460    MF.addLiveOut(SP::D0);
461    break;
462  }
463
464  return ArgValues;
465}
466
467std::pair<SDOperand, SDOperand>
468SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
469                                 bool isVarArg, unsigned CC,
470                                 bool isTailCall, SDOperand Callee,
471                                 ArgListTy &Args, SelectionDAG &DAG) {
472  MachineFunction &MF = DAG.getMachineFunction();
473  // Count the size of the outgoing arguments.
474  unsigned ArgsSize = 0;
475  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
476    switch (getValueType(Args[i].second)) {
477    default: assert(0 && "Unknown value type!");
478    case MVT::i1:
479    case MVT::i8:
480    case MVT::i16:
481    case MVT::i32:
482    case MVT::f32:
483      ArgsSize += 4;
484      break;
485    case MVT::i64:
486    case MVT::f64:
487      ArgsSize += 8;
488      break;
489    }
490  }
491  if (ArgsSize > 4*6)
492    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
493  else
494    ArgsSize = 0;
495
496  // Keep stack frames 8-byte aligned.
497  ArgsSize = (ArgsSize+7) & ~7;
498
499  Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
500
501  SDOperand StackPtr, NullSV;
502  std::vector<SDOperand> Stores;
503  std::vector<SDOperand> RegValuesToPass;
504  unsigned ArgOffset = 68;
505  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
506    SDOperand Val = Args[i].first;
507    MVT::ValueType ObjectVT = Val.getValueType();
508    SDOperand ValToStore(0, 0);
509    unsigned ObjSize;
510    switch (ObjectVT) {
511    default: assert(0 && "Unhandled argument type!");
512    case MVT::i1:
513    case MVT::i8:
514    case MVT::i16:
515      // Promote the integer to 32-bits.  If the input type is signed, use a
516      // sign extend, otherwise use a zero extend.
517      if (Args[i].second->isSigned())
518        Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
519      else
520        Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
521      // FALL THROUGH
522    case MVT::i32:
523      ObjSize = 4;
524
525      if (RegValuesToPass.size() >= 6) {
526        ValToStore = Val;
527      } else {
528        RegValuesToPass.push_back(Val);
529      }
530      break;
531    case MVT::f32:
532      ObjSize = 4;
533      if (RegValuesToPass.size() >= 6) {
534        ValToStore = Val;
535      } else {
536        // Convert this to a FP value in an int reg.
537        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
538        RegValuesToPass.push_back(Val);
539      }
540      break;
541    case MVT::f64:
542      ObjSize = 8;
543      // If we can store this directly into the outgoing slot, do so.  We can
544      // do this when all ArgRegs are used and if the outgoing slot is aligned.
545      // FIXME: McGill/misr fails with this.
546      if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
547        ValToStore = Val;
548        break;
549      }
550
551      // Otherwise, convert this to a FP value in int regs.
552      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
553      // FALL THROUGH
554    case MVT::i64:
555      ObjSize = 8;
556      if (RegValuesToPass.size() >= 6) {
557        ValToStore = Val;    // Whole thing is passed in memory.
558        break;
559      }
560
561      // Split the value into top and bottom part.  Top part goes in a reg.
562      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
563                                 DAG.getConstant(1, MVT::i32));
564      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
565                                 DAG.getConstant(0, MVT::i32));
566      RegValuesToPass.push_back(Hi);
567
568      if (RegValuesToPass.size() >= 6) {
569        ValToStore = Lo;
570        ArgOffset += 4;
571        ObjSize = 4;
572      } else {
573        RegValuesToPass.push_back(Lo);
574      }
575      break;
576    }
577
578    if (ValToStore.Val) {
579      if (!StackPtr.Val) {
580        StackPtr = DAG.getRegister(SP::O6, MVT::i32);
581        NullSV = DAG.getSrcValue(NULL);
582      }
583      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
584      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
585      Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
586                                   ValToStore, PtrOff, NullSV));
587    }
588    ArgOffset += ObjSize;
589  }
590
591  // Emit all stores, make sure the occur before any copies into physregs.
592  if (!Stores.empty())
593    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
594
595  static const unsigned ArgRegs[] = {
596    SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
597  };
598
599  // Build a sequence of copy-to-reg nodes chained together with token chain
600  // and flag operands which copy the outgoing args into O[0-5].
601  SDOperand InFlag;
602  for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
603    Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
604    InFlag = Chain.getValue(1);
605  }
606
607  // If the callee is a GlobalAddress node (quite common, every direct call is)
608  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
609  // Likewise ExternalSymbol -> TargetExternalSymbol.
610  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
611    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
612  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
613    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
614
615  std::vector<MVT::ValueType> NodeTys;
616  NodeTys.push_back(MVT::Other);   // Returns a chain
617  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
618  std::vector<SDOperand> Ops;
619  Ops.push_back(Chain);
620  Ops.push_back(Callee);
621  if (InFlag.Val)
622    Ops.push_back(InFlag);
623  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops);
624  InFlag = Chain.getValue(1);
625
626  MVT::ValueType RetTyVT = getValueType(RetTy);
627  SDOperand RetVal;
628  if (RetTyVT != MVT::isVoid) {
629    switch (RetTyVT) {
630    default: assert(0 && "Unknown value type to return!");
631    case MVT::i1:
632    case MVT::i8:
633    case MVT::i16:
634      RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
635      Chain = RetVal.getValue(1);
636
637      // Add a note to keep track of whether it is sign or zero extended.
638      RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
639                           MVT::i32, RetVal, DAG.getValueType(RetTyVT));
640      RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
641      break;
642    case MVT::i32:
643      RetVal = DAG.getCopyFromReg(Chain, SP::O0, MVT::i32, InFlag);
644      Chain = RetVal.getValue(1);
645      break;
646    case MVT::f32:
647      RetVal = DAG.getCopyFromReg(Chain, SP::F0, MVT::f32, InFlag);
648      Chain = RetVal.getValue(1);
649      break;
650    case MVT::f64:
651      RetVal = DAG.getCopyFromReg(Chain, SP::D0, MVT::f64, InFlag);
652      Chain = RetVal.getValue(1);
653      break;
654    case MVT::i64:
655      SDOperand Lo = DAG.getCopyFromReg(Chain, SP::O1, MVT::i32, InFlag);
656      SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), SP::O0, MVT::i32,
657                                        Lo.getValue(2));
658      RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
659      Chain = Hi.getValue(1);
660      break;
661    }
662  }
663
664  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
665                      DAG.getConstant(ArgsSize, getPointerTy()));
666
667  return std::make_pair(RetVal, Chain);
668}
669
670// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
671// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
672static void LookThroughSetCC(SDOperand &LHS, SDOperand &RHS,
673                             ISD::CondCode CC, unsigned &SPCC) {
674  if (isa<ConstantSDNode>(RHS) && cast<ConstantSDNode>(RHS)->getValue() == 0 &&
675      CC == ISD::SETNE &&
676      ((LHS.getOpcode() == SPISD::SELECT_ICC &&
677        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
678       (LHS.getOpcode() == SPISD::SELECT_FCC &&
679        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
680      isa<ConstantSDNode>(LHS.getOperand(0)) &&
681      isa<ConstantSDNode>(LHS.getOperand(1)) &&
682      cast<ConstantSDNode>(LHS.getOperand(0))->getValue() == 1 &&
683      cast<ConstantSDNode>(LHS.getOperand(1))->getValue() == 0) {
684    SDOperand CMPCC = LHS.getOperand(3);
685    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getValue();
686    LHS = CMPCC.getOperand(0);
687    RHS = CMPCC.getOperand(1);
688  }
689}
690
691
692SDOperand SparcTargetLowering::
693LowerOperation(SDOperand Op, SelectionDAG &DAG) {
694  switch (Op.getOpcode()) {
695  default: assert(0 && "Should not custom lower this!");
696  case ISD::GlobalAddress: {
697    GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
698    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
699    SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
700    SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
701    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
702  }
703  case ISD::ConstantPool: {
704    Constant *C = cast<ConstantPoolSDNode>(Op)->get();
705    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
706                                  cast<ConstantPoolSDNode>(Op)->getAlignment());
707    SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
708    SDOperand Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
709    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
710  }
711  case ISD::FP_TO_SINT:
712    // Convert the fp value to integer in an FP register.
713    assert(Op.getValueType() == MVT::i32);
714    Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
715    return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
716  case ISD::SINT_TO_FP: {
717    assert(Op.getOperand(0).getValueType() == MVT::i32);
718    SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
719    // Convert the int value to FP in an FP register.
720    return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
721  }
722  case ISD::BR_CC: {
723    SDOperand Chain = Op.getOperand(0);
724    ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
725    SDOperand LHS = Op.getOperand(2);
726    SDOperand RHS = Op.getOperand(3);
727    SDOperand Dest = Op.getOperand(4);
728    unsigned Opc, SPCC = ~0U;
729
730    // If this is a br_cc of a "setcc", and if the setcc got lowered into
731    // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
732    LookThroughSetCC(LHS, RHS, CC, SPCC);
733
734    // Get the condition flag.
735    SDOperand CompareFlag;
736    if (LHS.getValueType() == MVT::i32) {
737      std::vector<MVT::ValueType> VTs;
738      VTs.push_back(MVT::i32);
739      VTs.push_back(MVT::Flag);
740      std::vector<SDOperand> Ops;
741      Ops.push_back(LHS);
742      Ops.push_back(RHS);
743      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
744      if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
745      Opc = SPISD::BRICC;
746    } else {
747      CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
748      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
749      Opc = SPISD::BRFCC;
750    }
751    return DAG.getNode(Opc, MVT::Other, Chain, Dest,
752                       DAG.getConstant(SPCC, MVT::i32), CompareFlag);
753  }
754  case ISD::SELECT_CC: {
755    SDOperand LHS = Op.getOperand(0);
756    SDOperand RHS = Op.getOperand(1);
757    ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
758    SDOperand TrueVal = Op.getOperand(2);
759    SDOperand FalseVal = Op.getOperand(3);
760    unsigned Opc, SPCC = ~0U;
761
762    // If this is a select_cc of a "setcc", and if the setcc got lowered into
763    // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
764    LookThroughSetCC(LHS, RHS, CC, SPCC);
765
766    SDOperand CompareFlag;
767    if (LHS.getValueType() == MVT::i32) {
768      std::vector<MVT::ValueType> VTs;
769      VTs.push_back(LHS.getValueType());   // subcc returns a value
770      VTs.push_back(MVT::Flag);
771      std::vector<SDOperand> Ops;
772      Ops.push_back(LHS);
773      Ops.push_back(RHS);
774      CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
775      Opc = SPISD::SELECT_ICC;
776      if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
777    } else {
778      CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
779      Opc = SPISD::SELECT_FCC;
780      if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
781    }
782    return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
783                       DAG.getConstant(SPCC, MVT::i32), CompareFlag);
784  }
785  case ISD::VASTART: {
786    // vastart just stores the address of the VarArgsFrameIndex slot into the
787    // memory location argument.
788    SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
789                                   DAG.getRegister(SP::I6, MVT::i32),
790                                DAG.getConstant(VarArgsFrameOffset, MVT::i32));
791    return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset,
792                       Op.getOperand(1), Op.getOperand(2));
793  }
794  case ISD::VAARG: {
795    SDNode *Node = Op.Val;
796    MVT::ValueType VT = Node->getValueType(0);
797    SDOperand InChain = Node->getOperand(0);
798    SDOperand VAListPtr = Node->getOperand(1);
799    SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
800                                   Node->getOperand(2));
801    // Increment the pointer, VAList, to the next vaarg
802    SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
803                                    DAG.getConstant(MVT::getSizeInBits(VT)/8,
804                                                    getPointerTy()));
805    // Store the incremented VAList to the legalized pointer
806    InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr,
807                          VAListPtr, Node->getOperand(2));
808    // Load the actual argument out of the pointer VAList, unless this is an
809    // f64 load.
810    if (VT != MVT::f64) {
811      return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0));
812    } else {
813      // Otherwise, load it as i64, then do a bitconvert.
814      SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0));
815      std::vector<MVT::ValueType> Tys;
816      Tys.push_back(MVT::f64);
817      Tys.push_back(MVT::Other);
818      std::vector<SDOperand> Ops;
819      // Bit-Convert the value to f64.
820      Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V));
821      Ops.push_back(V.getValue(1));
822      return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
823    }
824  }
825  case ISD::DYNAMIC_STACKALLOC: {
826    SDOperand Chain = Op.getOperand(0);  // Legalize the chain.
827    SDOperand Size  = Op.getOperand(1);  // Legalize the size.
828
829    unsigned SPReg = SP::O6;
830    SDOperand SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
831    SDOperand NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);    // Value
832    Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP);      // Output chain
833
834    // The resultant pointer is actually 16 words from the bottom of the stack,
835    // to provide a register spill area.
836    SDOperand NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
837                                   DAG.getConstant(96, MVT::i32));
838    std::vector<MVT::ValueType> Tys;
839    Tys.push_back(MVT::i32);
840    Tys.push_back(MVT::Other);
841    std::vector<SDOperand> Ops;
842    Ops.push_back(NewVal);
843    Ops.push_back(Chain);
844    return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
845  }
846  case ISD::RET: {
847    SDOperand Copy;
848
849    switch(Op.getNumOperands()) {
850    default:
851      assert(0 && "Do not know how to return this many arguments!");
852      abort();
853    case 1:
854      return SDOperand(); // ret void is legal
855    case 2: {
856      unsigned ArgReg;
857      switch(Op.getOperand(1).getValueType()) {
858      default: assert(0 && "Unknown type to return!");
859      case MVT::i32: ArgReg = SP::I0; break;
860      case MVT::f32: ArgReg = SP::F0; break;
861      case MVT::f64: ArgReg = SP::D0; break;
862      }
863      Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
864                              SDOperand());
865      break;
866    }
867    case 3:
868      Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2),
869                              SDOperand());
870      Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
871      break;
872    }
873    return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
874  }
875  }
876}
877
878MachineBasicBlock *
879SparcTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
880                                             MachineBasicBlock *BB) {
881  unsigned BROpcode;
882  unsigned CC;
883  // Figure out the conditional branch opcode to use for this select_cc.
884  switch (MI->getOpcode()) {
885  default: assert(0 && "Unknown SELECT_CC!");
886  case SP::SELECT_CC_Int_ICC:
887  case SP::SELECT_CC_FP_ICC:
888  case SP::SELECT_CC_DFP_ICC:
889    BROpcode = SP::BCOND;
890    break;
891  case SP::SELECT_CC_Int_FCC:
892  case SP::SELECT_CC_FP_FCC:
893  case SP::SELECT_CC_DFP_FCC:
894    BROpcode = SP::FBCOND;
895    break;
896  }
897
898  CC = (SPCC::CondCodes)MI->getOperand(3).getImmedValue();
899
900  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
901  // control-flow pattern.  The incoming instruction knows the destination vreg
902  // to set, the condition code register to branch on, the true/false values to
903  // select between, and a branch opcode to use.
904  const BasicBlock *LLVM_BB = BB->getBasicBlock();
905  ilist<MachineBasicBlock>::iterator It = BB;
906  ++It;
907
908  //  thisMBB:
909  //  ...
910  //   TrueVal = ...
911  //   [f]bCC copy1MBB
912  //   fallthrough --> copy0MBB
913  MachineBasicBlock *thisMBB = BB;
914  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
915  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
916  BuildMI(BB, BROpcode, 2).addMBB(sinkMBB).addImm(CC);
917  MachineFunction *F = BB->getParent();
918  F->getBasicBlockList().insert(It, copy0MBB);
919  F->getBasicBlockList().insert(It, sinkMBB);
920  // Update machine-CFG edges
921  BB->addSuccessor(copy0MBB);
922  BB->addSuccessor(sinkMBB);
923
924  //  copy0MBB:
925  //   %FalseValue = ...
926  //   # fallthrough to sinkMBB
927  BB = copy0MBB;
928
929  // Update machine-CFG edges
930  BB->addSuccessor(sinkMBB);
931
932  //  sinkMBB:
933  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
934  //  ...
935  BB = sinkMBB;
936  BuildMI(BB, SP::PHI, 4, MI->getOperand(0).getReg())
937    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
938    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
939
940  delete MI;   // The pseudo instruction is gone now.
941  return BB;
942}
943
944//===----------------------------------------------------------------------===//
945// Instruction Selector Implementation
946//===----------------------------------------------------------------------===//
947
948//===--------------------------------------------------------------------===//
949/// SparcDAGToDAGISel - SPARC specific code to select SPARC machine
950/// instructions for SelectionDAG operations.
951///
952namespace {
953class SparcDAGToDAGISel : public SelectionDAGISel {
954  SparcTargetLowering Lowering;
955
956  /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
957  /// make the right decision when generating code for different targets.
958  const SparcSubtarget &Subtarget;
959public:
960  SparcDAGToDAGISel(TargetMachine &TM)
961    : SelectionDAGISel(Lowering), Lowering(TM),
962      Subtarget(TM.getSubtarget<SparcSubtarget>()) {
963  }
964
965  void Select(SDOperand &Result, SDOperand Op);
966
967  // Complex Pattern Selectors.
968  bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
969  bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
970
971  /// InstructionSelectBasicBlock - This callback is invoked by
972  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
973  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
974
975  virtual const char *getPassName() const {
976    return "SPARC DAG->DAG Pattern Instruction Selection";
977  }
978
979  // Include the pieces autogenerated from the target description.
980#include "SparcGenDAGISel.inc"
981};
982}  // end anonymous namespace
983
984/// InstructionSelectBasicBlock - This callback is invoked by
985/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
986void SparcDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
987  DEBUG(BB->dump());
988
989  // Select target instructions for the DAG.
990  DAG.setRoot(SelectRoot(DAG.getRoot()));
991  CodeGenMap.clear();
992  DAG.RemoveDeadNodes();
993
994  // Emit machine code to BB.
995  ScheduleAndEmitDAG(DAG);
996}
997
998bool SparcDAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
999                                     SDOperand &Offset) {
1000  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
1001    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1002    Offset = CurDAG->getTargetConstant(0, MVT::i32);
1003    return true;
1004  }
1005  if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1006      Addr.getOpcode() == ISD::TargetGlobalAddress)
1007    return false;  // direct calls.
1008
1009  if (Addr.getOpcode() == ISD::ADD) {
1010    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
1011      if (Predicate_simm13(CN)) {
1012        if (FrameIndexSDNode *FIN =
1013                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
1014          // Constant offset from frame ref.
1015          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
1016        } else {
1017          Base = Addr.getOperand(0);
1018        }
1019        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
1020        return true;
1021      }
1022    }
1023    if (Addr.getOperand(0).getOpcode() == SPISD::Lo) {
1024      Base = Addr.getOperand(1);
1025      Offset = Addr.getOperand(0).getOperand(0);
1026      return true;
1027    }
1028    if (Addr.getOperand(1).getOpcode() == SPISD::Lo) {
1029      Base = Addr.getOperand(0);
1030      Offset = Addr.getOperand(1).getOperand(0);
1031      return true;
1032    }
1033  }
1034  Base = Addr;
1035  Offset = CurDAG->getTargetConstant(0, MVT::i32);
1036  return true;
1037}
1038
1039bool SparcDAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
1040                                     SDOperand &R2) {
1041  if (Addr.getOpcode() == ISD::FrameIndex) return false;
1042  if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
1043      Addr.getOpcode() == ISD::TargetGlobalAddress)
1044    return false;  // direct calls.
1045
1046  if (Addr.getOpcode() == ISD::ADD) {
1047    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
1048        Predicate_simm13(Addr.getOperand(1).Val))
1049      return false;  // Let the reg+imm pattern catch this!
1050    if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
1051        Addr.getOperand(1).getOpcode() == SPISD::Lo)
1052      return false;  // Let the reg+imm pattern catch this!
1053    R1 = Addr.getOperand(0);
1054    R2 = Addr.getOperand(1);
1055    return true;
1056  }
1057
1058  R1 = Addr;
1059  R2 = CurDAG->getRegister(SP::G0, MVT::i32);
1060  return true;
1061}
1062
1063void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
1064  SDNode *N = Op.Val;
1065  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
1066      N->getOpcode() < SPISD::FIRST_NUMBER) {
1067    Result = Op;
1068    return;   // Already selected.
1069  }
1070
1071                 // If this has already been converted, use it.
1072  std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
1073  if (CGMI != CodeGenMap.end()) {
1074    Result = CGMI->second;
1075    return;
1076  }
1077
1078  switch (N->getOpcode()) {
1079  default: break;
1080  case ISD::SDIV:
1081  case ISD::UDIV: {
1082    // FIXME: should use a custom expander to expose the SRA to the dag.
1083    SDOperand DivLHS, DivRHS;
1084    Select(DivLHS, N->getOperand(0));
1085    Select(DivRHS, N->getOperand(1));
1086
1087    // Set the Y register to the high-part.
1088    SDOperand TopPart;
1089    if (N->getOpcode() == ISD::SDIV) {
1090      TopPart = SDOperand(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
1091                                   CurDAG->getTargetConstant(31, MVT::i32)), 0);
1092    } else {
1093      TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
1094    }
1095    TopPart = SDOperand(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
1096                                     CurDAG->getRegister(SP::G0, MVT::i32)), 0);
1097
1098    // FIXME: Handle div by immediate.
1099    unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
1100    Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
1101    return;
1102  }
1103  case ISD::MULHU:
1104  case ISD::MULHS: {
1105    // FIXME: Handle mul by immediate.
1106    SDOperand MulLHS, MulRHS;
1107    Select(MulLHS, N->getOperand(0));
1108    Select(MulRHS, N->getOperand(1));
1109    unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
1110    SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
1111                                        MulLHS, MulRHS);
1112    // The high part is in the Y register.
1113    Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
1114    return;
1115  }
1116  }
1117
1118  SelectCode(Result, Op);
1119}
1120
1121
1122/// createSparcISelDag - This pass converts a legalized DAG into a
1123/// SPARC-specific DAG, ready for instruction scheduling.
1124///
1125FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
1126  return new SparcDAGToDAGISel(TM);
1127}
1128