SparcISelDAGToDAG.cpp revision acc398c195a697795bff3245943d104eb19192b9 
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines an instruction selector for the V8 target
11//
12//===----------------------------------------------------------------------===//
13
14#include "SparcV8.h"
15#include "SparcV8TargetMachine.h"
16#include "llvm/DerivedTypes.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/MachineFrameInfo.h"
19#include "llvm/CodeGen/MachineFunction.h"
20#include "llvm/CodeGen/MachineInstrBuilder.h"
21#include "llvm/CodeGen/SelectionDAG.h"
22#include "llvm/CodeGen/SelectionDAGISel.h"
23#include "llvm/CodeGen/SSARegMap.h"
24#include "llvm/Target/TargetLowering.h"
25#include "llvm/Support/Debug.h"
26#include <iostream>
27using namespace llvm;
28
29//===----------------------------------------------------------------------===//
30// TargetLowering Implementation
31//===----------------------------------------------------------------------===//
32
33namespace V8ISD {
34  enum {
35    FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END,
36    CMPICC,   // Compare two GPR operands, set icc.
37    CMPFCC,   // Compare two FP operands, set fcc.
38    BRICC,    // Branch to dest on icc condition
39    BRFCC,    // Branch to dest on fcc condition
40
41    Hi, Lo,   // Hi/Lo operations, typically on a global address.
42
43    FTOI,     // FP to Int within a FP register.
44    ITOF,     // Int to FP within a FP register.
45
46    SELECT_ICC, // Select between two values using the current ICC flags.
47    SELECT_FCC, // Select between two values using the current FCC flags.
48
49    RET_FLAG,   // Return with a flag operand.
50  };
51}
52
53namespace {
54  class SparcV8TargetLowering : public TargetLowering {
55    int VarArgsFrameOffset;   // Frame offset to start of varargs area.
56  public:
57    SparcV8TargetLowering(TargetMachine &TM);
58    virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
59    virtual std::vector<SDOperand>
60      LowerArguments(Function &F, SelectionDAG &DAG);
61    virtual std::pair<SDOperand, SDOperand>
62      LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
63                  unsigned CC,
64                  bool isTailCall, SDOperand Callee, ArgListTy &Args,
65                  SelectionDAG &DAG);
66
67    virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op,
68                                    SelectionDAG &DAG);
69    virtual std::pair<SDOperand, SDOperand>
70      LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
71                              SelectionDAG &DAG);
72    virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
73                                                       MachineBasicBlock *MBB);
74
75    virtual const char *getTargetNodeName(unsigned Opcode) const;
76  };
77}
78
79SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
80  : TargetLowering(TM) {
81
82  // Set up the register classes.
83  addRegisterClass(MVT::i32, V8::IntRegsRegisterClass);
84  addRegisterClass(MVT::f32, V8::FPRegsRegisterClass);
85  addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass);
86
87  // Custom legalize GlobalAddress nodes into LO/HI parts.
88  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
89  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
90
91  // Sparc doesn't have sext_inreg, replace them with shl/sra
92  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
93  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
94  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
95
96  // Sparc has no REM operation.
97  setOperationAction(ISD::UREM, MVT::i32, Expand);
98  setOperationAction(ISD::SREM, MVT::i32, Expand);
99
100  // Custom expand fp<->sint
101  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
102  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
103
104  // Expand fp<->uint
105  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
106  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
107
108  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
109  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
110
111  // Turn FP extload into load/fextend
112  setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
113
114  // Sparc has no select or setcc: expand to SELECT_CC.
115  setOperationAction(ISD::SELECT, MVT::i32, Expand);
116  setOperationAction(ISD::SELECT, MVT::f32, Expand);
117  setOperationAction(ISD::SELECT, MVT::f64, Expand);
118  setOperationAction(ISD::SETCC, MVT::i32, Expand);
119  setOperationAction(ISD::SETCC, MVT::f32, Expand);
120  setOperationAction(ISD::SETCC, MVT::f64, Expand);
121
122  // Sparc doesn't have BRCOND either, it has BR_CC.
123  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
124  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
125  setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand);
126  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
127  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
128  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
129
130  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
131  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
132  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
133
134  // V8 has no intrinsics for these particular operations.
135  setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
136  setOperationAction(ISD::MEMSET, MVT::Other, Expand);
137  setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
138
139  setOperationAction(ISD::FSIN , MVT::f64, Expand);
140  setOperationAction(ISD::FCOS , MVT::f64, Expand);
141  setOperationAction(ISD::FSIN , MVT::f32, Expand);
142  setOperationAction(ISD::FCOS , MVT::f32, Expand);
143  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
144  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
145  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
146  setOperationAction(ISD::ROTL , MVT::i32, Expand);
147  setOperationAction(ISD::ROTR , MVT::i32, Expand);
148  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
149
150  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
151  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
152  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
153
154  // We don't have line number support yet.
155  setOperationAction(ISD::LOCATION, MVT::Other, Expand);
156  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
157  setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
158
159  // VASTART needs to be custom lowered to use the VarArgsFrameIndex
160  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
161
162  // Use the default implementation.
163  setOperationAction(ISD::VAARG             , MVT::Other, Expand);
164  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
165  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
166  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
167  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
168  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
169
170  setSchedulingPreference(SchedulingForLatency);
171  setStackPointerRegisterToSaveRestore(V8::O6);
172
173  computeRegisterProperties();
174}
175
176const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const {
177  switch (Opcode) {
178  default: return 0;
179  case V8ISD::CMPICC:     return "V8ISD::CMPICC";
180  case V8ISD::CMPFCC:     return "V8ISD::CMPFCC";
181  case V8ISD::BRICC:      return "V8ISD::BRICC";
182  case V8ISD::BRFCC:      return "V8ISD::BRFCC";
183  case V8ISD::Hi:         return "V8ISD::Hi";
184  case V8ISD::Lo:         return "V8ISD::Lo";
185  case V8ISD::FTOI:       return "V8ISD::FTOI";
186  case V8ISD::ITOF:       return "V8ISD::ITOF";
187  case V8ISD::SELECT_ICC: return "V8ISD::SELECT_ICC";
188  case V8ISD::SELECT_FCC: return "V8ISD::SELECT_FCC";
189  case V8ISD::RET_FLAG:   return "V8ISD::RET_FLAG";
190  }
191}
192
193/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
194/// either one or two GPRs, including FP values.  TODO: we should pass FP values
195/// in FP registers for fastcc functions.
196std::vector<SDOperand>
197SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
198  MachineFunction &MF = DAG.getMachineFunction();
199  SSARegMap *RegMap = MF.getSSARegMap();
200  std::vector<SDOperand> ArgValues;
201
202  static const unsigned ArgRegs[] = {
203    V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5
204  };
205
206  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
207  unsigned ArgOffset = 68;
208
209  SDOperand Root = DAG.getRoot();
210  std::vector<SDOperand> OutChains;
211
212  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
213    MVT::ValueType ObjectVT = getValueType(I->getType());
214
215    switch (ObjectVT) {
216    default: assert(0 && "Unhandled argument type!");
217    case MVT::i1:
218    case MVT::i8:
219    case MVT::i16:
220    case MVT::i32:
221      if (I->use_empty()) {                // Argument is dead.
222        if (CurArgReg < ArgRegEnd) ++CurArgReg;
223        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
224      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
225        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
226        MF.addLiveIn(*CurArgReg++, VReg);
227        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
228        if (ObjectVT != MVT::i32) {
229          unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
230                                                       : ISD::AssertZext;
231          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
232                            DAG.getValueType(ObjectVT));
233          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
234        }
235        ArgValues.push_back(Arg);
236      } else {
237        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
238        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
239        SDOperand Load;
240        if (ObjectVT == MVT::i32) {
241          Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
242        } else {
243          unsigned LoadOp =
244            I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
245
246          // Sparc is big endian, so add an offset based on the ObjectVT.
247          unsigned Offset = 4-std::max(1U, MVT::getSizeInBits(ObjectVT)/8);
248          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
249                              DAG.getConstant(Offset, MVT::i32));
250          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
251                                DAG.getSrcValue(0), ObjectVT);
252          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
253        }
254        ArgValues.push_back(Load);
255      }
256
257      ArgOffset += 4;
258      break;
259    case MVT::f32:
260      if (I->use_empty()) {                // Argument is dead.
261        if (CurArgReg < ArgRegEnd) ++CurArgReg;
262        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
263      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
264        // FP value is passed in an integer register.
265        unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
266        MF.addLiveIn(*CurArgReg++, VReg);
267        SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
268
269        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
270        ArgValues.push_back(Arg);
271      } else {
272        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
273        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
274        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
275        ArgValues.push_back(Load);
276      }
277      ArgOffset += 4;
278      break;
279
280    case MVT::i64:
281    case MVT::f64:
282      if (I->use_empty()) {                // Argument is dead.
283        if (CurArgReg < ArgRegEnd) ++CurArgReg;
284        if (CurArgReg < ArgRegEnd) ++CurArgReg;
285        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
286      } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 &&
287                 ((CurArgReg-ArgRegs) & 1) == 0) {
288        // If this is a double argument and the whole thing lives on the stack,
289        // and the argument is aligned, load the double straight from the stack.
290        // We can't do a load in cases like void foo([6ints], int,double),
291        // because the double wouldn't be aligned!
292        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
293        SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
294        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
295                                        DAG.getSrcValue(0)));
296      } else {
297        SDOperand HiVal;
298        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
299          unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
300          MF.addLiveIn(*CurArgReg++, VRegHi);
301          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
302        } else {
303          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
304          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
305          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
306        }
307
308        SDOperand LoVal;
309        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
310          unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
311          MF.addLiveIn(*CurArgReg++, VRegLo);
312          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
313        } else {
314          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
315          SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
316          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
317        }
318
319        // Compose the two halves together into an i64 unit.
320        SDOperand WholeValue =
321          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
322
323        // If we want a double, do a bit convert.
324        if (ObjectVT == MVT::f64)
325          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
326
327        ArgValues.push_back(WholeValue);
328      }
329      ArgOffset += 8;
330      break;
331    }
332  }
333
334  // Store remaining ArgRegs to the stack if this is a varargs function.
335  if (F.getFunctionType()->isVarArg()) {
336    // Remember the vararg offset for the va_start implementation.
337    VarArgsFrameOffset = ArgOffset;
338
339    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
340      unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass);
341      MF.addLiveIn(*CurArgReg, VReg);
342      SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
343
344      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
345      SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
346
347      OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
348                                      Arg, FIPtr, DAG.getSrcValue(0)));
349      ArgOffset += 4;
350    }
351  }
352
353  if (!OutChains.empty())
354    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
355
356  // Finally, inform the code generator which regs we return values in.
357  switch (getValueType(F.getReturnType())) {
358  default: assert(0 && "Unknown type!");
359  case MVT::isVoid: break;
360  case MVT::i1:
361  case MVT::i8:
362  case MVT::i16:
363  case MVT::i32:
364    MF.addLiveOut(V8::I0);
365    break;
366  case MVT::i64:
367    MF.addLiveOut(V8::I0);
368    MF.addLiveOut(V8::I1);
369    break;
370  case MVT::f32:
371    MF.addLiveOut(V8::F0);
372    break;
373  case MVT::f64:
374    MF.addLiveOut(V8::D0);
375    break;
376  }
377
378  return ArgValues;
379}
380
381std::pair<SDOperand, SDOperand>
382SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
383                                   bool isVarArg, unsigned CC,
384                                   bool isTailCall, SDOperand Callee,
385                                   ArgListTy &Args, SelectionDAG &DAG) {
386  MachineFunction &MF = DAG.getMachineFunction();
387  // Count the size of the outgoing arguments.
388  unsigned ArgsSize = 0;
389  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
390    switch (getValueType(Args[i].second)) {
391    default: assert(0 && "Unknown value type!");
392    case MVT::i1:
393    case MVT::i8:
394    case MVT::i16:
395    case MVT::i32:
396    case MVT::f32:
397      ArgsSize += 4;
398      break;
399    case MVT::i64:
400    case MVT::f64:
401      ArgsSize += 8;
402      break;
403    }
404  }
405  if (ArgsSize > 4*6)
406    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
407  else
408    ArgsSize = 0;
409
410  // Keep stack frames 8-byte aligned.
411  ArgsSize = (ArgsSize+7) & ~7;
412
413  Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
414                      DAG.getConstant(ArgsSize, getPointerTy()));
415
416  SDOperand StackPtr, NullSV;
417  std::vector<SDOperand> Stores;
418  std::vector<SDOperand> RegValuesToPass;
419  unsigned ArgOffset = 68;
420  for (unsigned i = 0, e = Args.size(); i != e; ++i) {
421    SDOperand Val = Args[i].first;
422    MVT::ValueType ObjectVT = Val.getValueType();
423    SDOperand ValToStore(0, 0);
424    unsigned ObjSize;
425    switch (ObjectVT) {
426    default: assert(0 && "Unhandled argument type!");
427    case MVT::i1:
428    case MVT::i8:
429    case MVT::i16:
430      // Promote the integer to 32-bits.  If the input type is signed, use a
431      // sign extend, otherwise use a zero extend.
432      if (Args[i].second->isSigned())
433        Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val);
434      else
435        Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val);
436      // FALL THROUGH
437    case MVT::i32:
438      ObjSize = 4;
439
440      if (RegValuesToPass.size() >= 6) {
441        ValToStore = Val;
442      } else {
443        RegValuesToPass.push_back(Val);
444      }
445      break;
446    case MVT::f32:
447      ObjSize = 4;
448      if (RegValuesToPass.size() >= 6) {
449        ValToStore = Val;
450      } else {
451        // Convert this to a FP value in an int reg.
452        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
453        RegValuesToPass.push_back(Val);
454      }
455      break;
456    case MVT::f64:
457      ObjSize = 8;
458      // If we can store this directly into the outgoing slot, do so.  We can
459      // do this when all ArgRegs are used and if the outgoing slot is aligned.
460      // FIXME: McGill/misr fails with this.
461      if (0 && RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) {
462        ValToStore = Val;
463        break;
464      }
465
466      // Otherwise, convert this to a FP value in int regs.
467      Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Val);
468      // FALL THROUGH
469    case MVT::i64:
470      ObjSize = 8;
471      if (RegValuesToPass.size() >= 6) {
472        ValToStore = Val;    // Whole thing is passed in memory.
473        break;
474      }
475
476      // Split the value into top and bottom part.  Top part goes in a reg.
477      SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
478                                 DAG.getConstant(1, MVT::i32));
479      SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
480                                 DAG.getConstant(0, MVT::i32));
481      RegValuesToPass.push_back(Hi);
482
483      if (RegValuesToPass.size() >= 6) {
484        ValToStore = Lo;
485        ArgOffset += 4;
486        ObjSize = 4;
487      } else {
488        RegValuesToPass.push_back(Lo);
489      }
490      break;
491    }
492
493    if (ValToStore.Val) {
494      if (!StackPtr.Val) {
495        StackPtr = DAG.getRegister(V8::O6, MVT::i32);
496        NullSV = DAG.getSrcValue(NULL);
497      }
498      SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
499      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
500      Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
501                                   ValToStore, PtrOff, NullSV));
502    }
503    ArgOffset += ObjSize;
504  }
505
506  // Emit all stores, make sure the occur before any copies into physregs.
507  if (!Stores.empty())
508    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
509
510  static const unsigned ArgRegs[] = {
511    V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5
512  };
513
514  // Build a sequence of copy-to-reg nodes chained together with token chain
515  // and flag operands which copy the outgoing args into O[0-5].
516  SDOperand InFlag;
517  for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) {
518    Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag);
519    InFlag = Chain.getValue(1);
520  }
521
522  // If the callee is a GlobalAddress node (quite common, every direct call is)
523  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
524  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
525    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
526
527  std::vector<MVT::ValueType> NodeTys;
528  NodeTys.push_back(MVT::Other);   // Returns a chain
529  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
530  if (InFlag.Val)
531    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0);
532  else
533    Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0);
534  InFlag = Chain.getValue(1);
535
536  MVT::ValueType RetTyVT = getValueType(RetTy);
537  SDOperand RetVal;
538  if (RetTyVT != MVT::isVoid) {
539    switch (RetTyVT) {
540    default: assert(0 && "Unknown value type to return!");
541    case MVT::i1:
542    case MVT::i8:
543    case MVT::i16:
544      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
545      Chain = RetVal.getValue(1);
546
547      // Add a note to keep track of whether it is sign or zero extended.
548      RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext,
549                           MVT::i32, RetVal, DAG.getValueType(RetTyVT));
550      RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
551      break;
552    case MVT::i32:
553      RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag);
554      Chain = RetVal.getValue(1);
555      break;
556    case MVT::f32:
557      RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag);
558      Chain = RetVal.getValue(1);
559      break;
560    case MVT::f64:
561      RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag);
562      Chain = RetVal.getValue(1);
563      break;
564    case MVT::i64:
565      SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag);
566      SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32,
567                                        Lo.getValue(2));
568      RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi);
569      Chain = Hi.getValue(1);
570      break;
571    }
572  }
573
574  Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
575                      DAG.getConstant(ArgsSize, getPointerTy()));
576
577  return std::make_pair(RetVal, Chain);
578}
579
580SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op,
581                                               SelectionDAG &DAG) {
582  SDOperand Copy;
583  switch (Op.getValueType()) {
584  default: assert(0 && "Unknown type to return!");
585  case MVT::i32:
586    Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand());
587    break;
588  case MVT::f32:
589    Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand());
590    break;
591  case MVT::f64:
592    Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand());
593    break;
594  case MVT::i64:
595    SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
596                               DAG.getConstant(1, MVT::i32));
597    SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op,
598                               DAG.getConstant(0, MVT::i32));
599    Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand());
600    Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1));
601    break;
602  }
603  return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
604}
605
606std::pair<SDOperand, SDOperand> SparcV8TargetLowering::
607LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
608                        SelectionDAG &DAG) {
609  assert(0 && "Unimp");
610  abort();
611}
612
613SDOperand SparcV8TargetLowering::
614LowerOperation(SDOperand Op, SelectionDAG &DAG) {
615  switch (Op.getOpcode()) {
616  default: assert(0 && "Should not custom lower this!");
617  case ISD::GlobalAddress: {
618    GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
619    SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
620    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA);
621    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA);
622    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
623  }
624  case ISD::ConstantPool: {
625    Constant *C = cast<ConstantPoolSDNode>(Op)->get();
626    SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32);
627    SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP);
628    SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP);
629    return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
630  }
631  case ISD::FP_TO_SINT:
632    // Convert the fp value to integer in an FP register.
633    assert(Op.getValueType() == MVT::i32);
634    Op = DAG.getNode(V8ISD::FTOI, MVT::f32, Op.getOperand(0));
635    return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
636  case ISD::SINT_TO_FP: {
637    assert(Op.getOperand(0).getValueType() == MVT::i32);
638    SDOperand Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
639    // Convert the int value to FP in an FP register.
640    return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Tmp);
641  }
642  case ISD::BR_CC: {
643    SDOperand Chain = Op.getOperand(0);
644    SDOperand CC = Op.getOperand(1);
645    SDOperand LHS = Op.getOperand(2);
646    SDOperand RHS = Op.getOperand(3);
647    SDOperand Dest = Op.getOperand(4);
648
649    // Get the condition flag.
650    if (LHS.getValueType() == MVT::i32) {
651      std::vector<MVT::ValueType> VTs;
652      VTs.push_back(MVT::i32);
653      VTs.push_back(MVT::Flag);
654      std::vector<SDOperand> Ops;
655      Ops.push_back(LHS);
656      Ops.push_back(RHS);
657      SDOperand Cond = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
658      return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond);
659    } else {
660      SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
661      return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond);
662    }
663  }
664  case ISD::SELECT_CC: {
665    SDOperand LHS = Op.getOperand(0);
666    SDOperand RHS = Op.getOperand(1);
667    unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
668    SDOperand TrueVal = Op.getOperand(2);
669    SDOperand FalseVal = Op.getOperand(3);
670
671    SDOperand CompareFlag;
672    unsigned Opc;
673    if (LHS.getValueType() == MVT::i32) {
674      std::vector<MVT::ValueType> VTs;
675      VTs.push_back(LHS.getValueType());   // subcc returns a value
676      VTs.push_back(MVT::Flag);
677      std::vector<SDOperand> Ops;
678      Ops.push_back(LHS);
679      Ops.push_back(RHS);
680      CompareFlag = DAG.getNode(V8ISD::CMPICC, VTs, Ops).getValue(1);
681      Opc = V8ISD::SELECT_ICC;
682    } else {
683      CompareFlag = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS);
684      Opc = V8ISD::SELECT_FCC;
685    }
686    return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
687                       DAG.getConstant(CC, MVT::i32), CompareFlag);
688  }
689  case ISD::VASTART: {
690    // vastart just stores the address of the VarArgsFrameIndex slot into the
691    // memory location argument.
692    SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
693                                   DAG.getRegister(V8::I6, MVT::i32),
694                                   DAG.getConstant(VarArgsFrameOffset, MVT::i32));
695    return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset,
696                       Op.getOperand(1), Op.getOperand(2));
697  }
698  }
699}
700
701MachineBasicBlock *
702SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
703                                               MachineBasicBlock *BB) {
704  unsigned BROpcode;
705  // Figure out the conditional branch opcode to use for this select_cc.
706  switch (MI->getOpcode()) {
707  default: assert(0 && "Unknown SELECT_CC!");
708  case V8::SELECT_CC_Int_ICC:
709  case V8::SELECT_CC_FP_ICC:
710  case V8::SELECT_CC_DFP_ICC:
711    // Integer compare.
712    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
713    default: assert(0 && "Unknown integer condition code!");
714    case ISD::SETEQ:  BROpcode = V8::BE; break;
715    case ISD::SETNE:  BROpcode = V8::BNE; break;
716    case ISD::SETLT:  BROpcode = V8::BL; break;
717    case ISD::SETGT:  BROpcode = V8::BG; break;
718    case ISD::SETLE:  BROpcode = V8::BLE; break;
719    case ISD::SETGE:  BROpcode = V8::BGE; break;
720    case ISD::SETULT: BROpcode = V8::BCS; break;
721    case ISD::SETULE: BROpcode = V8::BLEU; break;
722    case ISD::SETUGT: BROpcode = V8::BGU; break;
723    case ISD::SETUGE: BROpcode = V8::BCC; break;
724    }
725    break;
726  case V8::SELECT_CC_Int_FCC:
727  case V8::SELECT_CC_FP_FCC:
728  case V8::SELECT_CC_DFP_FCC:
729    // FP compare.
730    switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) {
731    default: assert(0 && "Unknown fp condition code!");
732    case ISD::SETEQ:  BROpcode = V8::FBE; break;
733    case ISD::SETNE:  BROpcode = V8::FBNE; break;
734    case ISD::SETLT:  BROpcode = V8::FBL; break;
735    case ISD::SETGT:  BROpcode = V8::FBG; break;
736    case ISD::SETLE:  BROpcode = V8::FBLE; break;
737    case ISD::SETGE:  BROpcode = V8::FBGE; break;
738    case ISD::SETULT: BROpcode = V8::FBUL; break;
739    case ISD::SETULE: BROpcode = V8::FBULE; break;
740    case ISD::SETUGT: BROpcode = V8::FBUG; break;
741    case ISD::SETUGE: BROpcode = V8::FBUGE; break;
742    case ISD::SETUO:  BROpcode = V8::FBU; break;
743    case ISD::SETO:   BROpcode = V8::FBO; break;
744    case ISD::SETONE: BROpcode = V8::FBLG; break;
745    case ISD::SETUEQ: BROpcode = V8::FBUE; break;
746    }
747    break;
748  }
749
750  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
751  // control-flow pattern.  The incoming instruction knows the destination vreg
752  // to set, the condition code register to branch on, the true/false values to
753  // select between, and a branch opcode to use.
754  const BasicBlock *LLVM_BB = BB->getBasicBlock();
755  ilist<MachineBasicBlock>::iterator It = BB;
756  ++It;
757
758  //  thisMBB:
759  //  ...
760  //   TrueVal = ...
761  //   [f]bCC copy1MBB
762  //   fallthrough --> copy0MBB
763  MachineBasicBlock *thisMBB = BB;
764  MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
765  MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
766  BuildMI(BB, BROpcode, 1).addMBB(sinkMBB);
767  MachineFunction *F = BB->getParent();
768  F->getBasicBlockList().insert(It, copy0MBB);
769  F->getBasicBlockList().insert(It, sinkMBB);
770  // Update machine-CFG edges
771  BB->addSuccessor(copy0MBB);
772  BB->addSuccessor(sinkMBB);
773
774  //  copy0MBB:
775  //   %FalseValue = ...
776  //   # fallthrough to sinkMBB
777  BB = copy0MBB;
778
779  // Update machine-CFG edges
780  BB->addSuccessor(sinkMBB);
781
782  //  sinkMBB:
783  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
784  //  ...
785  BB = sinkMBB;
786  BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg())
787    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
788    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
789
790  delete MI;   // The pseudo instruction is gone now.
791  return BB;
792}
793
794//===----------------------------------------------------------------------===//
795// Instruction Selector Implementation
796//===----------------------------------------------------------------------===//
797
798//===--------------------------------------------------------------------===//
799/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine
800/// instructions for SelectionDAG operations.
801///
802namespace {
803class SparcV8DAGToDAGISel : public SelectionDAGISel {
804  SparcV8TargetLowering V8Lowering;
805public:
806  SparcV8DAGToDAGISel(TargetMachine &TM)
807    : SelectionDAGISel(V8Lowering), V8Lowering(TM) {}
808
809  SDOperand Select(SDOperand Op);
810
811  // Complex Pattern Selectors.
812  bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
813  bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset);
814
815  /// InstructionSelectBasicBlock - This callback is invoked by
816  /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
817  virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
818
819  virtual const char *getPassName() const {
820    return "PowerPC DAG->DAG Pattern Instruction Selection";
821  }
822
823  // Include the pieces autogenerated from the target description.
824#include "SparcV8GenDAGISel.inc"
825};
826}  // end anonymous namespace
827
828/// InstructionSelectBasicBlock - This callback is invoked by
829/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
830void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
831  DEBUG(BB->dump());
832
833  // Select target instructions for the DAG.
834  DAG.setRoot(Select(DAG.getRoot()));
835  CodeGenMap.clear();
836  DAG.RemoveDeadNodes();
837
838  // Emit machine code to BB.
839  ScheduleAndEmitDAG(DAG);
840}
841
842bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base,
843                                       SDOperand &Offset) {
844  if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
845    Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
846    Offset = CurDAG->getTargetConstant(0, MVT::i32);
847    return true;
848  }
849
850  if (Addr.getOpcode() == ISD::ADD) {
851    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
852      if (Predicate_simm13(CN)) {
853        if (FrameIndexSDNode *FIN =
854                dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
855          // Constant offset from frame ref.
856          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
857        } else {
858          Base = Select(Addr.getOperand(0));
859        }
860        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
861        return true;
862      }
863    }
864    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) {
865      Base = Select(Addr.getOperand(1));
866      Offset = Addr.getOperand(0).getOperand(0);
867      return true;
868    }
869    if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) {
870      Base = Select(Addr.getOperand(0));
871      Offset = Addr.getOperand(1).getOperand(0);
872      return true;
873    }
874  }
875  Base = Select(Addr);
876  Offset = CurDAG->getTargetConstant(0, MVT::i32);
877  return true;
878}
879
880bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1,
881                                       SDOperand &R2) {
882  if (Addr.getOpcode() == ISD::FrameIndex) return false;
883  if (Addr.getOpcode() == ISD::ADD) {
884    if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
885        Predicate_simm13(Addr.getOperand(1).Val))
886      return false;  // Let the reg+imm pattern catch this!
887    if (Addr.getOperand(0).getOpcode() == V8ISD::Lo ||
888        Addr.getOperand(1).getOpcode() == V8ISD::Lo)
889      return false;  // Let the reg+imm pattern catch this!
890    R1 = Select(Addr.getOperand(0));
891    R2 = Select(Addr.getOperand(1));
892    return true;
893  }
894
895  R1 = Select(Addr);
896  R2 = CurDAG->getRegister(V8::G0, MVT::i32);
897  return true;
898}
899
900SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) {
901  SDNode *N = Op.Val;
902  if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
903      N->getOpcode() < V8ISD::FIRST_NUMBER)
904    return Op;   // Already selected.
905                 // If this has already been converted, use it.
906  std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
907  if (CGMI != CodeGenMap.end()) return CGMI->second;
908
909  switch (N->getOpcode()) {
910  default: break;
911  case ISD::FrameIndex: {
912    int FI = cast<FrameIndexSDNode>(N)->getIndex();
913    if (N->hasOneUse())
914      return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32,
915                                  CurDAG->getTargetFrameIndex(FI, MVT::i32),
916                                  CurDAG->getTargetConstant(0, MVT::i32));
917    return CodeGenMap[Op] =
918      CurDAG->getTargetNode(V8::ADDri, MVT::i32,
919                            CurDAG->getTargetFrameIndex(FI, MVT::i32),
920                            CurDAG->getTargetConstant(0, MVT::i32));
921  }
922  case ISD::ADD_PARTS: {
923    SDOperand LHSL = Select(N->getOperand(0));
924    SDOperand LHSH = Select(N->getOperand(1));
925    SDOperand RHSL = Select(N->getOperand(2));
926    SDOperand RHSH = Select(N->getOperand(3));
927    // FIXME, handle immediate RHS.
928    SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag,
929                                          LHSL, RHSL);
930    SDOperand Hi  = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH,
931                                          Low.getValue(1));
932    CodeGenMap[SDOperand(N, 0)] = Low;
933    CodeGenMap[SDOperand(N, 1)] = Hi;
934    return Op.ResNo ? Hi : Low;
935  }
936  case ISD::SUB_PARTS: {
937    SDOperand LHSL = Select(N->getOperand(0));
938    SDOperand LHSH = Select(N->getOperand(1));
939    SDOperand RHSL = Select(N->getOperand(2));
940    SDOperand RHSH = Select(N->getOperand(3));
941    // FIXME, handle immediate RHS.
942    SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag,
943                                          LHSL, RHSL);
944    SDOperand Hi  = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH,
945                                          Low.getValue(1));
946    CodeGenMap[SDOperand(N, 0)] = Low;
947    CodeGenMap[SDOperand(N, 1)] = Hi;
948    return Op.ResNo ? Hi : Low;
949  }
950  case ISD::SDIV:
951  case ISD::UDIV: {
952    // FIXME: should use a custom expander to expose the SRA to the dag.
953    SDOperand DivLHS = Select(N->getOperand(0));
954    SDOperand DivRHS = Select(N->getOperand(1));
955
956    // Set the Y register to the high-part.
957    SDOperand TopPart;
958    if (N->getOpcode() == ISD::SDIV) {
959      TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS,
960                                      CurDAG->getTargetConstant(31, MVT::i32));
961    } else {
962      TopPart = CurDAG->getRegister(V8::G0, MVT::i32);
963    }
964    TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart,
965                                    CurDAG->getRegister(V8::G0, MVT::i32));
966
967    // FIXME: Handle div by immediate.
968    unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr;
969    return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
970  }
971  case ISD::MULHU:
972  case ISD::MULHS: {
973    // FIXME: Handle mul by immediate.
974    SDOperand MulLHS = Select(N->getOperand(0));
975    SDOperand MulRHS = Select(N->getOperand(1));
976    unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr;
977    SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
978                                          MulLHS, MulRHS);
979    // The high part is in the Y register.
980    return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1));
981  }
982  case ISD::CALL:
983    // FIXME: This is a workaround for a bug in tblgen.
984  { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag)
985    // Emits: (CALL:void (tglobaladdr:i32):$dst)
986    // Pattern complexity = 2  cost = 1
987    SDOperand N1 = N->getOperand(1);
988    if (N1.getOpcode() != ISD::TargetGlobalAddress &&
989        N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail;
990    SDOperand InFlag = SDOperand(0, 0);
991    SDOperand Chain = N->getOperand(0);
992    SDOperand Tmp0 = N1;
993    Chain = Select(Chain);
994    SDOperand Result;
995    if (N->getNumOperands() == 3) {
996      InFlag = Select(N->getOperand(2));
997      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
998                                     Chain, InFlag);
999    } else {
1000      Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0,
1001                                     Chain);
1002    }
1003    Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0);
1004     CodeGenMap[SDOperand(N, 1)] = Result.getValue(1);
1005    return Result.getValue(Op.ResNo);
1006  }
1007    P47Fail:;
1008
1009  }
1010
1011  return SelectCode(Op);
1012}
1013
1014
1015/// createPPCISelDag - This pass converts a legalized DAG into a
1016/// PowerPC-specific DAG, ready for instruction scheduling.
1017///
1018FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) {
1019  return new SparcV8DAGToDAGISel(TM);
1020}
1021