SparcISelDAGToDAG.cpp revision e81aecbae69d4b3bd24523ec87673632d3b0beec
1//===-- SparcV8ISelDAGToDAG.cpp - A dag to dag inst selector for SparcV8 --===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file defines an instruction selector for the V8 target 11// 12//===----------------------------------------------------------------------===// 13 14#include "SparcV8.h" 15#include "SparcV8TargetMachine.h" 16#include "llvm/DerivedTypes.h" 17#include "llvm/Function.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/CodeGen/MachineFunction.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/SelectionDAG.h" 22#include "llvm/CodeGen/SelectionDAGISel.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetLowering.h" 25#include "llvm/Support/Debug.h" 26#include <iostream> 27using namespace llvm; 28 29//===----------------------------------------------------------------------===// 30// TargetLowering Implementation 31//===----------------------------------------------------------------------===// 32 33namespace V8ISD { 34 enum { 35 FIRST_NUMBER = ISD::BUILTIN_OP_END+V8::INSTRUCTION_LIST_END, 36 CMPICC, // Compare two GPR operands, set icc. 37 CMPFCC, // Compare two FP operands, set fcc. 38 BRICC, // Branch to dest on icc condition 39 BRFCC, // Branch to dest on fcc condition 40 41 Hi, Lo, // Hi/Lo operations, typically on a global address. 42 43 FTOI, // FP to Int within a FP register. 44 ITOF, // Int to FP within a FP register. 45 46 SELECT_ICC, // Select between two values using the current ICC flags. 47 SELECT_FCC, // Select between two values using the current FCC flags. 48 49 RET_FLAG, // Return with a flag operand. 50 }; 51} 52 53namespace { 54 class SparcV8TargetLowering : public TargetLowering { 55 int VarArgsFrameOffset; // Frame offset to start of varargs area. 56 public: 57 SparcV8TargetLowering(TargetMachine &TM); 58 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG); 59 virtual std::vector<SDOperand> 60 LowerArguments(Function &F, SelectionDAG &DAG); 61 virtual std::pair<SDOperand, SDOperand> 62 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, 63 unsigned CC, 64 bool isTailCall, SDOperand Callee, ArgListTy &Args, 65 SelectionDAG &DAG); 66 67 virtual SDOperand LowerReturnTo(SDOperand Chain, SDOperand Op, 68 SelectionDAG &DAG); 69 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP, 70 Value *VAListV, SelectionDAG &DAG); 71 virtual std::pair<SDOperand,SDOperand> 72 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 73 const Type *ArgTy, SelectionDAG &DAG); 74 virtual std::pair<SDOperand, SDOperand> 75 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 76 SelectionDAG &DAG); 77 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI, 78 MachineBasicBlock *MBB); 79 }; 80} 81 82SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM) 83 : TargetLowering(TM) { 84 85 // Set up the register classes. 86 addRegisterClass(MVT::i32, V8::IntRegsRegisterClass); 87 addRegisterClass(MVT::f32, V8::FPRegsRegisterClass); 88 addRegisterClass(MVT::f64, V8::DFPRegsRegisterClass); 89 90 // Custom legalize GlobalAddress nodes into LO/HI parts. 91 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 92 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 93 94 // Sparc doesn't have sext_inreg, replace them with shl/sra 95 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 98 99 // Sparc has no REM operation. 100 setOperationAction(ISD::UREM, MVT::i32, Expand); 101 setOperationAction(ISD::SREM, MVT::i32, Expand); 102 103 // Custom expand fp<->sint 104 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 105 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 106 107 // Expand fp<->uint 108 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 109 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 110 111 // Turn FP extload into load/fextend 112 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand); 113 114 // Sparc has no select or setcc: expand to SELECT_CC. 115 setOperationAction(ISD::SELECT, MVT::i32, Expand); 116 setOperationAction(ISD::SELECT, MVT::f32, Expand); 117 setOperationAction(ISD::SELECT, MVT::f64, Expand); 118 setOperationAction(ISD::SETCC, MVT::i32, Expand); 119 setOperationAction(ISD::SETCC, MVT::f32, Expand); 120 setOperationAction(ISD::SETCC, MVT::f64, Expand); 121 122 // Sparc doesn't have BRCOND either, it has BR_CC. 123 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 124 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); 125 setOperationAction(ISD::BRTWOWAY_CC, MVT::Other, Expand); 126 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 127 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 128 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 129 130 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 131 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 132 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 133 134 // V8 has no intrinsics for these particular operations. 135 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand); 136 setOperationAction(ISD::MEMSET, MVT::Other, Expand); 137 setOperationAction(ISD::MEMCPY, MVT::Other, Expand); 138 139 setOperationAction(ISD::FSIN , MVT::f64, Expand); 140 setOperationAction(ISD::FCOS , MVT::f64, Expand); 141 setOperationAction(ISD::FSIN , MVT::f32, Expand); 142 setOperationAction(ISD::FCOS , MVT::f32, Expand); 143 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 144 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 145 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 146 147 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 148 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 149 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 150 151 // We don't have line number support yet. 152 setOperationAction(ISD::LOCATION, MVT::Other, Expand); 153 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); 154 155 computeRegisterProperties(); 156} 157 158/// LowerArguments - V8 uses a very simple ABI, where all values are passed in 159/// either one or two GPRs, including FP values. TODO: we should pass FP values 160/// in FP registers for fastcc functions. 161std::vector<SDOperand> 162SparcV8TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { 163 MachineFunction &MF = DAG.getMachineFunction(); 164 SSARegMap *RegMap = MF.getSSARegMap(); 165 std::vector<SDOperand> ArgValues; 166 167 static const unsigned ArgRegs[] = { 168 V8::I0, V8::I1, V8::I2, V8::I3, V8::I4, V8::I5 169 }; 170 171 const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6; 172 unsigned ArgOffset = 68; 173 174 SDOperand Root = DAG.getRoot(); 175 std::vector<SDOperand> OutChains; 176 177 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { 178 MVT::ValueType ObjectVT = getValueType(I->getType()); 179 180 switch (ObjectVT) { 181 default: assert(0 && "Unhandled argument type!"); 182 case MVT::i1: 183 case MVT::i8: 184 case MVT::i16: 185 case MVT::i32: 186 if (I->use_empty()) { // Argument is dead. 187 if (CurArgReg < ArgRegEnd) ++CurArgReg; 188 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 189 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 190 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 191 MF.addLiveIn(*CurArgReg++, VReg); 192 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 193 if (ObjectVT != MVT::i32) { 194 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext 195 : ISD::AssertZext; 196 Arg = DAG.getNode(AssertOp, MVT::i32, Arg, 197 DAG.getValueType(ObjectVT)); 198 Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg); 199 } 200 ArgValues.push_back(Arg); 201 } else { 202 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 203 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 204 SDOperand Load; 205 if (ObjectVT == MVT::i32) { 206 Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 207 } else { 208 unsigned LoadOp = 209 I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD; 210 211 Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr, 212 DAG.getSrcValue(0), ObjectVT); 213 } 214 ArgValues.push_back(Load); 215 } 216 217 ArgOffset += 4; 218 break; 219 case MVT::f32: 220 if (I->use_empty()) { // Argument is dead. 221 if (CurArgReg < ArgRegEnd) ++CurArgReg; 222 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 223 } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 224 // FP value is passed in an integer register. 225 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 226 MF.addLiveIn(*CurArgReg++, VReg); 227 SDOperand Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32); 228 229 // We use the stack space that is already reserved for this reg. 230 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 231 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 232 233 SDOperand SV = DAG.getSrcValue(0); 234 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root, 235 Arg, FIPtr, SV); 236 ArgValues.push_back(DAG.getLoad(MVT::f32, Store, FIPtr, SV)); 237 } 238 ArgOffset += 4; 239 break; 240 241 case MVT::i64: 242 case MVT::f64: 243 if (I->use_empty()) { // Argument is dead. 244 if (CurArgReg < ArgRegEnd) ++CurArgReg; 245 if (CurArgReg < ArgRegEnd) ++CurArgReg; 246 ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT)); 247 } else if (CurArgReg == ArgRegEnd && ObjectVT == MVT::f64 && 248 ((CurArgReg-ArgRegs) & 1) == 0) { 249 // If this is a double argument and the whole thing lives on the stack, 250 // and the argument is aligned, load the double straight from the stack. 251 // We can't do a load in cases like void foo([6ints], int,double), 252 // because the double wouldn't be aligned! 253 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset); 254 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 255 ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 256 DAG.getSrcValue(0))); 257 } else { 258 SDOperand HiVal; 259 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 260 unsigned VRegHi = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 261 MF.addLiveIn(*CurArgReg++, VRegHi); 262 HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32); 263 } else { 264 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 265 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 266 HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 267 } 268 269 SDOperand LoVal; 270 if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR 271 unsigned VRegLo = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 272 MF.addLiveIn(*CurArgReg++, VRegLo); 273 LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32); 274 } else { 275 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); 276 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 277 LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0)); 278 } 279 280 // Compose the two halves together into an i64 unit. 281 SDOperand WholeValue = 282 DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal); 283 284 if (ObjectVT == MVT::i64) { 285 // If we are emitting an i64, this is what we want. 286 ArgValues.push_back(WholeValue); 287 } else { 288 assert(ObjectVT == MVT::f64); 289 // Otherwise, emit a store to the stack and reload into FPR. 290 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); 291 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 292 SDOperand SV = DAG.getSrcValue(0); 293 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Root, 294 WholeValue, FIPtr, SV); 295 ArgValues.push_back(DAG.getLoad(MVT::f64, Store, FIPtr, SV)); 296 } 297 } 298 ArgOffset += 8; 299 break; 300 } 301 } 302 303 // Store remaining ArgRegs to the stack if this is a varargs function. 304 if (F.getFunctionType()->isVarArg()) { 305 // Remember the vararg offset for the va_start implementation. 306 VarArgsFrameOffset = ArgOffset; 307 308 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 309 unsigned VReg = RegMap->createVirtualRegister(&V8::IntRegsRegClass); 310 MF.addLiveIn(*CurArgReg, VReg); 311 SDOperand Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32); 312 313 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); 314 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 315 316 OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(), 317 Arg, FIPtr, DAG.getSrcValue(0))); 318 ArgOffset += 4; 319 } 320 } 321 322 if (!OutChains.empty()) 323 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains)); 324 325 // Finally, inform the code generator which regs we return values in. 326 switch (getValueType(F.getReturnType())) { 327 default: assert(0 && "Unknown type!"); 328 case MVT::isVoid: break; 329 case MVT::i1: 330 case MVT::i8: 331 case MVT::i16: 332 case MVT::i32: 333 MF.addLiveOut(V8::I0); 334 break; 335 case MVT::i64: 336 MF.addLiveOut(V8::I0); 337 MF.addLiveOut(V8::I1); 338 break; 339 case MVT::f32: 340 MF.addLiveOut(V8::F0); 341 break; 342 case MVT::f64: 343 MF.addLiveOut(V8::D0); 344 break; 345 } 346 347 return ArgValues; 348} 349 350std::pair<SDOperand, SDOperand> 351SparcV8TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy, 352 bool isVarArg, unsigned CC, 353 bool isTailCall, SDOperand Callee, 354 ArgListTy &Args, SelectionDAG &DAG) { 355 MachineFunction &MF = DAG.getMachineFunction(); 356 // Count the size of the outgoing arguments. 357 unsigned ArgsSize = 0; 358 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 359 switch (getValueType(Args[i].second)) { 360 default: assert(0 && "Unknown value type!"); 361 case MVT::i1: 362 case MVT::i8: 363 case MVT::i16: 364 case MVT::i32: 365 case MVT::f32: 366 ArgsSize += 4; 367 break; 368 case MVT::i64: 369 case MVT::f64: 370 ArgsSize += 8; 371 break; 372 } 373 } 374 if (ArgsSize > 4*6) 375 ArgsSize -= 4*6; // Space for first 6 arguments is prereserved. 376 else 377 ArgsSize = 0; 378 379 // Keep stack frames 8-byte aligned. 380 ArgsSize = (ArgsSize+7) & ~7; 381 382 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain, 383 DAG.getConstant(ArgsSize, getPointerTy())); 384 385 SDOperand StackPtr, NullSV; 386 std::vector<SDOperand> Stores; 387 std::vector<SDOperand> RegValuesToPass; 388 unsigned ArgOffset = 68; 389 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 390 SDOperand Val = Args[i].first; 391 MVT::ValueType ObjectVT = Val.getValueType(); 392 SDOperand ValToStore; 393 unsigned ObjSize; 394 switch (ObjectVT) { 395 default: assert(0 && "Unhandled argument type!"); 396 case MVT::i1: 397 case MVT::i8: 398 case MVT::i16: 399 // Promote the integer to 32-bits. If the input type is signed, use a 400 // sign extend, otherwise use a zero extend. 401 if (Args[i].second->isSigned()) 402 Val = DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Val); 403 else 404 Val = DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Val); 405 // FALL THROUGH 406 case MVT::i32: 407 ObjSize = 4; 408 409 if (RegValuesToPass.size() >= 6) { 410 ValToStore = Val; 411 } else { 412 RegValuesToPass.push_back(Val); 413 } 414 break; 415 case MVT::f32: 416 ObjSize = 4; 417 if (RegValuesToPass.size() >= 6) { 418 ValToStore = Val; 419 } else { 420 // Convert this to a FP value in an int reg. 421 int FrameIdx = MF.getFrameInfo()->CreateStackObject(4, 4); 422 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 423 SDOperand SV = DAG.getSrcValue(0); 424 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 425 Val, FIPtr, SV); 426 Val = DAG.getLoad(MVT::i32, Store, FIPtr, SV); 427 RegValuesToPass.push_back(Val); 428 } 429 break; 430 case MVT::f64: { 431 ObjSize = 8; 432 // If we can store this directly into the outgoing slot, do so. We can 433 // do this when all ArgRegs are used and if the outgoing slot is aligned. 434 if (RegValuesToPass.size() >= 6 && ((ArgOffset-68) & 7) == 0) { 435 ValToStore = Val; 436 break; 437 } 438 439 // Otherwise, convert this to a FP value in int regs. 440 int FrameIdx = MF.getFrameInfo()->CreateStackObject(8, 8); 441 SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 442 SDOperand SV = DAG.getSrcValue(0); 443 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain, 444 Val, FIPtr, SV); 445 Val = DAG.getLoad(MVT::i64, Store, FIPtr, SV); 446 } 447 // FALL THROUGH 448 case MVT::i64: 449 ObjSize = 8; 450 if (RegValuesToPass.size() >= 6) { 451 ValToStore = Val; // Whole thing is passed in memory. 452 break; 453 } 454 455 // Split the value into top and bottom part. Top part goes in a reg. 456 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 457 DAG.getConstant(1, MVT::i32)); 458 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val, 459 DAG.getConstant(0, MVT::i32)); 460 RegValuesToPass.push_back(Hi); 461 462 if (RegValuesToPass.size() >= 6) { 463 ValToStore = Lo; 464 ArgOffset += 4; 465 ObjSize = 4; 466 } else { 467 RegValuesToPass.push_back(Lo); 468 } 469 break; 470 } 471 472 if (ValToStore.Val) { 473 if (!StackPtr.Val) { 474 StackPtr = DAG.getRegister(V8::O6, MVT::i32); 475 NullSV = DAG.getSrcValue(NULL); 476 } 477 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy()); 478 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); 479 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain, 480 ValToStore, PtrOff, NullSV)); 481 } 482 ArgOffset += ObjSize; 483 } 484 485 // Emit all stores, make sure the occur before any copies into physregs. 486 if (!Stores.empty()) 487 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores); 488 489 static const unsigned ArgRegs[] = { 490 V8::O0, V8::O1, V8::O2, V8::O3, V8::O4, V8::O5 491 }; 492 493 // Build a sequence of copy-to-reg nodes chained together with token chain 494 // and flag operands which copy the outgoing args into O[0-5]. 495 SDOperand InFlag; 496 for (unsigned i = 0, e = RegValuesToPass.size(); i != e; ++i) { 497 Chain = DAG.getCopyToReg(Chain, ArgRegs[i], RegValuesToPass[i], InFlag); 498 InFlag = Chain.getValue(1); 499 } 500 501 std::vector<MVT::ValueType> RetVals; 502 RetVals.push_back(MVT::Other); 503 RetVals.push_back(MVT::Flag); 504 505 // If the callee is a GlobalAddress node (quite common, every direct call is) 506 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 507 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 508 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); 509 510 std::vector<MVT::ValueType> NodeTys; 511 NodeTys.push_back(MVT::Other); // Returns a chain 512 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. 513 if (InFlag.Val) 514 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee, InFlag), 0); 515 else 516 Chain = SDOperand(DAG.getCall(NodeTys, Chain, Callee), 0); 517 InFlag = Chain.getValue(1); 518 519 MVT::ValueType RetTyVT = getValueType(RetTy); 520 SDOperand RetVal; 521 if (RetTyVT != MVT::isVoid) { 522 switch (RetTyVT) { 523 default: assert(0 && "Unknown value type to return!"); 524 case MVT::i1: 525 case MVT::i8: 526 case MVT::i16: 527 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 528 Chain = RetVal.getValue(1); 529 530 // Add a note to keep track of whether it is sign or zero extended. 531 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext :ISD::AssertZext, 532 MVT::i32, RetVal, DAG.getValueType(RetTyVT)); 533 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal); 534 break; 535 case MVT::i32: 536 RetVal = DAG.getCopyFromReg(Chain, V8::O0, MVT::i32, InFlag); 537 Chain = RetVal.getValue(1); 538 break; 539 case MVT::f32: 540 RetVal = DAG.getCopyFromReg(Chain, V8::F0, MVT::f32, InFlag); 541 Chain = RetVal.getValue(1); 542 break; 543 case MVT::f64: 544 RetVal = DAG.getCopyFromReg(Chain, V8::D0, MVT::f64, InFlag); 545 Chain = RetVal.getValue(1); 546 break; 547 case MVT::i64: 548 SDOperand Lo = DAG.getCopyFromReg(Chain, V8::O1, MVT::i32, InFlag); 549 SDOperand Hi = DAG.getCopyFromReg(Lo.getValue(1), V8::O0, MVT::i32, 550 Lo.getValue(2)); 551 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi); 552 Chain = Hi.getValue(1); 553 break; 554 } 555 } 556 557 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain, 558 DAG.getConstant(ArgsSize, getPointerTy())); 559 560 return std::make_pair(RetVal, Chain); 561} 562 563SDOperand SparcV8TargetLowering::LowerReturnTo(SDOperand Chain, SDOperand Op, 564 SelectionDAG &DAG) { 565 SDOperand Copy; 566 switch (Op.getValueType()) { 567 default: assert(0 && "Unknown type to return!"); 568 case MVT::i32: 569 Copy = DAG.getCopyToReg(Chain, V8::I0, Op, SDOperand()); 570 break; 571 case MVT::f32: 572 Copy = DAG.getCopyToReg(Chain, V8::F0, Op, SDOperand()); 573 break; 574 case MVT::f64: 575 Copy = DAG.getCopyToReg(Chain, V8::D0, Op, SDOperand()); 576 break; 577 case MVT::i64: 578 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 579 DAG.getConstant(1, MVT::i32)); 580 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op, 581 DAG.getConstant(0, MVT::i32)); 582 Copy = DAG.getCopyToReg(Chain, V8::I0, Hi, SDOperand()); 583 Copy = DAG.getCopyToReg(Copy, V8::I1, Lo, Copy.getValue(1)); 584 break; 585 } 586 return DAG.getNode(V8ISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1)); 587} 588 589SDOperand SparcV8TargetLowering:: 590LowerVAStart(SDOperand Chain, SDOperand VAListP, Value *VAListV, 591 SelectionDAG &DAG) { 592 593 assert(0 && "Unimp"); 594 abort(); 595} 596 597std::pair<SDOperand,SDOperand> SparcV8TargetLowering:: 598LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV, 599 const Type *ArgTy, SelectionDAG &DAG) { 600 assert(0 && "Unimp"); 601 abort(); 602} 603 604std::pair<SDOperand, SDOperand> SparcV8TargetLowering:: 605LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth, 606 SelectionDAG &DAG) { 607 assert(0 && "Unimp"); 608 abort(); 609} 610 611SDOperand SparcV8TargetLowering:: 612LowerOperation(SDOperand Op, SelectionDAG &DAG) { 613 switch (Op.getOpcode()) { 614 default: assert(0 && "Should not custom lower this!"); 615 case ISD::GlobalAddress: { 616 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 617 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32); 618 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, GA); 619 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, GA); 620 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 621 } 622 case ISD::ConstantPool: { 623 Constant *C = cast<ConstantPoolSDNode>(Op)->get(); 624 SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32); 625 SDOperand Hi = DAG.getNode(V8ISD::Hi, MVT::i32, CP); 626 SDOperand Lo = DAG.getNode(V8ISD::Lo, MVT::i32, CP); 627 return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi); 628 } 629 case ISD::FP_TO_SINT: { 630 // Convert the fp value to integer in an FP register. 631 Op = DAG.getNode(V8ISD::FTOI, Op.getOperand(0).getValueType(), 632 Op.getOperand(0)); 633 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8; 634 int FrameIdx = 635 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size); 636 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 637 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 638 Op, FI, DAG.getSrcValue(0)); 639 return DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0)); 640 } 641 case ISD::SINT_TO_FP: { 642 int Size = Op.getOperand(0).getValueType() == MVT::f32 ? 4 : 8; 643 int FrameIdx = 644 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(Size, Size); 645 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32); 646 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(), 647 Op.getOperand(0), FI, DAG.getSrcValue(0)); 648 649 Op = DAG.getLoad(Op.getValueType(), ST, FI, DAG.getSrcValue(0)); 650 651 // Convert the int value to FP in an FP register. 652 return DAG.getNode(V8ISD::ITOF, Op.getValueType(), Op); 653 } 654 case ISD::BR_CC: { 655 SDOperand Chain = Op.getOperand(0); 656 SDOperand CC = Op.getOperand(1); 657 SDOperand LHS = Op.getOperand(2); 658 SDOperand RHS = Op.getOperand(3); 659 SDOperand Dest = Op.getOperand(4); 660 661 // Get the condition flag. 662 if (LHS.getValueType() == MVT::i32) { 663 SDOperand Cond = DAG.getNode(V8ISD::CMPICC, MVT::Flag, LHS, RHS); 664 return DAG.getNode(V8ISD::BRICC, MVT::Other, Chain, Dest, CC, Cond); 665 } else { 666 SDOperand Cond = DAG.getNode(V8ISD::CMPFCC, MVT::Flag, LHS, RHS); 667 return DAG.getNode(V8ISD::BRFCC, MVT::Other, Chain, Dest, CC, Cond); 668 } 669 } 670 case ISD::SELECT_CC: { 671 SDOperand LHS = Op.getOperand(0); 672 SDOperand RHS = Op.getOperand(1); 673 unsigned CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 674 SDOperand TrueVal = Op.getOperand(2); 675 SDOperand FalseVal = Op.getOperand(3); 676 677 unsigned Opc; 678 Opc = LHS.getValueType() == MVT::i32 ? V8ISD::CMPICC : V8ISD::CMPFCC; 679 SDOperand CompareFlag = DAG.getNode(Opc, MVT::Flag, LHS, RHS); 680 681 Opc = LHS.getValueType() == MVT::i32 ? 682 V8ISD::SELECT_ICC : V8ISD::SELECT_FCC; 683 return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal, 684 DAG.getConstant(CC, MVT::i32), CompareFlag); 685 } 686 } 687} 688 689MachineBasicBlock * 690SparcV8TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI, 691 MachineBasicBlock *BB) { 692 unsigned BROpcode; 693 // Figure out the conditional branch opcode to use for this select_cc. 694 switch (MI->getOpcode()) { 695 default: assert(0 && "Unknown SELECT_CC!"); 696 case V8::SELECT_CC_Int_ICC: 697 case V8::SELECT_CC_FP_ICC: 698 case V8::SELECT_CC_DFP_ICC: 699 // Integer compare. 700 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 701 default: assert(0 && "Unknown integer condition code!"); 702 case ISD::SETEQ: BROpcode = V8::BE; break; 703 case ISD::SETNE: BROpcode = V8::BNE; break; 704 case ISD::SETLT: BROpcode = V8::BL; break; 705 case ISD::SETGT: BROpcode = V8::BG; break; 706 case ISD::SETLE: BROpcode = V8::BLE; break; 707 case ISD::SETGE: BROpcode = V8::BGE; break; 708 case ISD::SETULT: BROpcode = V8::BCS; break; 709 case ISD::SETULE: BROpcode = V8::BLEU; break; 710 case ISD::SETUGT: BROpcode = V8::BGU; break; 711 case ISD::SETUGE: BROpcode = V8::BCC; break; 712 } 713 break; 714 case V8::SELECT_CC_Int_FCC: 715 case V8::SELECT_CC_FP_FCC: 716 case V8::SELECT_CC_DFP_FCC: 717 // FP compare. 718 switch ((ISD::CondCode)MI->getOperand(3).getImmedValue()) { 719 default: assert(0 && "Unknown fp condition code!"); 720 case ISD::SETEQ: BROpcode = V8::FBE; break; 721 case ISD::SETNE: BROpcode = V8::FBNE; break; 722 case ISD::SETLT: BROpcode = V8::FBL; break; 723 case ISD::SETGT: BROpcode = V8::FBG; break; 724 case ISD::SETLE: BROpcode = V8::FBLE; break; 725 case ISD::SETGE: BROpcode = V8::FBGE; break; 726 case ISD::SETULT: BROpcode = V8::FBUL; break; 727 case ISD::SETULE: BROpcode = V8::FBULE; break; 728 case ISD::SETUGT: BROpcode = V8::FBUG; break; 729 case ISD::SETUGE: BROpcode = V8::FBUGE; break; 730 case ISD::SETUO: BROpcode = V8::FBU; break; 731 case ISD::SETO: BROpcode = V8::FBO; break; 732 case ISD::SETONE: BROpcode = V8::FBLG; break; 733 case ISD::SETUEQ: BROpcode = V8::FBUE; break; 734 } 735 break; 736 } 737 738 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 739 // control-flow pattern. The incoming instruction knows the destination vreg 740 // to set, the condition code register to branch on, the true/false values to 741 // select between, and a branch opcode to use. 742 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 743 ilist<MachineBasicBlock>::iterator It = BB; 744 ++It; 745 746 // thisMBB: 747 // ... 748 // TrueVal = ... 749 // [f]bCC copy1MBB 750 // fallthrough --> copy0MBB 751 MachineBasicBlock *thisMBB = BB; 752 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB); 753 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB); 754 BuildMI(BB, BROpcode, 1).addMBB(sinkMBB); 755 MachineFunction *F = BB->getParent(); 756 F->getBasicBlockList().insert(It, copy0MBB); 757 F->getBasicBlockList().insert(It, sinkMBB); 758 // Update machine-CFG edges 759 BB->addSuccessor(copy0MBB); 760 BB->addSuccessor(sinkMBB); 761 762 // copy0MBB: 763 // %FalseValue = ... 764 // # fallthrough to sinkMBB 765 BB = copy0MBB; 766 767 // Update machine-CFG edges 768 BB->addSuccessor(sinkMBB); 769 770 // sinkMBB: 771 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 772 // ... 773 BB = sinkMBB; 774 BuildMI(BB, V8::PHI, 4, MI->getOperand(0).getReg()) 775 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 776 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 777 778 delete MI; // The pseudo instruction is gone now. 779 return BB; 780} 781 782//===----------------------------------------------------------------------===// 783// Instruction Selector Implementation 784//===----------------------------------------------------------------------===// 785 786//===--------------------------------------------------------------------===// 787/// SparcV8DAGToDAGISel - PPC specific code to select Sparc V8 machine 788/// instructions for SelectionDAG operations. 789/// 790namespace { 791class SparcV8DAGToDAGISel : public SelectionDAGISel { 792 SparcV8TargetLowering V8Lowering; 793public: 794 SparcV8DAGToDAGISel(TargetMachine &TM) 795 : SelectionDAGISel(V8Lowering), V8Lowering(TM) {} 796 797 SDOperand Select(SDOperand Op); 798 799 // Complex Pattern Selectors. 800 bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2); 801 bool SelectADDRri(SDOperand N, SDOperand &Base, SDOperand &Offset); 802 803 /// InstructionSelectBasicBlock - This callback is invoked by 804 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 805 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG); 806 807 virtual const char *getPassName() const { 808 return "PowerPC DAG->DAG Pattern Instruction Selection"; 809 } 810 811 // Include the pieces autogenerated from the target description. 812#include "SparcV8GenDAGISel.inc" 813}; 814} // end anonymous namespace 815 816/// InstructionSelectBasicBlock - This callback is invoked by 817/// SelectionDAGISel when it has created a SelectionDAG for us to codegen. 818void SparcV8DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) { 819 DEBUG(BB->dump()); 820 821 // Select target instructions for the DAG. 822 DAG.setRoot(Select(DAG.getRoot())); 823 CodeGenMap.clear(); 824 DAG.RemoveDeadNodes(); 825 826 // Emit machine code to BB. 827 ScheduleAndEmitDAG(DAG); 828} 829 830bool SparcV8DAGToDAGISel::SelectADDRri(SDOperand Addr, SDOperand &Base, 831 SDOperand &Offset) { 832 if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { 833 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 834 Offset = CurDAG->getTargetConstant(0, MVT::i32); 835 return true; 836 } 837 838 if (Addr.getOpcode() == ISD::ADD) { 839 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { 840 if (Predicate_simm13(CN)) { 841 if (FrameIndexSDNode *FIN = 842 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { 843 // Constant offset from frame ref. 844 Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); 845 } else { 846 Base = Select(Addr.getOperand(0)); 847 } 848 Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32); 849 return true; 850 } 851 } 852 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo) { 853 Base = Select(Addr.getOperand(1)); 854 Offset = Addr.getOperand(0).getOperand(0); 855 return true; 856 } 857 if (Addr.getOperand(1).getOpcode() == V8ISD::Lo) { 858 Base = Select(Addr.getOperand(0)); 859 Offset = Addr.getOperand(1).getOperand(0); 860 return true; 861 } 862 } 863 Base = Select(Addr); 864 Offset = CurDAG->getTargetConstant(0, MVT::i32); 865 return true; 866} 867 868bool SparcV8DAGToDAGISel::SelectADDRrr(SDOperand Addr, SDOperand &R1, 869 SDOperand &R2) { 870 if (Addr.getOpcode() == ISD::FrameIndex) return false; 871 if (Addr.getOpcode() == ISD::ADD) { 872 if (isa<ConstantSDNode>(Addr.getOperand(1)) && 873 Predicate_simm13(Addr.getOperand(1).Val)) 874 return false; // Let the reg+imm pattern catch this! 875 if (Addr.getOperand(0).getOpcode() == V8ISD::Lo || 876 Addr.getOperand(1).getOpcode() == V8ISD::Lo) 877 return false; // Let the reg+imm pattern catch this! 878 R1 = Select(Addr.getOperand(0)); 879 R2 = Select(Addr.getOperand(1)); 880 return true; 881 } 882 883 R1 = Select(Addr); 884 R2 = CurDAG->getRegister(V8::G0, MVT::i32); 885 return true; 886} 887 888SDOperand SparcV8DAGToDAGISel::Select(SDOperand Op) { 889 SDNode *N = Op.Val; 890 if (N->getOpcode() >= ISD::BUILTIN_OP_END && 891 N->getOpcode() < V8ISD::FIRST_NUMBER) 892 return Op; // Already selected. 893 // If this has already been converted, use it. 894 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op); 895 if (CGMI != CodeGenMap.end()) return CGMI->second; 896 897 switch (N->getOpcode()) { 898 default: break; 899 case ISD::Register: return Op; 900 case ISD::FrameIndex: { 901 int FI = cast<FrameIndexSDNode>(N)->getIndex(); 902 if (N->hasOneUse()) 903 return CurDAG->SelectNodeTo(N, V8::ADDri, MVT::i32, 904 CurDAG->getTargetFrameIndex(FI, MVT::i32), 905 CurDAG->getTargetConstant(0, MVT::i32)); 906 return CodeGenMap[Op] = 907 CurDAG->getTargetNode(V8::ADDri, MVT::i32, 908 CurDAG->getTargetFrameIndex(FI, MVT::i32), 909 CurDAG->getTargetConstant(0, MVT::i32)); 910 } 911 case V8ISD::CMPICC: { 912 // FIXME: Handle compare with immediate. 913 SDOperand LHS = Select(N->getOperand(0)); 914 SDOperand RHS = Select(N->getOperand(1)); 915 SDOperand Result = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 916 LHS, RHS); 917 return CodeGenMap[Op] = Result.getValue(1); 918 } 919 case ISD::ADD_PARTS: { 920 SDOperand LHSL = Select(N->getOperand(0)); 921 SDOperand LHSH = Select(N->getOperand(1)); 922 SDOperand RHSL = Select(N->getOperand(2)); 923 SDOperand RHSH = Select(N->getOperand(3)); 924 // FIXME, handle immediate RHS. 925 SDOperand Low = CurDAG->getTargetNode(V8::ADDCCrr, MVT::i32, MVT::Flag, 926 LHSL, RHSL); 927 SDOperand Hi = CurDAG->getTargetNode(V8::ADDXrr, MVT::i32, LHSH, RHSH, 928 Low.getValue(1)); 929 CodeGenMap[SDOperand(N, 0)] = Low; 930 CodeGenMap[SDOperand(N, 1)] = Hi; 931 return Op.ResNo ? Hi : Low; 932 } 933 case ISD::SUB_PARTS: { 934 SDOperand LHSL = Select(N->getOperand(0)); 935 SDOperand LHSH = Select(N->getOperand(1)); 936 SDOperand RHSL = Select(N->getOperand(2)); 937 SDOperand RHSH = Select(N->getOperand(3)); 938 // FIXME, handle immediate RHS. 939 SDOperand Low = CurDAG->getTargetNode(V8::SUBCCrr, MVT::i32, MVT::Flag, 940 LHSL, RHSL); 941 SDOperand Hi = CurDAG->getTargetNode(V8::SUBXrr, MVT::i32, LHSH, RHSH, 942 Low.getValue(1)); 943 CodeGenMap[SDOperand(N, 0)] = Low; 944 CodeGenMap[SDOperand(N, 1)] = Hi; 945 return Op.ResNo ? Hi : Low; 946 } 947 case ISD::SDIV: 948 case ISD::UDIV: { 949 // FIXME: should use a custom expander to expose the SRA to the dag. 950 SDOperand DivLHS = Select(N->getOperand(0)); 951 SDOperand DivRHS = Select(N->getOperand(1)); 952 953 // Set the Y register to the high-part. 954 SDOperand TopPart; 955 if (N->getOpcode() == ISD::SDIV) { 956 TopPart = CurDAG->getTargetNode(V8::SRAri, MVT::i32, DivLHS, 957 CurDAG->getTargetConstant(31, MVT::i32)); 958 } else { 959 TopPart = CurDAG->getRegister(V8::G0, MVT::i32); 960 } 961 TopPart = CurDAG->getTargetNode(V8::WRYrr, MVT::Flag, TopPart, 962 CurDAG->getRegister(V8::G0, MVT::i32)); 963 964 // FIXME: Handle div by immediate. 965 unsigned Opcode = N->getOpcode() == ISD::SDIV ? V8::SDIVrr : V8::UDIVrr; 966 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart); 967 } 968 case ISD::MULHU: 969 case ISD::MULHS: { 970 // FIXME: Handle mul by immediate. 971 SDOperand MulLHS = Select(N->getOperand(0)); 972 SDOperand MulRHS = Select(N->getOperand(1)); 973 unsigned Opcode = N->getOpcode() == ISD::MULHU ? V8::UMULrr : V8::SMULrr; 974 SDOperand Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag, 975 MulLHS, MulRHS); 976 // The high part is in the Y register. 977 return CurDAG->SelectNodeTo(N, V8::RDY, MVT::i32, Mul.getValue(1)); 978 } 979 case ISD::CALL: 980 // FIXME: This is a workaround for a bug in tblgen. 981 { // Pattern #47: (call:Flag (tglobaladdr:i32):$dst, ICC:Flag) 982 // Emits: (CALL:void (tglobaladdr:i32):$dst) 983 // Pattern complexity = 2 cost = 1 984 SDOperand N1 = N->getOperand(1); 985 if (N1.getOpcode() != ISD::TargetGlobalAddress && 986 N1.getOpcode() != ISD::ExternalSymbol) goto P47Fail; 987 SDOperand InFlag = SDOperand(0, 0); 988 SDOperand Chain = N->getOperand(0); 989 SDOperand Tmp0 = N1; 990 Chain = Select(Chain); 991 SDOperand Result; 992 if (N->getNumOperands() == 3) { 993 InFlag = Select(N->getOperand(2)); 994 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 995 Chain, InFlag); 996 } else { 997 Result = CurDAG->getTargetNode(V8::CALL, MVT::Other, MVT::Flag, Tmp0, 998 Chain); 999 } 1000 Chain = CodeGenMap[SDOperand(N, 0)] = Result.getValue(0); 1001 CodeGenMap[SDOperand(N, 1)] = Result.getValue(1); 1002 return Result.getValue(Op.ResNo); 1003 } 1004 P47Fail:; 1005 1006 } 1007 1008 return SelectCode(Op); 1009} 1010 1011 1012/// createPPCISelDag - This pass converts a legalized DAG into a 1013/// PowerPC-specific DAG, ready for instruction scheduling. 1014/// 1015FunctionPass *llvm::createSparcV8ISelDag(TargetMachine &TM) { 1016 return new SparcV8DAGToDAGISel(TM); 1017} 1018