SparcISelLowering.cpp revision 33390848a7eca75301d04a59b89b516d83e19ee0
1533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org// 3533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org// The LLVM Compiler Infrastructure 4533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org// 5533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org// This file is distributed under the University of Illinois Open Source 6533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org// License. See LICENSE.TXT for details. 7533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org// 8533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org//===----------------------------------------------------------------------===// 9533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org// 10533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org// This file implements the interfaces that Sparc uses to lower LLVM code into a 118b0e8ac5f582de80356019406e2975079bf0829dcommit-bot@chromium.org// selection DAG. 128b0e8ac5f582de80356019406e2975079bf0829dcommit-bot@chromium.org// 13533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org//===----------------------------------------------------------------------===// 14533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org 15533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "SparcISelLowering.h" 16533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "SparcTargetMachine.h" 17533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "SparcMachineFunctionInfo.h" 18cac5fd597f6e2495f50aaa6bcbe3dadc56f0b977commit-bot@chromium.org#include "llvm/DerivedTypes.h" 19cac5fd597f6e2495f50aaa6bcbe3dadc56f0b977commit-bot@chromium.org#include "llvm/Function.h" 20533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "llvm/Module.h" 21533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "llvm/CodeGen/CallingConvLower.h" 22533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "llvm/CodeGen/MachineFrameInfo.h" 23cac5fd597f6e2495f50aaa6bcbe3dadc56f0b977commit-bot@chromium.org#include "llvm/CodeGen/MachineFunction.h" 24533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "llvm/CodeGen/MachineInstrBuilder.h" 25533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "llvm/CodeGen/MachineRegisterInfo.h" 26cac5fd597f6e2495f50aaa6bcbe3dadc56f0b977commit-bot@chromium.org#include "llvm/CodeGen/SelectionDAG.h" 27533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 28533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "llvm/ADT/VectorExtras.h" 29533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "llvm/Support/ErrorHandling.h" 30533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.orgusing namespace llvm; 31533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org 32533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org 33533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org//===----------------------------------------------------------------------===// 348b0e8ac5f582de80356019406e2975079bf0829dcommit-bot@chromium.org// Calling Convention Implementation 35533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org//===----------------------------------------------------------------------===// 36533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org 3797f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.orgstatic bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, 3897f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org MVT &LocVT, CCValAssign::LocInfo &LocInfo, 3997f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org ISD::ArgFlagsTy &ArgFlags, CCState &State) 4097f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org{ 4197f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org assert (ArgFlags.isSRet()); 4297f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org 435e0995e4b36178e1e4465a9f50114ed39f038c27commit-bot@chromium.org //Assign SRet argument 44cac5fd597f6e2495f50aaa6bcbe3dadc56f0b977commit-bot@chromium.org State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 45533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org 0, 46533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org LocVT, LocInfo)); 478b0e8ac5f582de80356019406e2975079bf0829dcommit-bot@chromium.org return true; 48533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org} 4997f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org 5097f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.orgstatic bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, 5197f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org MVT &LocVT, CCValAssign::LocInfo &LocInfo, 5297f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org ISD::ArgFlagsTy &ArgFlags, CCState &State) 5397f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org{ 5497f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org static const unsigned RegList[] = { 5597f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 5697f5fc651956287e78e35934cf62b9e1b45b4f6csenorblanco@chromium.org }; 575e0995e4b36178e1e4465a9f50114ed39f038c27commit-bot@chromium.org //Try to get first reg 58cac5fd597f6e2495f50aaa6bcbe3dadc56f0b977commit-bot@chromium.org if (unsigned Reg = State.AllocateReg(RegList, 6)) { 59533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 60533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org } else { 614cb543d6057b692e1099e9f115155f0bf323a0c8senorblanco@chromium.org //Assign whole thing in stack 624cb543d6057b692e1099e9f115155f0bf323a0c8senorblanco@chromium.org State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 63533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org State.AllocateStack(8,4), 646776b82d466fa93ccffd251fdf556fe058395444senorblanco@chromium.org LocVT, LocInfo)); 65533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org return true; 66533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org } 67533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org 68533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org //Try to get second reg 69533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org if (unsigned Reg = State.AllocateReg(RegList, 6)) 704cb543d6057b692e1099e9f115155f0bf323a0c8senorblanco@chromium.org State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 71533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org else 72533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 73533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org State.AllocateStack(4,4), 746776b82d466fa93ccffd251fdf556fe058395444senorblanco@chromium.org LocVT, LocInfo)); 75533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org return true; 76533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org} 77533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org 78533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org#include "SparcGenCallingConv.inc" 79533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org 80533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.orgSDValue 81533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.orgSparcTargetLowering::LowerReturn(SDValue Chain, 82533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org CallingConv::ID CallConv, bool isVarArg, 83533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org const SmallVectorImpl<ISD::OutputArg> &Outs, 84533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org const SmallVectorImpl<SDValue> &OutVals, 85533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org DebugLoc dl, SelectionDAG &DAG) const { 86533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org 874cb543d6057b692e1099e9f115155f0bf323a0c8senorblanco@chromium.org MachineFunction &MF = DAG.getMachineFunction(); 889b14f26d0f3a974f3dd626c8354e1db1cfcd322frobertphillips 89533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org // CCValAssign - represent the assignment of the return value to locations. 90533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org SmallVector<CCValAssign, 16> RVLocs; 916776b82d466fa93ccffd251fdf556fe058395444senorblanco@chromium.org 926776b82d466fa93ccffd251fdf556fe058395444senorblanco@chromium.org // CCState - Info about the registers and stack slot. 93533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 94533330065a28b51808e5bf564ae45e56f8d9956asenorblanco@chromium.org DAG.getTarget(), RVLocs, *DAG.getContext()); 95910702b564048d77e36a68b0f8dda7cc48a8fcffsenorblanco@chromium.org 96910702b564048d77e36a68b0f8dda7cc48a8fcffsenorblanco@chromium.org // Analize return values. 97910702b564048d77e36a68b0f8dda7cc48a8fcffsenorblanco@chromium.org CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 98910702b564048d77e36a68b0f8dda7cc48a8fcffsenorblanco@chromium.org 99910702b564048d77e36a68b0f8dda7cc48a8fcffsenorblanco@chromium.org // If this is the first return lowered for this function, add the regs to the 100910702b564048d77e36a68b0f8dda7cc48a8fcffsenorblanco@chromium.org // liveout set for the function. 101910702b564048d77e36a68b0f8dda7cc48a8fcffsenorblanco@chromium.org if (MF.getRegInfo().liveout_empty()) { 102 for (unsigned i = 0; i != RVLocs.size(); ++i) 103 if (RVLocs[i].isRegLoc()) 104 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 105 } 106 107 SDValue Flag; 108 109 // Copy the result values into the output registers. 110 for (unsigned i = 0; i != RVLocs.size(); ++i) { 111 CCValAssign &VA = RVLocs[i]; 112 assert(VA.isRegLoc() && "Can only return in registers!"); 113 114 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 115 OutVals[i], Flag); 116 117 // Guarantee that all emitted copies are stuck together with flags. 118 Flag = Chain.getValue(1); 119 } 120 121 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot 122 // If the function returns a struct, copy the SRetReturnReg to I0 123 if (MF.getFunction()->hasStructRetAttr()) { 124 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 125 unsigned Reg = SFI->getSRetReturnReg(); 126 if (!Reg) 127 llvm_unreachable("sret virtual register not created in the entry block"); 128 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 129 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag); 130 Flag = Chain.getValue(1); 131 if (MF.getRegInfo().liveout_empty()) 132 MF.getRegInfo().addLiveOut(SP::I0); 133 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp 134 } 135 136 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32); 137 138 if (Flag.getNode()) 139 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, 140 RetAddrOffsetNode, Flag); 141 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, 142 RetAddrOffsetNode); 143} 144 145/// LowerFormalArguments - V8 uses a very simple ABI, where all values are 146/// passed in either one or two GPRs, including FP values. TODO: we should 147/// pass FP values in FP registers for fastcc functions. 148SDValue 149SparcTargetLowering::LowerFormalArguments(SDValue Chain, 150 CallingConv::ID CallConv, bool isVarArg, 151 const SmallVectorImpl<ISD::InputArg> 152 &Ins, 153 DebugLoc dl, SelectionDAG &DAG, 154 SmallVectorImpl<SDValue> &InVals) 155 const { 156 157 MachineFunction &MF = DAG.getMachineFunction(); 158 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 159 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 160 161 // Assign locations to all of the incoming arguments. 162 SmallVector<CCValAssign, 16> ArgLocs; 163 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 164 getTargetMachine(), ArgLocs, *DAG.getContext()); 165 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 166 167 const unsigned StackOffset = 92; 168 169 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 170 CCValAssign &VA = ArgLocs[i]; 171 172 if (i == 0 && Ins[i].Flags.isSRet()) { 173 //Get SRet from [%fp+64] 174 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); 175 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 176 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 177 MachinePointerInfo(), 178 false, false, 0); 179 InVals.push_back(Arg); 180 continue; 181 } 182 183 if (VA.isRegLoc()) { 184 if (VA.needsCustom()) { 185 assert(VA.getLocVT() == MVT::f64); 186 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 187 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 188 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 189 190 assert(i+1 < e); 191 CCValAssign &NextVA = ArgLocs[++i]; 192 193 SDValue LoVal; 194 if (NextVA.isMemLoc()) { 195 int FrameIdx = MF.getFrameInfo()-> 196 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); 197 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 198 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 199 MachinePointerInfo(), 200 false, false, 0); 201 } else { 202 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), 203 &SP::IntRegsRegClass); 204 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); 205 } 206 SDValue WholeValue = 207 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 208 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 209 InVals.push_back(WholeValue); 210 continue; 211 } 212 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 213 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 214 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 215 if (VA.getLocVT() == MVT::f32) 216 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 217 else if (VA.getLocVT() != MVT::i32) { 218 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 219 DAG.getValueType(VA.getLocVT())); 220 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); 221 } 222 InVals.push_back(Arg); 223 continue; 224 } 225 226 assert(VA.isMemLoc()); 227 228 unsigned Offset = VA.getLocMemOffset()+StackOffset; 229 230 if (VA.needsCustom()) { 231 assert(VA.getValVT() == MVT::f64); 232 //If it is double-word aligned, just load. 233 if (Offset % 8 == 0) { 234 int FI = MF.getFrameInfo()->CreateFixedObject(8, 235 Offset, 236 true); 237 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 238 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 239 MachinePointerInfo(), 240 false,false, 0); 241 InVals.push_back(Load); 242 continue; 243 } 244 245 int FI = MF.getFrameInfo()->CreateFixedObject(4, 246 Offset, 247 true); 248 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 249 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 250 MachinePointerInfo(), 251 false, false, 0); 252 int FI2 = MF.getFrameInfo()->CreateFixedObject(4, 253 Offset+4, 254 true); 255 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy()); 256 257 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, 258 MachinePointerInfo(), 259 false, false, 0); 260 261 SDValue WholeValue = 262 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 263 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 264 InVals.push_back(WholeValue); 265 continue; 266 } 267 268 int FI = MF.getFrameInfo()->CreateFixedObject(4, 269 Offset, 270 true); 271 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 272 SDValue Load ; 273 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { 274 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 275 MachinePointerInfo(), 276 false, false, 0); 277 } else { 278 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 279 // Sparc is big endian, so add an offset based on the ObjectVT. 280 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); 281 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 282 DAG.getConstant(Offset, MVT::i32)); 283 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, 284 MachinePointerInfo(), 285 VA.getValVT(), false, false,0); 286 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); 287 } 288 InVals.push_back(Load); 289 } 290 291 if (MF.getFunction()->hasStructRetAttr()) { 292 //Copy the SRet Argument to SRetReturnReg 293 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 294 unsigned Reg = SFI->getSRetReturnReg(); 295 if (!Reg) { 296 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); 297 SFI->setSRetReturnReg(Reg); 298 } 299 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 300 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 301 } 302 303 // Store remaining ArgRegs to the stack if this is a varargs function. 304 if (isVarArg) { 305 static const unsigned ArgRegs[] = { 306 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 307 }; 308 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); 309 const unsigned *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; 310 unsigned ArgOffset = CCInfo.getNextStackOffset(); 311 if (NumAllocated == 6) 312 ArgOffset += StackOffset; 313 else { 314 assert(!ArgOffset); 315 ArgOffset = 68+4*NumAllocated; 316 } 317 318 // Remember the vararg offset for the va_start implementation. 319 FuncInfo->setVarArgsFrameOffset(ArgOffset); 320 321 std::vector<SDValue> OutChains; 322 323 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 324 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 325 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 326 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 327 328 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 329 true); 330 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 331 332 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, 333 MachinePointerInfo(), 334 false, false, 0)); 335 ArgOffset += 4; 336 } 337 338 if (!OutChains.empty()) { 339 OutChains.push_back(Chain); 340 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 341 &OutChains[0], OutChains.size()); 342 } 343 } 344 345 return Chain; 346} 347 348SDValue 349SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 350 CallingConv::ID CallConv, bool isVarArg, 351 bool &isTailCall, 352 const SmallVectorImpl<ISD::OutputArg> &Outs, 353 const SmallVectorImpl<SDValue> &OutVals, 354 const SmallVectorImpl<ISD::InputArg> &Ins, 355 DebugLoc dl, SelectionDAG &DAG, 356 SmallVectorImpl<SDValue> &InVals) const { 357 // Sparc target does not yet support tail call optimization. 358 isTailCall = false; 359 360 // Analyze operands of the call, assigning locations to each operand. 361 SmallVector<CCValAssign, 16> ArgLocs; 362 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 363 DAG.getTarget(), ArgLocs, *DAG.getContext()); 364 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 365 366 // Get the size of the outgoing arguments stack space requirement. 367 unsigned ArgsSize = CCInfo.getNextStackOffset(); 368 369 // Keep stack frames 8-byte aligned. 370 ArgsSize = (ArgsSize+7) & ~7; 371 372 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 373 374 //Create local copies for byval args. 375 SmallVector<SDValue, 8> ByValArgs; 376 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 377 ISD::ArgFlagsTy Flags = Outs[i].Flags; 378 if (!Flags.isByVal()) 379 continue; 380 381 SDValue Arg = OutVals[i]; 382 unsigned Size = Flags.getByValSize(); 383 unsigned Align = Flags.getByValAlign(); 384 385 int FI = MFI->CreateStackObject(Size, Align, false); 386 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 387 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 388 389 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, 390 false, //isVolatile, 391 (Size <= 32), //AlwaysInline if size <= 32 392 MachinePointerInfo(), MachinePointerInfo()); 393 ByValArgs.push_back(FIPtr); 394 } 395 396 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 397 398 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 399 SmallVector<SDValue, 8> MemOpChains; 400 401 const unsigned StackOffset = 92; 402 bool hasStructRetAttr = false; 403 // Walk the register/memloc assignments, inserting copies/loads. 404 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size(); 405 i != e; 406 ++i, ++realArgIdx) { 407 CCValAssign &VA = ArgLocs[i]; 408 SDValue Arg = OutVals[realArgIdx]; 409 410 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 411 412 //Use local copy if it is a byval arg. 413 if (Flags.isByVal()) 414 Arg = ByValArgs[byvalArgIdx++]; 415 416 // Promote the value if needed. 417 switch (VA.getLocInfo()) { 418 default: llvm_unreachable("Unknown loc info!"); 419 case CCValAssign::Full: break; 420 case CCValAssign::SExt: 421 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 422 break; 423 case CCValAssign::ZExt: 424 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 425 break; 426 case CCValAssign::AExt: 427 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 428 break; 429 case CCValAssign::BCvt: 430 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 431 break; 432 } 433 434 if (Flags.isSRet()) { 435 assert(VA.needsCustom()); 436 // store SRet argument in %sp+64 437 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 438 SDValue PtrOff = DAG.getIntPtrConstant(64); 439 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 440 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 441 MachinePointerInfo(), 442 false, false, 0)); 443 hasStructRetAttr = true; 444 continue; 445 } 446 447 if (VA.needsCustom()) { 448 assert(VA.getLocVT() == MVT::f64); 449 450 if (VA.isMemLoc()) { 451 unsigned Offset = VA.getLocMemOffset() + StackOffset; 452 //if it is double-word aligned, just store. 453 if (Offset % 8 == 0) { 454 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 455 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 456 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 457 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 458 MachinePointerInfo(), 459 false, false, 0)); 460 continue; 461 } 462 } 463 464 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 465 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 466 Arg, StackPtr, MachinePointerInfo(), 467 false, false, 0); 468 // Sparc is big-endian, so the high part comes first. 469 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 470 MachinePointerInfo(), false, false, 0); 471 // Increment the pointer to the other half. 472 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 473 DAG.getIntPtrConstant(4)); 474 // Load the low part. 475 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 476 MachinePointerInfo(), false, false, 0); 477 478 if (VA.isRegLoc()) { 479 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); 480 assert(i+1 != e); 481 CCValAssign &NextVA = ArgLocs[++i]; 482 if (NextVA.isRegLoc()) { 483 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 484 } else { 485 //Store the low part in stack. 486 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; 487 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 488 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 489 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 490 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 491 MachinePointerInfo(), 492 false, false, 0)); 493 } 494 } else { 495 unsigned Offset = VA.getLocMemOffset() + StackOffset; 496 // Store the high part. 497 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 498 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 499 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 500 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, 501 MachinePointerInfo(), 502 false, false, 0)); 503 // Store the low part. 504 PtrOff = DAG.getIntPtrConstant(Offset+4); 505 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 506 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 507 MachinePointerInfo(), 508 false, false, 0)); 509 } 510 continue; 511 } 512 513 // Arguments that can be passed on register must be kept at 514 // RegsToPass vector 515 if (VA.isRegLoc()) { 516 if (VA.getLocVT() != MVT::f32) { 517 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 518 continue; 519 } 520 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 521 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 522 continue; 523 } 524 525 assert(VA.isMemLoc()); 526 527 // Create a store off the stack pointer for this argument. 528 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 529 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); 530 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 531 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 532 MachinePointerInfo(), 533 false, false, 0)); 534 } 535 536 537 // Emit all stores, make sure the occur before any copies into physregs. 538 if (!MemOpChains.empty()) 539 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 540 &MemOpChains[0], MemOpChains.size()); 541 542 // Build a sequence of copy-to-reg nodes chained together with token 543 // chain and flag operands which copy the outgoing args into registers. 544 // The InFlag in necessary since all emitted instructions must be 545 // stuck together. 546 SDValue InFlag; 547 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 548 unsigned Reg = RegsToPass[i].first; 549 // Remap I0->I7 -> O0->O7. 550 if (Reg >= SP::I0 && Reg <= SP::I7) 551 Reg = Reg-SP::I0+SP::O0; 552 553 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 554 InFlag = Chain.getValue(1); 555 } 556 557 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0; 558 559 // If the callee is a GlobalAddress node (quite common, every direct call is) 560 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 561 // Likewise ExternalSymbol -> TargetExternalSymbol. 562 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 563 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 564 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 565 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 566 567 // Returns a chain & a flag for retval copy to use 568 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 569 SmallVector<SDValue, 8> Ops; 570 Ops.push_back(Chain); 571 Ops.push_back(Callee); 572 if (hasStructRetAttr) 573 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); 574 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 575 unsigned Reg = RegsToPass[i].first; 576 if (Reg >= SP::I0 && Reg <= SP::I7) 577 Reg = Reg-SP::I0+SP::O0; 578 579 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType())); 580 } 581 if (InFlag.getNode()) 582 Ops.push_back(InFlag); 583 584 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 585 InFlag = Chain.getValue(1); 586 587 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 588 DAG.getIntPtrConstant(0, true), InFlag); 589 InFlag = Chain.getValue(1); 590 591 // Assign locations to each value returned by this call. 592 SmallVector<CCValAssign, 16> RVLocs; 593 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), 594 DAG.getTarget(), RVLocs, *DAG.getContext()); 595 596 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 597 598 // Copy all of the result registers out of their specified physreg. 599 for (unsigned i = 0; i != RVLocs.size(); ++i) { 600 unsigned Reg = RVLocs[i].getLocReg(); 601 602 // Remap I0->I7 -> O0->O7. 603 if (Reg >= SP::I0 && Reg <= SP::I7) 604 Reg = Reg-SP::I0+SP::O0; 605 606 Chain = DAG.getCopyFromReg(Chain, dl, Reg, 607 RVLocs[i].getValVT(), InFlag).getValue(1); 608 InFlag = Chain.getValue(2); 609 InVals.push_back(Chain.getValue(0)); 610 } 611 612 return Chain; 613} 614 615unsigned 616SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const 617{ 618 const Function *CalleeFn = 0; 619 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 620 CalleeFn = dyn_cast<Function>(G->getGlobal()); 621 } else if (ExternalSymbolSDNode *E = 622 dyn_cast<ExternalSymbolSDNode>(Callee)) { 623 const Function *Fn = DAG.getMachineFunction().getFunction(); 624 const Module *M = Fn->getParent(); 625 CalleeFn = M->getFunction(E->getSymbol()); 626 } 627 628 if (!CalleeFn) 629 return 0; 630 631 assert(CalleeFn->hasStructRetAttr() && 632 "Callee does not have the StructRet attribute."); 633 634 const PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType()); 635 const Type *ElementTy = Ty->getElementType(); 636 return getTargetData()->getTypeAllocSize(ElementTy); 637} 638 639//===----------------------------------------------------------------------===// 640// TargetLowering Implementation 641//===----------------------------------------------------------------------===// 642 643/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 644/// condition. 645static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 646 switch (CC) { 647 default: llvm_unreachable("Unknown integer condition code!"); 648 case ISD::SETEQ: return SPCC::ICC_E; 649 case ISD::SETNE: return SPCC::ICC_NE; 650 case ISD::SETLT: return SPCC::ICC_L; 651 case ISD::SETGT: return SPCC::ICC_G; 652 case ISD::SETLE: return SPCC::ICC_LE; 653 case ISD::SETGE: return SPCC::ICC_GE; 654 case ISD::SETULT: return SPCC::ICC_CS; 655 case ISD::SETULE: return SPCC::ICC_LEU; 656 case ISD::SETUGT: return SPCC::ICC_GU; 657 case ISD::SETUGE: return SPCC::ICC_CC; 658 } 659} 660 661/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 662/// FCC condition. 663static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 664 switch (CC) { 665 default: llvm_unreachable("Unknown fp condition code!"); 666 case ISD::SETEQ: 667 case ISD::SETOEQ: return SPCC::FCC_E; 668 case ISD::SETNE: 669 case ISD::SETUNE: return SPCC::FCC_NE; 670 case ISD::SETLT: 671 case ISD::SETOLT: return SPCC::FCC_L; 672 case ISD::SETGT: 673 case ISD::SETOGT: return SPCC::FCC_G; 674 case ISD::SETLE: 675 case ISD::SETOLE: return SPCC::FCC_LE; 676 case ISD::SETGE: 677 case ISD::SETOGE: return SPCC::FCC_GE; 678 case ISD::SETULT: return SPCC::FCC_UL; 679 case ISD::SETULE: return SPCC::FCC_ULE; 680 case ISD::SETUGT: return SPCC::FCC_UG; 681 case ISD::SETUGE: return SPCC::FCC_UGE; 682 case ISD::SETUO: return SPCC::FCC_U; 683 case ISD::SETO: return SPCC::FCC_O; 684 case ISD::SETONE: return SPCC::FCC_LG; 685 case ISD::SETUEQ: return SPCC::FCC_UE; 686 } 687} 688 689SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 690 : TargetLowering(TM, new TargetLoweringObjectFileELF()) { 691 692 // Set up the register classes. 693 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 694 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 695 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 696 697 // Turn FP extload into load/fextend 698 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 699 // Sparc doesn't have i1 sign extending load 700 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 701 // Turn FP truncstore into trunc + store. 702 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 703 704 // Custom legalize GlobalAddress nodes into LO/HI parts. 705 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 706 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 707 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 708 709 // Sparc doesn't have sext_inreg, replace them with shl/sra 710 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 711 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 712 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 713 714 // Sparc has no REM or DIVREM operations. 715 setOperationAction(ISD::UREM, MVT::i32, Expand); 716 setOperationAction(ISD::SREM, MVT::i32, Expand); 717 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 718 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 719 720 // Custom expand fp<->sint 721 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 722 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 723 724 // Expand fp<->uint 725 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 726 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 727 728 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 729 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 730 731 // Sparc has no select or setcc: expand to SELECT_CC. 732 setOperationAction(ISD::SELECT, MVT::i32, Expand); 733 setOperationAction(ISD::SELECT, MVT::f32, Expand); 734 setOperationAction(ISD::SELECT, MVT::f64, Expand); 735 setOperationAction(ISD::SETCC, MVT::i32, Expand); 736 setOperationAction(ISD::SETCC, MVT::f32, Expand); 737 setOperationAction(ISD::SETCC, MVT::f64, Expand); 738 739 // Sparc doesn't have BRCOND either, it has BR_CC. 740 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 741 setOperationAction(ISD::BRIND, MVT::Other, Expand); 742 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 743 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 744 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 745 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 746 747 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 748 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 749 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 750 751 // SPARC has no intrinsics for these particular operations. 752 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 753 754 setOperationAction(ISD::FSIN , MVT::f64, Expand); 755 setOperationAction(ISD::FCOS , MVT::f64, Expand); 756 setOperationAction(ISD::FREM , MVT::f64, Expand); 757 setOperationAction(ISD::FMA , MVT::f64, Expand); 758 setOperationAction(ISD::FSIN , MVT::f32, Expand); 759 setOperationAction(ISD::FCOS , MVT::f32, Expand); 760 setOperationAction(ISD::FREM , MVT::f32, Expand); 761 setOperationAction(ISD::FMA , MVT::f32, Expand); 762 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 763 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 764 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 765 setOperationAction(ISD::ROTL , MVT::i32, Expand); 766 setOperationAction(ISD::ROTR , MVT::i32, Expand); 767 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 768 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 769 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 770 setOperationAction(ISD::FPOW , MVT::f64, Expand); 771 setOperationAction(ISD::FPOW , MVT::f32, Expand); 772 773 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 774 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 775 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 776 777 // FIXME: Sparc provides these multiplies, but we don't have them yet. 778 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 779 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 780 781 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 782 783 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 784 setOperationAction(ISD::VASTART , MVT::Other, Custom); 785 // VAARG needs to be lowered to not do unaligned accesses for doubles. 786 setOperationAction(ISD::VAARG , MVT::Other, Custom); 787 788 // Use the default implementation. 789 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 790 setOperationAction(ISD::VAEND , MVT::Other, Expand); 791 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 792 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 793 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 794 795 // No debug info support yet. 796 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 797 798 setStackPointerRegisterToSaveRestore(SP::O6); 799 800 if (TM.getSubtarget<SparcSubtarget>().isV9()) 801 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 802 803 setMinFunctionAlignment(2); 804 805 computeRegisterProperties(); 806} 807 808const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 809 switch (Opcode) { 810 default: return 0; 811 case SPISD::CMPICC: return "SPISD::CMPICC"; 812 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 813 case SPISD::BRICC: return "SPISD::BRICC"; 814 case SPISD::BRFCC: return "SPISD::BRFCC"; 815 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 816 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 817 case SPISD::Hi: return "SPISD::Hi"; 818 case SPISD::Lo: return "SPISD::Lo"; 819 case SPISD::FTOI: return "SPISD::FTOI"; 820 case SPISD::ITOF: return "SPISD::ITOF"; 821 case SPISD::CALL: return "SPISD::CALL"; 822 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 823 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; 824 case SPISD::FLUSHW: return "SPISD::FLUSHW"; 825 } 826} 827 828/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 829/// be zero. Op is expected to be a target specific node. Used by DAG 830/// combiner. 831void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 832 const APInt &Mask, 833 APInt &KnownZero, 834 APInt &KnownOne, 835 const SelectionDAG &DAG, 836 unsigned Depth) const { 837 APInt KnownZero2, KnownOne2; 838 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 839 840 switch (Op.getOpcode()) { 841 default: break; 842 case SPISD::SELECT_ICC: 843 case SPISD::SELECT_FCC: 844 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 845 Depth+1); 846 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 847 Depth+1); 848 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 849 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 850 851 // Only known if known in both the LHS and RHS. 852 KnownOne &= KnownOne2; 853 KnownZero &= KnownZero2; 854 break; 855 } 856} 857 858// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 859// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 860static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 861 ISD::CondCode CC, unsigned &SPCC) { 862 if (isa<ConstantSDNode>(RHS) && 863 cast<ConstantSDNode>(RHS)->isNullValue() && 864 CC == ISD::SETNE && 865 ((LHS.getOpcode() == SPISD::SELECT_ICC && 866 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 867 (LHS.getOpcode() == SPISD::SELECT_FCC && 868 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 869 isa<ConstantSDNode>(LHS.getOperand(0)) && 870 isa<ConstantSDNode>(LHS.getOperand(1)) && 871 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && 872 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { 873 SDValue CMPCC = LHS.getOperand(3); 874 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 875 LHS = CMPCC.getOperand(0); 876 RHS = CMPCC.getOperand(1); 877 } 878} 879 880SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, 881 SelectionDAG &DAG) const { 882 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 883 // FIXME there isn't really any debug info here 884 DebugLoc dl = Op.getDebugLoc(); 885 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32); 886 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA); 887 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA); 888 889 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 890 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 891 892 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 893 getPointerTy()); 894 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 895 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 896 GlobalBase, RelAddr); 897 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 898 AbsAddr, MachinePointerInfo(), false, false, 0); 899} 900 901SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, 902 SelectionDAG &DAG) const { 903 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 904 // FIXME there isn't really any debug info here 905 DebugLoc dl = Op.getDebugLoc(); 906 const Constant *C = N->getConstVal(); 907 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); 908 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP); 909 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP); 910 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 911 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 912 913 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 914 getPointerTy()); 915 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 916 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 917 GlobalBase, RelAddr); 918 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 919 AbsAddr, MachinePointerInfo(), false, false, 0); 920} 921 922static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 923 DebugLoc dl = Op.getDebugLoc(); 924 // Convert the fp value to integer in an FP register. 925 assert(Op.getValueType() == MVT::i32); 926 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 927 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 928} 929 930static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 931 DebugLoc dl = Op.getDebugLoc(); 932 assert(Op.getOperand(0).getValueType() == MVT::i32); 933 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 934 // Convert the int value to FP in an FP register. 935 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp); 936} 937 938static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 939 SDValue Chain = Op.getOperand(0); 940 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 941 SDValue LHS = Op.getOperand(2); 942 SDValue RHS = Op.getOperand(3); 943 SDValue Dest = Op.getOperand(4); 944 DebugLoc dl = Op.getDebugLoc(); 945 unsigned Opc, SPCC = ~0U; 946 947 // If this is a br_cc of a "setcc", and if the setcc got lowered into 948 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 949 LookThroughSetCC(LHS, RHS, CC, SPCC); 950 951 // Get the condition flag. 952 SDValue CompareFlag; 953 if (LHS.getValueType() == MVT::i32) { 954 std::vector<EVT> VTs; 955 VTs.push_back(MVT::i32); 956 VTs.push_back(MVT::Glue); 957 SDValue Ops[2] = { LHS, RHS }; 958 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 959 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 960 Opc = SPISD::BRICC; 961 } else { 962 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 963 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 964 Opc = SPISD::BRFCC; 965 } 966 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 967 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 968} 969 970static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 971 SDValue LHS = Op.getOperand(0); 972 SDValue RHS = Op.getOperand(1); 973 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 974 SDValue TrueVal = Op.getOperand(2); 975 SDValue FalseVal = Op.getOperand(3); 976 DebugLoc dl = Op.getDebugLoc(); 977 unsigned Opc, SPCC = ~0U; 978 979 // If this is a select_cc of a "setcc", and if the setcc got lowered into 980 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 981 LookThroughSetCC(LHS, RHS, CC, SPCC); 982 983 SDValue CompareFlag; 984 if (LHS.getValueType() == MVT::i32) { 985 std::vector<EVT> VTs; 986 VTs.push_back(LHS.getValueType()); // subcc returns a value 987 VTs.push_back(MVT::Glue); 988 SDValue Ops[2] = { LHS, RHS }; 989 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 990 Opc = SPISD::SELECT_ICC; 991 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 992 } else { 993 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 994 Opc = SPISD::SELECT_FCC; 995 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 996 } 997 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 998 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 999} 1000 1001static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 1002 const SparcTargetLowering &TLI) { 1003 MachineFunction &MF = DAG.getMachineFunction(); 1004 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 1005 1006 // vastart just stores the address of the VarArgsFrameIndex slot into the 1007 // memory location argument. 1008 DebugLoc dl = Op.getDebugLoc(); 1009 SDValue Offset = 1010 DAG.getNode(ISD::ADD, dl, MVT::i32, 1011 DAG.getRegister(SP::I6, MVT::i32), 1012 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(), 1013 MVT::i32)); 1014 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1015 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), 1016 MachinePointerInfo(SV), false, false, 0); 1017} 1018 1019static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 1020 SDNode *Node = Op.getNode(); 1021 EVT VT = Node->getValueType(0); 1022 SDValue InChain = Node->getOperand(0); 1023 SDValue VAListPtr = Node->getOperand(1); 1024 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1025 DebugLoc dl = Node->getDebugLoc(); 1026 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, 1027 MachinePointerInfo(SV), false, false, 0); 1028 // Increment the pointer, VAList, to the next vaarg 1029 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, 1030 DAG.getConstant(VT.getSizeInBits()/8, 1031 MVT::i32)); 1032 // Store the incremented VAList to the legalized pointer 1033 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr, 1034 VAListPtr, MachinePointerInfo(SV), false, false, 0); 1035 // Load the actual argument out of the pointer VAList, unless this is an 1036 // f64 load. 1037 if (VT != MVT::f64) 1038 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(), 1039 false, false, 0); 1040 1041 // Otherwise, load it as i64, then do a bitconvert. 1042 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(), 1043 false, false, 0); 1044 1045 // Bit-Convert the value to f64. 1046 SDValue Ops[2] = { 1047 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V), 1048 V.getValue(1) 1049 }; 1050 return DAG.getMergeValues(Ops, 2, dl); 1051} 1052 1053static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { 1054 SDValue Chain = Op.getOperand(0); // Legalize the chain. 1055 SDValue Size = Op.getOperand(1); // Legalize the size. 1056 DebugLoc dl = Op.getDebugLoc(); 1057 1058 unsigned SPReg = SP::O6; 1059 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 1060 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value 1061 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 1062 1063 // The resultant pointer is actually 16 words from the bottom of the stack, 1064 // to provide a register spill area. 1065 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, 1066 DAG.getConstant(96, MVT::i32)); 1067 SDValue Ops[2] = { NewVal, Chain }; 1068 return DAG.getMergeValues(Ops, 2, dl); 1069} 1070 1071 1072static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { 1073 DebugLoc dl = Op.getDebugLoc(); 1074 SDValue Chain = DAG.getNode(SPISD::FLUSHW, 1075 dl, MVT::Other, DAG.getEntryNode()); 1076 return Chain; 1077} 1078 1079static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 1080 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1081 MFI->setFrameAddressIsTaken(true); 1082 1083 EVT VT = Op.getValueType(); 1084 DebugLoc dl = Op.getDebugLoc(); 1085 unsigned FrameReg = SP::I6; 1086 1087 uint64_t depth = Op.getConstantOperandVal(0); 1088 1089 SDValue FrameAddr; 1090 if (depth == 0) 1091 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 1092 else { 1093 // flush first to make sure the windowed registers' values are in stack 1094 SDValue Chain = getFLUSHW(Op, DAG); 1095 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); 1096 1097 for (uint64_t i = 0; i != depth; ++i) { 1098 SDValue Ptr = DAG.getNode(ISD::ADD, 1099 dl, MVT::i32, 1100 FrameAddr, DAG.getIntPtrConstant(56)); 1101 FrameAddr = DAG.getLoad(MVT::i32, dl, 1102 Chain, 1103 Ptr, 1104 MachinePointerInfo(), false, false, 0); 1105 } 1106 } 1107 return FrameAddr; 1108} 1109 1110static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 1111 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1112 MFI->setReturnAddressIsTaken(true); 1113 1114 EVT VT = Op.getValueType(); 1115 DebugLoc dl = Op.getDebugLoc(); 1116 unsigned RetReg = SP::I7; 1117 1118 uint64_t depth = Op.getConstantOperandVal(0); 1119 1120 SDValue RetAddr; 1121 if (depth == 0) 1122 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); 1123 else { 1124 // flush first to make sure the windowed registers' values are in stack 1125 SDValue Chain = getFLUSHW(Op, DAG); 1126 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT); 1127 1128 for (uint64_t i = 0; i != depth; ++i) { 1129 SDValue Ptr = DAG.getNode(ISD::ADD, 1130 dl, MVT::i32, 1131 RetAddr, 1132 DAG.getIntPtrConstant((i == depth-1)?60:56)); 1133 RetAddr = DAG.getLoad(MVT::i32, dl, 1134 Chain, 1135 Ptr, 1136 MachinePointerInfo(), false, false, 0); 1137 } 1138 } 1139 return RetAddr; 1140} 1141 1142SDValue SparcTargetLowering:: 1143LowerOperation(SDValue Op, SelectionDAG &DAG) const { 1144 switch (Op.getOpcode()) { 1145 default: llvm_unreachable("Should not custom lower this!"); 1146 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1147 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1148 case ISD::GlobalTLSAddress: 1149 llvm_unreachable("TLS not implemented for Sparc."); 1150 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 1151 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1152 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 1153 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 1154 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 1155 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1156 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 1157 case ISD::VAARG: return LowerVAARG(Op, DAG); 1158 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 1159 } 1160} 1161 1162MachineBasicBlock * 1163SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1164 MachineBasicBlock *BB) const { 1165 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1166 unsigned BROpcode; 1167 unsigned CC; 1168 DebugLoc dl = MI->getDebugLoc(); 1169 // Figure out the conditional branch opcode to use for this select_cc. 1170 switch (MI->getOpcode()) { 1171 default: llvm_unreachable("Unknown SELECT_CC!"); 1172 case SP::SELECT_CC_Int_ICC: 1173 case SP::SELECT_CC_FP_ICC: 1174 case SP::SELECT_CC_DFP_ICC: 1175 BROpcode = SP::BCOND; 1176 break; 1177 case SP::SELECT_CC_Int_FCC: 1178 case SP::SELECT_CC_FP_FCC: 1179 case SP::SELECT_CC_DFP_FCC: 1180 BROpcode = SP::FBCOND; 1181 break; 1182 } 1183 1184 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 1185 1186 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1187 // control-flow pattern. The incoming instruction knows the destination vreg 1188 // to set, the condition code register to branch on, the true/false values to 1189 // select between, and a branch opcode to use. 1190 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1191 MachineFunction::iterator It = BB; 1192 ++It; 1193 1194 // thisMBB: 1195 // ... 1196 // TrueVal = ... 1197 // [f]bCC copy1MBB 1198 // fallthrough --> copy0MBB 1199 MachineBasicBlock *thisMBB = BB; 1200 MachineFunction *F = BB->getParent(); 1201 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1202 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1203 F->insert(It, copy0MBB); 1204 F->insert(It, sinkMBB); 1205 1206 // Transfer the remainder of BB and its successor edges to sinkMBB. 1207 sinkMBB->splice(sinkMBB->begin(), BB, 1208 llvm::next(MachineBasicBlock::iterator(MI)), 1209 BB->end()); 1210 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1211 1212 // Add the true and fallthrough blocks as its successors. 1213 BB->addSuccessor(copy0MBB); 1214 BB->addSuccessor(sinkMBB); 1215 1216 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 1217 1218 // copy0MBB: 1219 // %FalseValue = ... 1220 // # fallthrough to sinkMBB 1221 BB = copy0MBB; 1222 1223 // Update machine-CFG edges 1224 BB->addSuccessor(sinkMBB); 1225 1226 // sinkMBB: 1227 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1228 // ... 1229 BB = sinkMBB; 1230 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 1231 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1232 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1233 1234 MI->eraseFromParent(); // The pseudo instruction is gone now. 1235 return BB; 1236} 1237 1238//===----------------------------------------------------------------------===// 1239// Sparc Inline Assembly Support 1240//===----------------------------------------------------------------------===// 1241 1242/// getConstraintType - Given a constraint letter, return the type of 1243/// constraint it is for this target. 1244SparcTargetLowering::ConstraintType 1245SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 1246 if (Constraint.size() == 1) { 1247 switch (Constraint[0]) { 1248 default: break; 1249 case 'r': return C_RegisterClass; 1250 } 1251 } 1252 1253 return TargetLowering::getConstraintType(Constraint); 1254} 1255 1256std::pair<unsigned, const TargetRegisterClass*> 1257SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1258 EVT VT) const { 1259 if (Constraint.size() == 1) { 1260 switch (Constraint[0]) { 1261 case 'r': 1262 return std::make_pair(0U, SP::IntRegsRegisterClass); 1263 } 1264 } 1265 1266 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1267} 1268 1269bool 1270SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1271 // The Sparc target isn't yet aware of offsets. 1272 return false; 1273} 1274