SparcISelLowering.cpp revision 33c960f523f2308482d5b2816af46a7ec90a6d3d 
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "SparcISelLowering.h"
16#include "SparcTargetMachine.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24#include "llvm/ADT/VectorExtras.h"
25using namespace llvm;
26
27
28//===----------------------------------------------------------------------===//
29// Calling Convention Implementation
30//===----------------------------------------------------------------------===//
31
32#include "SparcGenCallingConv.inc"
33
34static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
35  // CCValAssign - represent the assignment of the return value to locations.
36  SmallVector<CCValAssign, 16> RVLocs;
37  unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
38  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
39
40  // CCState - Info about the registers and stack slot.
41  CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
42
43  // Analize return values of ISD::RET
44  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32);
45
46  // If this is the first return lowered for this function, add the regs to the
47  // liveout set for the function.
48  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
49    for (unsigned i = 0; i != RVLocs.size(); ++i)
50      if (RVLocs[i].isRegLoc())
51        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
52  }
53
54  SDValue Chain = Op.getOperand(0);
55  SDValue Flag;
56
57  // Copy the result values into the output registers.
58  for (unsigned i = 0; i != RVLocs.size(); ++i) {
59    CCValAssign &VA = RVLocs[i];
60    assert(VA.isRegLoc() && "Can only return in registers!");
61
62    // ISD::RET => ret chain, (regnum1,val1), ...
63    // So i*2+1 index only the regnums.
64    Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
65
66    // Guarantee that all emitted copies are stuck together with flags.
67    Flag = Chain.getValue(1);
68  }
69
70  if (Flag.getNode())
71    return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag);
72  return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain);
73}
74
75/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
76/// either one or two GPRs, including FP values.  TODO: we should pass FP values
77/// in FP registers for fastcc functions.
78void
79SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
80                                    SmallVectorImpl<SDValue> &ArgValues,
81                                    DebugLoc dl) {
82  MachineFunction &MF = DAG.getMachineFunction();
83  MachineRegisterInfo &RegInfo = MF.getRegInfo();
84
85  static const unsigned ArgRegs[] = {
86    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
87  };
88
89  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
90  unsigned ArgOffset = 68;
91
92  SDValue Root = DAG.getRoot();
93  std::vector<SDValue> OutChains;
94
95  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
96    MVT ObjectVT = getValueType(I->getType());
97
98    switch (ObjectVT.getSimpleVT()) {
99    default: assert(0 && "Unhandled argument type!");
100    case MVT::i1:
101    case MVT::i8:
102    case MVT::i16:
103    case MVT::i32:
104      if (I->use_empty()) {                // Argument is dead.
105        if (CurArgReg < ArgRegEnd) ++CurArgReg;
106        ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT));
107      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
108        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
109        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
110        SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
111        if (ObjectVT != MVT::i32) {
112          unsigned AssertOp = ISD::AssertSext;
113          Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg,
114                            DAG.getValueType(ObjectVT));
115          Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg);
116        }
117        ArgValues.push_back(Arg);
118      } else {
119        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
120        SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
121        SDValue Load;
122        if (ObjectVT == MVT::i32) {
123          Load = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
124        } else {
125          ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
126
127          // Sparc is big endian, so add an offset based on the ObjectVT.
128          unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
129          FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
130                              DAG.getConstant(Offset, MVT::i32));
131          Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Root, FIPtr,
132                                NULL, 0, ObjectVT);
133          Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
134        }
135        ArgValues.push_back(Load);
136      }
137
138      ArgOffset += 4;
139      break;
140    case MVT::f32:
141      if (I->use_empty()) {                // Argument is dead.
142        if (CurArgReg < ArgRegEnd) ++CurArgReg;
143        ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT));
144      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
145        // FP value is passed in an integer register.
146        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
147        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
148        SDValue Arg = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
149
150        Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg);
151        ArgValues.push_back(Arg);
152      } else {
153        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
154        SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
155        SDValue Load = DAG.getLoad(MVT::f32, dl, Root, FIPtr, NULL, 0);
156        ArgValues.push_back(Load);
157      }
158      ArgOffset += 4;
159      break;
160
161    case MVT::i64:
162    case MVT::f64:
163      if (I->use_empty()) {                // Argument is dead.
164        if (CurArgReg < ArgRegEnd) ++CurArgReg;
165        if (CurArgReg < ArgRegEnd) ++CurArgReg;
166        ArgValues.push_back(DAG.getNode(ISD::UNDEF, dl, ObjectVT));
167      } else {
168        SDValue HiVal;
169        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
170          unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
171          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
172          HiVal = DAG.getCopyFromReg(Root, dl, VRegHi, MVT::i32);
173        } else {
174          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
175          SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
176          HiVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
177        }
178
179        SDValue LoVal;
180        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
181          unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
182          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
183          LoVal = DAG.getCopyFromReg(Root, dl, VRegLo, MVT::i32);
184        } else {
185          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
186          SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
187          LoVal = DAG.getLoad(MVT::i32, dl, Root, FIPtr, NULL, 0);
188        }
189
190        // Compose the two halves together into an i64 unit.
191        SDValue WholeValue =
192          DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
193
194        // If we want a double, do a bit convert.
195        if (ObjectVT == MVT::f64)
196          WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue);
197
198        ArgValues.push_back(WholeValue);
199      }
200      ArgOffset += 8;
201      break;
202    }
203  }
204
205  // Store remaining ArgRegs to the stack if this is a varargs function.
206  if (F.isVarArg()) {
207    // Remember the vararg offset for the va_start implementation.
208    VarArgsFrameOffset = ArgOffset;
209
210    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
211      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
212      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
213      SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
214
215      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
216      SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
217
218      OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0));
219      ArgOffset += 4;
220    }
221  }
222
223  if (!OutChains.empty())
224    DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
225                            &OutChains[0], OutChains.size()));
226}
227
228static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) {
229  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
230  unsigned CallingConv = TheCall->getCallingConv();
231  SDValue Chain = TheCall->getChain();
232  SDValue Callee = TheCall->getCallee();
233  bool isVarArg = TheCall->isVarArg();
234  DebugLoc dl = TheCall->getDebugLoc();
235
236#if 0
237  // Analyze operands of the call, assigning locations to each operand.
238  SmallVector<CCValAssign, 16> ArgLocs;
239  CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs);
240  CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Sparc32);
241
242  // Get the size of the outgoing arguments stack space requirement.
243  unsigned ArgsSize = CCInfo.getNextStackOffset();
244  // FIXME: We can't use this until f64 is known to take two GPRs.
245#else
246  (void)CC_Sparc32;
247
248  // Count the size of the outgoing arguments.
249  unsigned ArgsSize = 0;
250  for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
251    switch (TheCall->getArg(i).getValueType().getSimpleVT()) {
252      default: assert(0 && "Unknown value type!");
253      case MVT::i1:
254      case MVT::i8:
255      case MVT::i16:
256      case MVT::i32:
257      case MVT::f32:
258        ArgsSize += 4;
259        break;
260      case MVT::i64:
261      case MVT::f64:
262        ArgsSize += 8;
263        break;
264    }
265  }
266  if (ArgsSize > 4*6)
267    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
268  else
269    ArgsSize = 0;
270#endif
271
272  // Keep stack frames 8-byte aligned.
273  ArgsSize = (ArgsSize+7) & ~7;
274
275  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
276
277  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
278  SmallVector<SDValue, 8> MemOpChains;
279
280#if 0
281  // Walk the register/memloc assignments, inserting copies/loads.
282  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
283    CCValAssign &VA = ArgLocs[i];
284
285    // Arguments start after the 5 first operands of ISD::CALL
286    SDValue Arg = TheCall->getArg(i);
287
288    // Promote the value if needed.
289    switch (VA.getLocInfo()) {
290    default: assert(0 && "Unknown loc info!");
291    case CCValAssign::Full: break;
292    case CCValAssign::SExt:
293      Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
294      break;
295    case CCValAssign::ZExt:
296      Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
297      break;
298    case CCValAssign::AExt:
299      Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
300      break;
301    }
302
303    // Arguments that can be passed on register must be kept at
304    // RegsToPass vector
305    if (VA.isRegLoc()) {
306      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
307      continue;
308    }
309
310    assert(VA.isMemLoc());
311
312    // Create a store off the stack pointer for this argument.
313    SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
314    // FIXME: VERIFY THAT 68 IS RIGHT.
315    SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
316    PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
317    MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
318  }
319
320#else
321  static const unsigned ArgRegs[] = {
322    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
323  };
324  unsigned ArgOffset = 68;
325
326  for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
327    SDValue Val = TheCall->getArg(i);
328    MVT ObjectVT = Val.getValueType();
329    SDValue ValToStore(0, 0);
330    unsigned ObjSize;
331    switch (ObjectVT.getSimpleVT()) {
332    default: assert(0 && "Unhandled argument type!");
333    case MVT::i32:
334      ObjSize = 4;
335
336      if (RegsToPass.size() >= 6) {
337        ValToStore = Val;
338      } else {
339        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
340      }
341      break;
342    case MVT::f32:
343      ObjSize = 4;
344      if (RegsToPass.size() >= 6) {
345        ValToStore = Val;
346      } else {
347        // Convert this to a FP value in an int reg.
348        Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val);
349        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
350      }
351      break;
352    case MVT::f64: {
353      ObjSize = 8;
354      if (RegsToPass.size() >= 6) {
355        ValToStore = Val;    // Whole thing is passed in memory.
356        break;
357      }
358
359      // Break into top and bottom parts by storing to the stack and loading
360      // out the parts as integers.  Top part goes in a reg.
361      SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
362      SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
363                                   Val, StackPtr, NULL, 0);
364      // Sparc is big-endian, so the high part comes first.
365      SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
366      // Increment the pointer to the other half.
367      StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
368                             DAG.getIntPtrConstant(4));
369      // Load the low part.
370      SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
371
372      RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
373
374      if (RegsToPass.size() >= 6) {
375        ValToStore = Lo;
376        ArgOffset += 4;
377        ObjSize = 4;
378      } else {
379        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
380      }
381      break;
382    }
383    case MVT::i64: {
384      ObjSize = 8;
385      if (RegsToPass.size() >= 6) {
386        ValToStore = Val;    // Whole thing is passed in memory.
387        break;
388      }
389
390      // Split the value into top and bottom part.  Top part goes in a reg.
391      SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
392                                 DAG.getConstant(1, MVT::i32));
393      SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
394                                 DAG.getConstant(0, MVT::i32));
395      RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
396
397      if (RegsToPass.size() >= 6) {
398        ValToStore = Lo;
399        ArgOffset += 4;
400        ObjSize = 4;
401      } else {
402        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
403      }
404      break;
405    }
406    }
407
408    if (ValToStore.getNode()) {
409      SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
410      SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
411      PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
412      MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore,
413                                         PtrOff, NULL, 0));
414    }
415    ArgOffset += ObjSize;
416  }
417#endif
418
419  // Emit all stores, make sure the occur before any copies into physregs.
420  if (!MemOpChains.empty())
421    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
422                        &MemOpChains[0], MemOpChains.size());
423
424  // Build a sequence of copy-to-reg nodes chained together with token
425  // chain and flag operands which copy the outgoing args into registers.
426  // The InFlag in necessary since all emited instructions must be
427  // stuck together.
428  SDValue InFlag;
429  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
430    unsigned Reg = RegsToPass[i].first;
431    // Remap I0->I7 -> O0->O7.
432    if (Reg >= SP::I0 && Reg <= SP::I7)
433      Reg = Reg-SP::I0+SP::O0;
434
435    Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
436    InFlag = Chain.getValue(1);
437  }
438
439  // If the callee is a GlobalAddress node (quite common, every direct call is)
440  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
441  // Likewise ExternalSymbol -> TargetExternalSymbol.
442  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
443    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
444  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
445    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
446
447  std::vector<MVT> NodeTys;
448  NodeTys.push_back(MVT::Other);   // Returns a chain
449  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
450  SDValue Ops[] = { Chain, Callee, InFlag };
451  Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
452  InFlag = Chain.getValue(1);
453
454  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
455                             DAG.getIntPtrConstant(0, true), InFlag);
456  InFlag = Chain.getValue(1);
457
458  // Assign locations to each value returned by this call.
459  SmallVector<CCValAssign, 16> RVLocs;
460  CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
461
462  RVInfo.AnalyzeCallResult(TheCall, RetCC_Sparc32);
463  SmallVector<SDValue, 8> ResultVals;
464
465  // Copy all of the result registers out of their specified physreg.
466  for (unsigned i = 0; i != RVLocs.size(); ++i) {
467    unsigned Reg = RVLocs[i].getLocReg();
468
469    // Remap I0->I7 -> O0->O7.
470    if (Reg >= SP::I0 && Reg <= SP::I7)
471      Reg = Reg-SP::I0+SP::O0;
472
473    Chain = DAG.getCopyFromReg(Chain, dl, Reg,
474                               RVLocs[i].getValVT(), InFlag).getValue(1);
475    InFlag = Chain.getValue(2);
476    ResultVals.push_back(Chain.getValue(0));
477  }
478
479  ResultVals.push_back(Chain);
480
481  // Merge everything together with a MERGE_VALUES node.
482  return DAG.getNode(ISD::MERGE_VALUES, dl,
483                     TheCall->getVTList(), &ResultVals[0],
484                     ResultVals.size());
485}
486
487
488
489//===----------------------------------------------------------------------===//
490// TargetLowering Implementation
491//===----------------------------------------------------------------------===//
492
493/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
494/// condition.
495static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
496  switch (CC) {
497  default: assert(0 && "Unknown integer condition code!");
498  case ISD::SETEQ:  return SPCC::ICC_E;
499  case ISD::SETNE:  return SPCC::ICC_NE;
500  case ISD::SETLT:  return SPCC::ICC_L;
501  case ISD::SETGT:  return SPCC::ICC_G;
502  case ISD::SETLE:  return SPCC::ICC_LE;
503  case ISD::SETGE:  return SPCC::ICC_GE;
504  case ISD::SETULT: return SPCC::ICC_CS;
505  case ISD::SETULE: return SPCC::ICC_LEU;
506  case ISD::SETUGT: return SPCC::ICC_GU;
507  case ISD::SETUGE: return SPCC::ICC_CC;
508  }
509}
510
511/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
512/// FCC condition.
513static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
514  switch (CC) {
515  default: assert(0 && "Unknown fp condition code!");
516  case ISD::SETEQ:
517  case ISD::SETOEQ: return SPCC::FCC_E;
518  case ISD::SETNE:
519  case ISD::SETUNE: return SPCC::FCC_NE;
520  case ISD::SETLT:
521  case ISD::SETOLT: return SPCC::FCC_L;
522  case ISD::SETGT:
523  case ISD::SETOGT: return SPCC::FCC_G;
524  case ISD::SETLE:
525  case ISD::SETOLE: return SPCC::FCC_LE;
526  case ISD::SETGE:
527  case ISD::SETOGE: return SPCC::FCC_GE;
528  case ISD::SETULT: return SPCC::FCC_UL;
529  case ISD::SETULE: return SPCC::FCC_ULE;
530  case ISD::SETUGT: return SPCC::FCC_UG;
531  case ISD::SETUGE: return SPCC::FCC_UGE;
532  case ISD::SETUO:  return SPCC::FCC_U;
533  case ISD::SETO:   return SPCC::FCC_O;
534  case ISD::SETONE: return SPCC::FCC_LG;
535  case ISD::SETUEQ: return SPCC::FCC_UE;
536  }
537}
538
539
540SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
541  : TargetLowering(TM) {
542
543  // Set up the register classes.
544  addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
545  addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
546  addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
547
548  // Turn FP extload into load/fextend
549  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
550  // Sparc doesn't have i1 sign extending load
551  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
552  // Turn FP truncstore into trunc + store.
553  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
554
555  // Custom legalize GlobalAddress nodes into LO/HI parts.
556  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
557  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
558  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
559
560  // Sparc doesn't have sext_inreg, replace them with shl/sra
561  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
562  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
563  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
564
565  // Sparc has no REM or DIVREM operations.
566  setOperationAction(ISD::UREM, MVT::i32, Expand);
567  setOperationAction(ISD::SREM, MVT::i32, Expand);
568  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
569  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
570
571  // Custom expand fp<->sint
572  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
573  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
574
575  // Expand fp<->uint
576  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
577  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
578
579  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
580  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
581
582  // Sparc has no select or setcc: expand to SELECT_CC.
583  setOperationAction(ISD::SELECT, MVT::i32, Expand);
584  setOperationAction(ISD::SELECT, MVT::f32, Expand);
585  setOperationAction(ISD::SELECT, MVT::f64, Expand);
586  setOperationAction(ISD::SETCC, MVT::i32, Expand);
587  setOperationAction(ISD::SETCC, MVT::f32, Expand);
588  setOperationAction(ISD::SETCC, MVT::f64, Expand);
589
590  // Sparc doesn't have BRCOND either, it has BR_CC.
591  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
592  setOperationAction(ISD::BRIND, MVT::Other, Expand);
593  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
594  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
595  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
596  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
597
598  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
599  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
600  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
601
602  // SPARC has no intrinsics for these particular operations.
603  setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
604
605  setOperationAction(ISD::FSIN , MVT::f64, Expand);
606  setOperationAction(ISD::FCOS , MVT::f64, Expand);
607  setOperationAction(ISD::FREM , MVT::f64, Expand);
608  setOperationAction(ISD::FSIN , MVT::f32, Expand);
609  setOperationAction(ISD::FCOS , MVT::f32, Expand);
610  setOperationAction(ISD::FREM , MVT::f32, Expand);
611  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
612  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
613  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
614  setOperationAction(ISD::ROTL , MVT::i32, Expand);
615  setOperationAction(ISD::ROTR , MVT::i32, Expand);
616  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
617  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
618  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
619  setOperationAction(ISD::FPOW , MVT::f64, Expand);
620  setOperationAction(ISD::FPOW , MVT::f32, Expand);
621
622  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
623  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
624  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
625
626  // FIXME: Sparc provides these multiplies, but we don't have them yet.
627  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
628  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
629
630  // We don't have line number support yet.
631  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
632  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
633  setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
634  setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
635
636  // RET must be custom lowered, to meet ABI requirements
637  setOperationAction(ISD::RET               , MVT::Other, Custom);
638
639  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
640  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
641  // VAARG needs to be lowered to not do unaligned accesses for doubles.
642  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
643
644  // Use the default implementation.
645  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
646  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
647  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
648  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
649  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
650
651  // No debug info support yet.
652  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
653  setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
654  setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
655  setOperationAction(ISD::DECLARE, MVT::Other, Expand);
656
657  setStackPointerRegisterToSaveRestore(SP::O6);
658
659  if (TM.getSubtarget<SparcSubtarget>().isV9())
660    setOperationAction(ISD::CTPOP, MVT::i32, Legal);
661
662  computeRegisterProperties();
663}
664
665const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
666  switch (Opcode) {
667  default: return 0;
668  case SPISD::CMPICC:     return "SPISD::CMPICC";
669  case SPISD::CMPFCC:     return "SPISD::CMPFCC";
670  case SPISD::BRICC:      return "SPISD::BRICC";
671  case SPISD::BRFCC:      return "SPISD::BRFCC";
672  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
673  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
674  case SPISD::Hi:         return "SPISD::Hi";
675  case SPISD::Lo:         return "SPISD::Lo";
676  case SPISD::FTOI:       return "SPISD::FTOI";
677  case SPISD::ITOF:       return "SPISD::ITOF";
678  case SPISD::CALL:       return "SPISD::CALL";
679  case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
680  }
681}
682
683/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
684/// be zero. Op is expected to be a target specific node. Used by DAG
685/// combiner.
686void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
687                                                         const APInt &Mask,
688                                                         APInt &KnownZero,
689                                                         APInt &KnownOne,
690                                                         const SelectionDAG &DAG,
691                                                         unsigned Depth) const {
692  APInt KnownZero2, KnownOne2;
693  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);   // Don't know anything.
694
695  switch (Op.getOpcode()) {
696  default: break;
697  case SPISD::SELECT_ICC:
698  case SPISD::SELECT_FCC:
699    DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
700                          Depth+1);
701    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
702                          Depth+1);
703    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
704    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
705
706    // Only known if known in both the LHS and RHS.
707    KnownOne &= KnownOne2;
708    KnownZero &= KnownZero2;
709    break;
710  }
711}
712
713// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
714// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
715static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
716                             ISD::CondCode CC, unsigned &SPCC) {
717  if (isa<ConstantSDNode>(RHS) &&
718      cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
719      CC == ISD::SETNE &&
720      ((LHS.getOpcode() == SPISD::SELECT_ICC &&
721        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
722       (LHS.getOpcode() == SPISD::SELECT_FCC &&
723        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
724      isa<ConstantSDNode>(LHS.getOperand(0)) &&
725      isa<ConstantSDNode>(LHS.getOperand(1)) &&
726      cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
727      cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
728    SDValue CMPCC = LHS.getOperand(3);
729    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
730    LHS = CMPCC.getOperand(0);
731    RHS = CMPCC.getOperand(1);
732  }
733}
734
735static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) {
736  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
737  SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
738  SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
739  SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
740  return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
741}
742
743static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
744  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
745  Constant *C = N->getConstVal();
746  SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
747  SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
748  SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
749  return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
750}
751
752static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
753  // Convert the fp value to integer in an FP register.
754  assert(Op.getValueType() == MVT::i32);
755  Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
756  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
757}
758
759static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
760  assert(Op.getOperand(0).getValueType() == MVT::i32);
761  SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
762  // Convert the int value to FP in an FP register.
763  return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
764}
765
766static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
767  SDValue Chain = Op.getOperand(0);
768  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
769  SDValue LHS = Op.getOperand(2);
770  SDValue RHS = Op.getOperand(3);
771  SDValue Dest = Op.getOperand(4);
772  unsigned Opc, SPCC = ~0U;
773
774  // If this is a br_cc of a "setcc", and if the setcc got lowered into
775  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
776  LookThroughSetCC(LHS, RHS, CC, SPCC);
777
778  // Get the condition flag.
779  SDValue CompareFlag;
780  if (LHS.getValueType() == MVT::i32) {
781    std::vector<MVT> VTs;
782    VTs.push_back(MVT::i32);
783    VTs.push_back(MVT::Flag);
784    SDValue Ops[2] = { LHS, RHS };
785    CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
786    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
787    Opc = SPISD::BRICC;
788  } else {
789    CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
790    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
791    Opc = SPISD::BRFCC;
792  }
793  return DAG.getNode(Opc, MVT::Other, Chain, Dest,
794                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
795}
796
797static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
798  SDValue LHS = Op.getOperand(0);
799  SDValue RHS = Op.getOperand(1);
800  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
801  SDValue TrueVal = Op.getOperand(2);
802  SDValue FalseVal = Op.getOperand(3);
803  unsigned Opc, SPCC = ~0U;
804
805  // If this is a select_cc of a "setcc", and if the setcc got lowered into
806  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
807  LookThroughSetCC(LHS, RHS, CC, SPCC);
808
809  SDValue CompareFlag;
810  if (LHS.getValueType() == MVT::i32) {
811    std::vector<MVT> VTs;
812    VTs.push_back(LHS.getValueType());   // subcc returns a value
813    VTs.push_back(MVT::Flag);
814    SDValue Ops[2] = { LHS, RHS };
815    CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
816    Opc = SPISD::SELECT_ICC;
817    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
818  } else {
819    CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
820    Opc = SPISD::SELECT_FCC;
821    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
822  }
823  return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
824                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
825}
826
827static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
828                              SparcTargetLowering &TLI) {
829  // vastart just stores the address of the VarArgsFrameIndex slot into the
830  // memory location argument.
831  DebugLoc dl = Op.getNode()->getDebugLoc();
832  SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32,
833                                 DAG.getRegister(SP::I6, MVT::i32),
834                                 DAG.getConstant(TLI.getVarArgsFrameOffset(),
835                                                 MVT::i32));
836  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
837  return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0);
838}
839
840static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
841  SDNode *Node = Op.getNode();
842  MVT VT = Node->getValueType(0);
843  SDValue InChain = Node->getOperand(0);
844  SDValue VAListPtr = Node->getOperand(1);
845  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
846  DebugLoc dl = Node->getDebugLoc();
847  SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0);
848  // Increment the pointer, VAList, to the next vaarg
849  SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
850                                  DAG.getConstant(VT.getSizeInBits()/8,
851                                                  MVT::i32));
852  // Store the incremented VAList to the legalized pointer
853  InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
854                         VAListPtr, SV, 0);
855  // Load the actual argument out of the pointer VAList, unless this is an
856  // f64 load.
857  if (VT != MVT::f64)
858    return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0);
859
860  // Otherwise, load it as i64, then do a bitconvert.
861  SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0);
862
863  // Bit-Convert the value to f64.
864  SDValue Ops[2] = {
865    DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V),
866    V.getValue(1)
867  };
868  return DAG.getMergeValues(Ops, 2, dl);
869}
870
871static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
872  SDValue Chain = Op.getOperand(0);  // Legalize the chain.
873  SDValue Size  = Op.getOperand(1);  // Legalize the size.
874
875  unsigned SPReg = SP::O6;
876  SDValue SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
877  SDValue NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);    // Value
878  Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP);      // Output chain
879
880  // The resultant pointer is actually 16 words from the bottom of the stack,
881  // to provide a register spill area.
882  SDValue NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
883                                 DAG.getConstant(96, MVT::i32));
884  SDValue Ops[2] = { NewVal, Chain };
885  return DAG.getMergeValues(Ops, 2);
886}
887
888
889SDValue SparcTargetLowering::
890LowerOperation(SDValue Op, SelectionDAG &DAG) {
891  switch (Op.getOpcode()) {
892  default: assert(0 && "Should not custom lower this!");
893  // Frame & Return address.  Currently unimplemented
894  case ISD::RETURNADDR: return SDValue();
895  case ISD::FRAMEADDR:  return SDValue();
896  case ISD::GlobalTLSAddress:
897    assert(0 && "TLS not implemented for Sparc.");
898  case ISD::GlobalAddress:      return LowerGLOBALADDRESS(Op, DAG);
899  case ISD::ConstantPool:       return LowerCONSTANTPOOL(Op, DAG);
900  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
901  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);
902  case ISD::BR_CC:              return LowerBR_CC(Op, DAG);
903  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
904  case ISD::VASTART:            return LowerVASTART(Op, DAG, *this);
905  case ISD::VAARG:              return LowerVAARG(Op, DAG);
906  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
907  case ISD::CALL:               return LowerCALL(Op, DAG);
908  case ISD::RET:                return LowerRET(Op, DAG);
909  }
910}
911
912MachineBasicBlock *
913SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
914                                                 MachineBasicBlock *BB) {
915  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
916  unsigned BROpcode;
917  unsigned CC;
918  // Figure out the conditional branch opcode to use for this select_cc.
919  switch (MI->getOpcode()) {
920  default: assert(0 && "Unknown SELECT_CC!");
921  case SP::SELECT_CC_Int_ICC:
922  case SP::SELECT_CC_FP_ICC:
923  case SP::SELECT_CC_DFP_ICC:
924    BROpcode = SP::BCOND;
925    break;
926  case SP::SELECT_CC_Int_FCC:
927  case SP::SELECT_CC_FP_FCC:
928  case SP::SELECT_CC_DFP_FCC:
929    BROpcode = SP::FBCOND;
930    break;
931  }
932
933  CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
934
935  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
936  // control-flow pattern.  The incoming instruction knows the destination vreg
937  // to set, the condition code register to branch on, the true/false values to
938  // select between, and a branch opcode to use.
939  const BasicBlock *LLVM_BB = BB->getBasicBlock();
940  MachineFunction::iterator It = BB;
941  ++It;
942
943  //  thisMBB:
944  //  ...
945  //   TrueVal = ...
946  //   [f]bCC copy1MBB
947  //   fallthrough --> copy0MBB
948  MachineBasicBlock *thisMBB = BB;
949  MachineFunction *F = BB->getParent();
950  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
951  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
952  BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
953  F->insert(It, copy0MBB);
954  F->insert(It, sinkMBB);
955  // Update machine-CFG edges by transferring all successors of the current
956  // block to the new block which will contain the Phi node for the select.
957  sinkMBB->transferSuccessors(BB);
958  // Next, add the true and fallthrough blocks as its successors.
959  BB->addSuccessor(copy0MBB);
960  BB->addSuccessor(sinkMBB);
961
962  //  copy0MBB:
963  //   %FalseValue = ...
964  //   # fallthrough to sinkMBB
965  BB = copy0MBB;
966
967  // Update machine-CFG edges
968  BB->addSuccessor(sinkMBB);
969
970  //  sinkMBB:
971  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
972  //  ...
973  BB = sinkMBB;
974  BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
975    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
976    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
977
978  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
979  return BB;
980}
981
982//===----------------------------------------------------------------------===//
983//                         Sparc Inline Assembly Support
984//===----------------------------------------------------------------------===//
985
986/// getConstraintType - Given a constraint letter, return the type of
987/// constraint it is for this target.
988SparcTargetLowering::ConstraintType
989SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
990  if (Constraint.size() == 1) {
991    switch (Constraint[0]) {
992    default:  break;
993    case 'r': return C_RegisterClass;
994    }
995  }
996
997  return TargetLowering::getConstraintType(Constraint);
998}
999
1000std::pair<unsigned, const TargetRegisterClass*>
1001SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1002                                                  MVT VT) const {
1003  if (Constraint.size() == 1) {
1004    switch (Constraint[0]) {
1005    case 'r':
1006      return std::make_pair(0U, SP::IntRegsRegisterClass);
1007    }
1008  }
1009
1010  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1011}
1012
1013std::vector<unsigned> SparcTargetLowering::
1014getRegClassForInlineAsmConstraint(const std::string &Constraint,
1015                                  MVT VT) const {
1016  if (Constraint.size() != 1)
1017    return std::vector<unsigned>();
1018
1019  switch (Constraint[0]) {
1020  default: break;
1021  case 'r':
1022    return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3,
1023                                 SP::L4, SP::L5, SP::L6, SP::L7,
1024                                 SP::I0, SP::I1, SP::I2, SP::I3,
1025                                 SP::I4, SP::I5,
1026                                 SP::O0, SP::O1, SP::O2, SP::O3,
1027                                 SP::O4, SP::O5, SP::O7, 0);
1028  }
1029
1030  return std::vector<unsigned>();
1031}
1032
1033bool
1034SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1035  // The Sparc target isn't yet aware of offsets.
1036  return false;
1037}
1038