SparcISelLowering.cpp revision 36b56886974eae4f9c5ebc96befd3e7bfe5de338
128c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar// 3fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar// The LLVM Compiler Infrastructure 4fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar// 5fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar// This file is distributed under the University of Illinois Open Source 6fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar// License. See LICENSE.TXT for details. 7fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar// 8fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar//===----------------------------------------------------------------------===// 9fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar// 1028c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar// This file implements the interfaces that Sparc uses to lower LLVM code into a 1128c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar// selection DAG. 12fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar// 1385f2ecc697a8ca6c8cf08093054cbbb9d2060ccfRafael Espindola//===----------------------------------------------------------------------===// 14fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar 151f6efa3996dd1929fbc129203ce5009b620e6969Michael J. Spencer#include "SparcISelLowering.h" 16fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar#include "MCTargetDesc/SparcMCExpr.h" 17fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar#include "SparcMachineFunctionInfo.h" 18684c593d05db0bd277268fc9d8c05bce138c745aChris Lattner#include "SparcRegisterInfo.h" 19f82f4490b130eca55b08d605456a4ceacccf288aDaniel Dunbar#include "SparcTargetMachine.h" 2032a006e606742b1c5401e49607e33717bb5441f0Rafael Espindola#include "SparcTargetObjectFile.h" 21fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar#include "llvm/CodeGen/CallingConvLower.h" 2285f2ecc697a8ca6c8cf08093054cbbb9d2060ccfRafael Espindola#include "llvm/CodeGen/MachineFrameInfo.h" 23fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar#include "llvm/CodeGen/MachineFunction.h" 2415d170709608e2f1efcada74c297c10c8c71fdcfDaniel Dunbar#include "llvm/CodeGen/MachineInstrBuilder.h" 2587392fde1f261fea161b48886fafbedddb18dcceDaniel Dunbar#include "llvm/CodeGen/MachineRegisterInfo.h" 264f3e7aa154577c86791908e73a9fec075fdea0baChris Lattner#include "llvm/CodeGen/SelectionDAG.h" 2785f2ecc697a8ca6c8cf08093054cbbb9d2060ccfRafael Espindola#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 28fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar#include "llvm/IR/DerivedTypes.h" 2928c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar#include "llvm/IR/Function.h" 309643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar#include "llvm/IR/Module.h" 3128c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar#include "llvm/Support/ErrorHandling.h" 32fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbarusing namespace llvm; 3328c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar 341aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar 351aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar//===----------------------------------------------------------------------===// 361aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar// Calling Convention Implementation 375d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner//===----------------------------------------------------------------------===// 385d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner 39fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbarstatic bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, 409643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar MVT &LocVT, CCValAssign::LocInfo &LocInfo, 41fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar ISD::ArgFlagsTy &ArgFlags, CCState &State) 4228c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar{ 439643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar assert (ArgFlags.isSRet()); 449643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 459643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Assign SRet argument. 469643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 47d076482ab7e672d1d65a43809695e8d0d3995203Rafael Espindola 0, 48d076482ab7e672d1d65a43809695e8d0d3995203Rafael Espindola LocVT, LocInfo)); 4985f2ecc697a8ca6c8cf08093054cbbb9d2060ccfRafael Espindola return true; 50fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar} 51159f527cb269002de85e671023b9231a2c8792e9Dan Gohman 529643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbarstatic bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, 53d076482ab7e672d1d65a43809695e8d0d3995203Rafael Espindola MVT &LocVT, CCValAssign::LocInfo &LocInfo, 54d076482ab7e672d1d65a43809695e8d0d3995203Rafael Espindola ISD::ArgFlagsTy &ArgFlags, CCState &State) 5585f2ecc697a8ca6c8cf08093054cbbb9d2060ccfRafael Espindola{ 56f230df9af4012f9510de664b6d62b128e26a5861Rafael Espindola static const uint16_t RegList[] = { 57fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 589643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar }; 599643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Try to get first reg. 60fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar if (unsigned Reg = State.AllocateReg(RegList, 6)) { 6128c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 62fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar } else { 639643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Assign whole thing in stack. 6487392fde1f261fea161b48886fafbedddb18dcceDaniel Dunbar State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 6587392fde1f261fea161b48886fafbedddb18dcceDaniel Dunbar State.AllocateStack(8,4), 6687392fde1f261fea161b48886fafbedddb18dcceDaniel Dunbar LocVT, LocInfo)); 678cb9a3b13f3226b7e741768b69d26ecd6b5231f1Chris Lattner return true; 6887392fde1f261fea161b48886fafbedddb18dcceDaniel Dunbar } 6987392fde1f261fea161b48886fafbedddb18dcceDaniel Dunbar 7087392fde1f261fea161b48886fafbedddb18dcceDaniel Dunbar // Try to get second reg. 719643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar if (unsigned Reg = State.AllocateReg(RegList, 6)) 729643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 739643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar else 74fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 75fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar State.AllocateStack(4,4), 7615d170709608e2f1efcada74c297c10c8c71fdcfDaniel Dunbar LocVT, LocInfo)); 77f82f4490b130eca55b08d605456a4ceacccf288aDaniel Dunbar return true; 78f82f4490b130eca55b08d605456a4ceacccf288aDaniel Dunbar} 79f82f4490b130eca55b08d605456a4ceacccf288aDaniel Dunbar 80fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar// Allocate a full-sized argument for the 64-bit ABI. 81d076482ab7e672d1d65a43809695e8d0d3995203Rafael Espindolastatic bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, 82d076482ab7e672d1d65a43809695e8d0d3995203Rafael Espindola MVT &LocVT, CCValAssign::LocInfo &LocInfo, 83d076482ab7e672d1d65a43809695e8d0d3995203Rafael Espindola ISD::ArgFlagsTy &ArgFlags, CCState &State) { 8485f2ecc697a8ca6c8cf08093054cbbb9d2060ccfRafael Espindola assert((LocVT == MVT::f32 || LocVT == MVT::f128 85d076482ab7e672d1d65a43809695e8d0d3995203Rafael Espindola || LocVT.getSizeInBits() == 64) && 86fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar "Can't handle non-64 bits locations"); 8715d170709608e2f1efcada74c297c10c8c71fdcfDaniel Dunbar 881aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar // Stack space is allocated for all arguments starting from [%fp+BIAS+128]. 8915d170709608e2f1efcada74c297c10c8c71fdcfDaniel Dunbar unsigned size = (LocVT == MVT::f128) ? 16 : 8; 9015d170709608e2f1efcada74c297c10c8c71fdcfDaniel Dunbar unsigned alignment = (LocVT == MVT::f128) ? 16 : 8; 91f82f4490b130eca55b08d605456a4ceacccf288aDaniel Dunbar unsigned Offset = State.AllocateStack(size, alignment); 9215d170709608e2f1efcada74c297c10c8c71fdcfDaniel Dunbar unsigned Reg = 0; 9333a38a1b5a35acd15c867193bc2175f3d4e7b83dRafael Espindola 9415d170709608e2f1efcada74c297c10c8c71fdcfDaniel Dunbar if (LocVT == MVT::i64 && Offset < 6*8) 959643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Promote integers to %i0-%i5. 969643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar Reg = SP::I0 + Offset/8; 9728c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar else if (LocVT == MVT::f64 && Offset < 16*8) 98fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). 99a0e36d55c495b3325805c659ac365b5faea84e34Daniel Dunbar Reg = SP::D0 + Offset/8; 1008cb9a3b13f3226b7e741768b69d26ecd6b5231f1Chris Lattner else if (LocVT == MVT::f32 && Offset < 16*8) 1018cb9a3b13f3226b7e741768b69d26ecd6b5231f1Chris Lattner // Promote floats to %f1, %f3, ... 1028cb9a3b13f3226b7e741768b69d26ecd6b5231f1Chris Lattner Reg = SP::F1 + Offset/4; 1038cb9a3b13f3226b7e741768b69d26ecd6b5231f1Chris Lattner else if (LocVT == MVT::f128 && Offset < 16*8) 104fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar // Promote long doubles to %q0-%q28. (Which LLVM calls Q0-Q7). 10528c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar Reg = SP::Q0 + Offset/16; 10628c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar 107fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar // Promote to register when possible, otherwise use the stack slot. 108fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar if (Reg) { 109159f527cb269002de85e671023b9231a2c8792e9Dan Gohman State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 11028c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar return true; 1119643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar } 1129643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 1139643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // This argument goes on the stack in an 8-byte slot. 1149643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to 1159643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // the right-aligned float. The first 4 bytes of the stack slot are undefined. 1169643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar if (LocVT == MVT::f32) 1179643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar Offset += 4; 1189643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 1199643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1209643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar return true; 1219643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar} 122fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar 123fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar// Allocate a half-sized argument for the 64-bit ABI. 1249643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar// 1259643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar// This is used when passing { float, int } structs by value in registers. 1269643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbarstatic bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, 1279643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar MVT &LocVT, CCValAssign::LocInfo &LocInfo, 128fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar ISD::ArgFlagsTy &ArgFlags, CCState &State) { 12928c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations"); 130fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar unsigned Offset = State.AllocateStack(4, 4); 131fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar 13228c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar if (LocVT == MVT::f32 && Offset < 16*8) { 1331aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar // Promote floats to %f0-%f31. 1341aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, 1351aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar LocVT, LocInfo)); 1361aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar return true; 1371aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar } 13828c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar 1394e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar if (LocVT == MVT::i32 && Offset < 6*8) { 1404e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar // Promote integers to %i0-%i5, using half the register. 1414e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar unsigned Reg = SP::I0 + Offset/8; 1424e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar LocVT = MVT::i64; 1434e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar LocInfo = CCValAssign::AExt; 1444e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar 1454e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar // Set the Custom bit if this i32 goes in the high bits of a register. 1464e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar if (Offset % 8 == 0) 1474e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, 1484e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar LocVT, LocInfo)); 1494e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar else 150a0a2f8734cdfc19d44201b791a969bcdda96bb70Rafael Espindola State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1514e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar return true; 1524e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar } 153b4d1721eff7b43577e5f2e53f885973fb6c43683Rafael Espindola 154a264f72d3fb9dec1427480fcf17ef3c746ea723aRafael Espindola State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 15518c1021ec108722506125926087b1e5fcfb28046Rafael Espindola return true; 1560cf15d61b7e3bf53f5a99f58ada37b93bc039559Rafael Espindola} 1576135a96792ca05f6366e5dbaee6208e84589c47fChris Lattner 1582c4d5125c708bb35140fc2a40b02beb1add101dbJim Grosbach#include "SparcGenCallingConv.inc" 1592c4d5125c708bb35140fc2a40b02beb1add101dbJim Grosbach 1602c4d5125c708bb35140fc2a40b02beb1add101dbJim Grosbach// The calling conventions in SparcCallingConv.td are described in terms of the 1612c4d5125c708bb35140fc2a40b02beb1add101dbJim Grosbach// callee's register window. This function translates registers to the 1622c4d5125c708bb35140fc2a40b02beb1add101dbJim Grosbach// corresponding caller window %o register. 1632c4d5125c708bb35140fc2a40b02beb1add101dbJim Grosbachstatic unsigned toCallerWindow(unsigned Reg) { 1642c4d5125c708bb35140fc2a40b02beb1add101dbJim Grosbach assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum"); 165c67b1a3a76ea6ff642d30610cf63595ccb661e6bBob Wilson if (Reg >= SP::I0 && Reg <= SP::I7) 1661e61e69d401045c54b15815f15a0fdb3ca56a9b5Chris Lattner return Reg - SP::I0 + SP::O0; 1671e61e69d401045c54b15815f15a0fdb3ca56a9b5Chris Lattner return Reg; 1681e61e69d401045c54b15815f15a0fdb3ca56a9b5Chris Lattner} 1694e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar 1704e815f8a8cae6c846cdca52420046cab902865deDaniel DunbarSDValue 1714e815f8a8cae6c846cdca52420046cab902865deDaniel DunbarSparcTargetLowering::LowerReturn(SDValue Chain, 1724e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar CallingConv::ID CallConv, bool IsVarArg, 1739643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar const SmallVectorImpl<ISD::OutputArg> &Outs, 174fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar const SmallVectorImpl<SDValue> &OutVals, 1754e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar SDLoc DL, SelectionDAG &DAG) const { 1764e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar if (Subtarget->is64Bit()) 1774e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 1784e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 1794e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar} 180fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar 1819643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel DunbarSDValue 1829643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel DunbarSparcTargetLowering::LowerReturn_32(SDValue Chain, 1839643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CallingConv::ID CallConv, bool IsVarArg, 1849643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar const SmallVectorImpl<ISD::OutputArg> &Outs, 1854e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar const SmallVectorImpl<SDValue> &OutVals, 1864e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar SDLoc DL, SelectionDAG &DAG) const { 1874e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar MachineFunction &MF = DAG.getMachineFunction(); 1884e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar 1894e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar // CCValAssign - represent the assignment of the return value to locations. 1904e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar SmallVector<CCValAssign, 16> RVLocs; 1914e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar 1924e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar // CCState - Info about the registers and stack slot. 193c67b1a3a76ea6ff642d30610cf63595ccb661e6bBob Wilson CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 1949643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar DAG.getTarget(), RVLocs, *DAG.getContext()); 1959643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 1969643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Analyze return values. 1979643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 1989643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 1999643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SDValue Flag; 2004e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar SmallVector<SDValue, 4> RetOps(1, Chain); 2014e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar // Make room for the return address offset. 2024e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar RetOps.push_back(SDValue()); 2034e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar 2044e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar // Copy the result values into the output registers. 2054e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar for (unsigned i = 0; i != RVLocs.size(); ++i) { 2064e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar CCValAssign &VA = RVLocs[i]; 2074e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar assert(VA.isRegLoc() && "Can only return in registers!"); 2084e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar 2094e815f8a8cae6c846cdca52420046cab902865deDaniel Dunbar Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), 2109643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar OutVals[i], Flag); 2119643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 2129643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Guarantee that all emitted copies are stuck together with flags. 2139643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar Flag = Chain.getValue(1); 214fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 21528c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar } 216fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar 217fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar unsigned RetAddrOffset = 8; // Call Inst + Delay Slot 21828c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar // If the function returns a struct, copy the SRetReturnReg to I0 21928c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar if (MF.getFunction()->hasStructRetAttr()) { 220fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 221fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar unsigned Reg = SFI->getSRetReturnReg(); 2221aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar if (!Reg) 2231aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar llvm_unreachable("sret virtual register not created in the entry block"); 2241aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 2251aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag); 226fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar Flag = Chain.getValue(1); 227fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy())); 228fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar RetAddrOffset = 12; // CallInst + Delay Slot + Unimp 229fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar } 2309643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 231fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar RetOps[0] = Chain; // Update chain. 2329643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32); 23328c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar 2349643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Add the flag if we have it. 2359643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar if (Flag.getNode()) 2369643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar RetOps.push_back(Flag); 2379643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 2389643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 2399643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar &RetOps[0], RetOps.size()); 2409643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar} 2419643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 2429643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar// Lower return values for the 64-bit ABI. 2439643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar// Return values are passed the exactly the same way as function arguments. 2449643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel DunbarSDValue 2459643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel DunbarSparcTargetLowering::LowerReturn_64(SDValue Chain, 2469643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CallingConv::ID CallConv, bool IsVarArg, 2479643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar const SmallVectorImpl<ISD::OutputArg> &Outs, 2489643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar const SmallVectorImpl<SDValue> &OutVals, 249fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar SDLoc DL, SelectionDAG &DAG) const { 2509643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // CCValAssign - represent the assignment of the return value to locations. 2519643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SmallVector<CCValAssign, 16> RVLocs; 2529643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 2539643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // CCState - Info about the registers and stack slot. 2549643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 2559643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar DAG.getTarget(), RVLocs, *DAG.getContext()); 2569643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 257fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar // Analyze return values. 2589643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CCInfo.AnalyzeReturn(Outs, RetCC_Sparc64); 259fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar 260fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar SDValue Flag; 2619643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SmallVector<SDValue, 4> RetOps(1, Chain); 2629643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 263fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar // The second operand on the return instruction is the return address offset. 2649643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // The return address is always %i7+8 with the 64-bit ABI. 2659643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar RetOps.push_back(DAG.getConstant(8, MVT::i32)); 2669643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 2679643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Copy the result values into the output registers. 268fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar for (unsigned i = 0; i != RVLocs.size(); ++i) { 26928c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar CCValAssign &VA = RVLocs[i]; 270fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar assert(VA.isRegLoc() && "Can only return in registers!"); 271fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar SDValue OutVal = OutVals[i]; 27228c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar 27328c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar // Integer return values must be sign or zero extended by the callee. 274fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar switch (VA.getLocInfo()) { 275fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar case CCValAssign::Full: break; 2761aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar case CCValAssign::SExt: 2771aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); 278036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman break; 2791aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar case CCValAssign::ZExt: 280036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); 281036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman break; 282036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman case CCValAssign::AExt: 283036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); 2841aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar break; 2851aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar default: 286036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman llvm_unreachable("Unknown loc info!"); 287036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman } 288036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman 289036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman // The custom bit on an i32 return value indicates that it should be passed 290036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman // in the high bits of the register. 2911aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 2921aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, 2931aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar DAG.getConstant(32, MVT::i32)); 294036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman 295036c130e90eb5c93b0dc0a70ad07b9343623c2a8Dan Gohman // The next value may go in the low bits of the same register. 2961aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar // Handle both at once. 2971aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { 298fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); 299fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); 300fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar // Skip the next value, it's already done. 301fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar ++i; 3029643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar } 303fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar } 3049643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 30528c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); 3069643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3079643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Guarantee that all emitted copies are stuck together with flags. 3089643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar Flag = Chain.getValue(1); 3099643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 3109643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar } 3119643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3129643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar RetOps[0] = Chain; // Update chain. 3139643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3149643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Add the flag if we have it. 3159643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar if (Flag.getNode()) 3169643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar RetOps.push_back(Flag); 3179643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3189643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 3199643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar &RetOps[0], RetOps.size()); 3209643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar} 3219643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3229643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel DunbarSDValue SparcTargetLowering:: 3239643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel DunbarLowerFormalArguments(SDValue Chain, 3249643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CallingConv::ID CallConv, 3259643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar bool IsVarArg, 3269643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar const SmallVectorImpl<ISD::InputArg> &Ins, 3279643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SDLoc DL, 3289643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SelectionDAG &DAG, 3299643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SmallVectorImpl<SDValue> &InVals) const { 3309643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar if (Subtarget->is64Bit()) 3319643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins, 3329643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar DL, DAG, InVals); 3339643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins, 3349643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar DL, DAG, InVals); 3359643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar} 3369643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3379643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are 3389643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar/// passed in either one or two GPRs, including FP values. TODO: we should 3399643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar/// pass FP values in FP registers for fastcc functions. 340fc6877aec9826fa830204d49eba7fac7412b841eDaniel DunbarSDValue SparcTargetLowering:: 3419643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel DunbarLowerFormalArguments_32(SDValue Chain, 3429643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CallingConv::ID CallConv, 3439643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar bool isVarArg, 3449643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar const SmallVectorImpl<ISD::InputArg> &Ins, 3459643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SDLoc dl, 3469643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SelectionDAG &DAG, 3479643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SmallVectorImpl<SDValue> &InVals) const { 3489643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar MachineFunction &MF = DAG.getMachineFunction(); 3499643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3509643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 3519643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3529643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Assign locations to all of the incoming arguments. 3539643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SmallVector<CCValAssign, 16> ArgLocs; 3549643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 3559643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar getTargetMachine(), ArgLocs, *DAG.getContext()); 3569643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 3579643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3589643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar const unsigned StackOffset = 92; 3599643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3609643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 3619643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CCValAssign &VA = ArgLocs[i]; 3629643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3639643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar if (i == 0 && Ins[i].Flags.isSRet()) { 3649643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar // Get SRet from [%fp+64]. 3659643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); 3669643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 3679643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 3689643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar MachinePointerInfo(), 3699643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar false, false, false, 0); 3709643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar InVals.push_back(Arg); 3719643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar continue; 3729643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar } 3739643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3749643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar if (VA.isRegLoc()) { 3759643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar if (VA.needsCustom()) { 3769643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar assert(VA.getLocVT() == MVT::f64); 3779643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 3789643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 3799643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 3809643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3819643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar assert(i+1 < e); 3829643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CCValAssign &NextVA = ArgLocs[++i]; 3839643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar 3849643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SDValue LoVal; 3859643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar if (NextVA.isMemLoc()) { 3869643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar int FrameIdx = MF.getFrameInfo()-> 3879643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); 3889643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 389fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 3909643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar MachinePointerInfo(), 391fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar false, false, false, 0); 392fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar } else { 3931aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), 3949643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar &SP::IntRegsRegClass); 3951aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); 3961aa14aac4198bca0f44e4adad42bf6238cbf9757Daniel Dunbar } 3979643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar SDValue WholeValue = 3989643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 3999643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 400fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar InVals.push_back(WholeValue); 4019643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar continue; 4029643ac55142d40da404caa8e5fedfef2cd7b4afcDaniel Dunbar } 403fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 40428c251b54b0b311749f07babe0f6909e71e877bcDaniel Dunbar MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 405fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 406fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar if (VA.getLocVT() == MVT::f32) 4075d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 4085d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner else if (VA.getLocVT() != MVT::i32) { 4095d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 4105d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner DAG.getValueType(VA.getLocVT())); 4115d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); 4125d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner } 413df9c4380ee7e60c1de5cae32685b113170b1faa2Chris Lattner InVals.push_back(Arg); 4145d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner continue; 4155d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner } 416e3e7a369f20af66a96830d8bfe52668c9e2e1fa1Chris Lattner 4175d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner assert(VA.isMemLoc()); 418a0e36d55c495b3325805c659ac365b5faea84e34Daniel Dunbar 4195d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner unsigned Offset = VA.getLocMemOffset()+StackOffset; 420f82f4490b130eca55b08d605456a4ceacccf288aDaniel Dunbar 421a0e36d55c495b3325805c659ac365b5faea84e34Daniel Dunbar if (VA.needsCustom()) { 4227597212abced110723f2fee985a7d60557c092ecEvan Cheng assert(VA.getValVT() == MVT::f64); 4235d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner // If it is double-word aligned, just load. 4245d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner if (Offset % 8 == 0) { 4255d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner int FI = MF.getFrameInfo()->CreateFixedObject(8, 4265d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner Offset, 4275d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner true); 4285d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 4295d917a8952c09a345180ec36f0df4ee5dd5eddeaChris Lattner SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 430fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar MachinePointerInfo(), 431fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar false,false, false, 0); 432fc6877aec9826fa830204d49eba7fac7412b841eDaniel Dunbar InVals.push_back(Load); 433 continue; 434 } 435 436 int FI = MF.getFrameInfo()->CreateFixedObject(4, 437 Offset, 438 true); 439 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 440 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 441 MachinePointerInfo(), 442 false, false, false, 0); 443 int FI2 = MF.getFrameInfo()->CreateFixedObject(4, 444 Offset+4, 445 true); 446 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy()); 447 448 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, 449 MachinePointerInfo(), 450 false, false, false, 0); 451 452 SDValue WholeValue = 453 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 454 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 455 InVals.push_back(WholeValue); 456 continue; 457 } 458 459 int FI = MF.getFrameInfo()->CreateFixedObject(4, 460 Offset, 461 true); 462 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 463 SDValue Load ; 464 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { 465 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 466 MachinePointerInfo(), 467 false, false, false, 0); 468 } else { 469 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 470 // Sparc is big endian, so add an offset based on the ObjectVT. 471 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); 472 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 473 DAG.getConstant(Offset, MVT::i32)); 474 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, 475 MachinePointerInfo(), 476 VA.getValVT(), false, false,0); 477 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); 478 } 479 InVals.push_back(Load); 480 } 481 482 if (MF.getFunction()->hasStructRetAttr()) { 483 // Copy the SRet Argument to SRetReturnReg. 484 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 485 unsigned Reg = SFI->getSRetReturnReg(); 486 if (!Reg) { 487 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); 488 SFI->setSRetReturnReg(Reg); 489 } 490 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 491 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 492 } 493 494 // Store remaining ArgRegs to the stack if this is a varargs function. 495 if (isVarArg) { 496 static const uint16_t ArgRegs[] = { 497 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 498 }; 499 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); 500 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; 501 unsigned ArgOffset = CCInfo.getNextStackOffset(); 502 if (NumAllocated == 6) 503 ArgOffset += StackOffset; 504 else { 505 assert(!ArgOffset); 506 ArgOffset = 68+4*NumAllocated; 507 } 508 509 // Remember the vararg offset for the va_start implementation. 510 FuncInfo->setVarArgsFrameOffset(ArgOffset); 511 512 std::vector<SDValue> OutChains; 513 514 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 515 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 516 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 517 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 518 519 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 520 true); 521 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 522 523 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, 524 MachinePointerInfo(), 525 false, false, 0)); 526 ArgOffset += 4; 527 } 528 529 if (!OutChains.empty()) { 530 OutChains.push_back(Chain); 531 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 532 &OutChains[0], OutChains.size()); 533 } 534 } 535 536 return Chain; 537} 538 539// Lower formal arguments for the 64 bit ABI. 540SDValue SparcTargetLowering:: 541LowerFormalArguments_64(SDValue Chain, 542 CallingConv::ID CallConv, 543 bool IsVarArg, 544 const SmallVectorImpl<ISD::InputArg> &Ins, 545 SDLoc DL, 546 SelectionDAG &DAG, 547 SmallVectorImpl<SDValue> &InVals) const { 548 MachineFunction &MF = DAG.getMachineFunction(); 549 550 // Analyze arguments according to CC_Sparc64. 551 SmallVector<CCValAssign, 16> ArgLocs; 552 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 553 getTargetMachine(), ArgLocs, *DAG.getContext()); 554 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64); 555 556 // The argument array begins at %fp+BIAS+128, after the register save area. 557 const unsigned ArgArea = 128; 558 559 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 560 CCValAssign &VA = ArgLocs[i]; 561 if (VA.isRegLoc()) { 562 // This argument is passed in a register. 563 // All integer register arguments are promoted by the caller to i64. 564 565 // Create a virtual register for the promoted live-in value. 566 unsigned VReg = MF.addLiveIn(VA.getLocReg(), 567 getRegClassFor(VA.getLocVT())); 568 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); 569 570 // Get the high bits for i32 struct elements. 571 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 572 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, 573 DAG.getConstant(32, MVT::i32)); 574 575 // The caller promoted the argument, so insert an Assert?ext SDNode so we 576 // won't promote the value again in this function. 577 switch (VA.getLocInfo()) { 578 case CCValAssign::SExt: 579 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, 580 DAG.getValueType(VA.getValVT())); 581 break; 582 case CCValAssign::ZExt: 583 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, 584 DAG.getValueType(VA.getValVT())); 585 break; 586 default: 587 break; 588 } 589 590 // Truncate the register down to the argument type. 591 if (VA.isExtInLoc()) 592 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); 593 594 InVals.push_back(Arg); 595 continue; 596 } 597 598 // The registers are exhausted. This argument was passed on the stack. 599 assert(VA.isMemLoc()); 600 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the 601 // beginning of the arguments area at %fp+BIAS+128. 602 unsigned Offset = VA.getLocMemOffset() + ArgArea; 603 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; 604 // Adjust offset for extended arguments, SPARC is big-endian. 605 // The caller will have written the full slot with extended bytes, but we 606 // prefer our own extending loads. 607 if (VA.isExtInLoc()) 608 Offset += 8 - ValSize; 609 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true); 610 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, 611 DAG.getFrameIndex(FI, getPointerTy()), 612 MachinePointerInfo::getFixedStack(FI), 613 false, false, false, 0)); 614 } 615 616 if (!IsVarArg) 617 return Chain; 618 619 // This function takes variable arguments, some of which may have been passed 620 // in registers %i0-%i5. Variable floating point arguments are never passed 621 // in floating point registers. They go on %i0-%i5 or on the stack like 622 // integer arguments. 623 // 624 // The va_start intrinsic needs to know the offset to the first variable 625 // argument. 626 unsigned ArgOffset = CCInfo.getNextStackOffset(); 627 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 628 // Skip the 128 bytes of register save area. 629 FuncInfo->setVarArgsFrameOffset(ArgOffset + ArgArea + 630 Subtarget->getStackPointerBias()); 631 632 // Save the variable arguments that were passed in registers. 633 // The caller is required to reserve stack space for 6 arguments regardless 634 // of how many arguments were actually passed. 635 SmallVector<SDValue, 8> OutChains; 636 for (; ArgOffset < 6*8; ArgOffset += 8) { 637 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); 638 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64); 639 int FI = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset + ArgArea, true); 640 OutChains.push_back(DAG.getStore(Chain, DL, VArg, 641 DAG.getFrameIndex(FI, getPointerTy()), 642 MachinePointerInfo::getFixedStack(FI), 643 false, false, 0)); 644 } 645 646 if (!OutChains.empty()) 647 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 648 &OutChains[0], OutChains.size()); 649 650 return Chain; 651} 652 653SDValue 654SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 655 SmallVectorImpl<SDValue> &InVals) const { 656 if (Subtarget->is64Bit()) 657 return LowerCall_64(CLI, InVals); 658 return LowerCall_32(CLI, InVals); 659} 660 661static bool hasReturnsTwiceAttr(SelectionDAG &DAG, SDValue Callee, 662 ImmutableCallSite *CS) { 663 if (CS) 664 return CS->hasFnAttr(Attribute::ReturnsTwice); 665 666 const Function *CalleeFn = 0; 667 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 668 CalleeFn = dyn_cast<Function>(G->getGlobal()); 669 } else if (ExternalSymbolSDNode *E = 670 dyn_cast<ExternalSymbolSDNode>(Callee)) { 671 const Function *Fn = DAG.getMachineFunction().getFunction(); 672 const Module *M = Fn->getParent(); 673 const char *CalleeName = E->getSymbol(); 674 CalleeFn = M->getFunction(CalleeName); 675 } 676 677 if (!CalleeFn) 678 return false; 679 return CalleeFn->hasFnAttribute(Attribute::ReturnsTwice); 680} 681 682// Lower a call for the 32-bit ABI. 683SDValue 684SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 685 SmallVectorImpl<SDValue> &InVals) const { 686 SelectionDAG &DAG = CLI.DAG; 687 SDLoc &dl = CLI.DL; 688 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs; 689 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals; 690 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins; 691 SDValue Chain = CLI.Chain; 692 SDValue Callee = CLI.Callee; 693 bool &isTailCall = CLI.IsTailCall; 694 CallingConv::ID CallConv = CLI.CallConv; 695 bool isVarArg = CLI.IsVarArg; 696 697 // Sparc target does not yet support tail call optimization. 698 isTailCall = false; 699 700 // Analyze operands of the call, assigning locations to each operand. 701 SmallVector<CCValAssign, 16> ArgLocs; 702 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 703 DAG.getTarget(), ArgLocs, *DAG.getContext()); 704 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 705 706 // Get the size of the outgoing arguments stack space requirement. 707 unsigned ArgsSize = CCInfo.getNextStackOffset(); 708 709 // Keep stack frames 8-byte aligned. 710 ArgsSize = (ArgsSize+7) & ~7; 711 712 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 713 714 // Create local copies for byval args. 715 SmallVector<SDValue, 8> ByValArgs; 716 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 717 ISD::ArgFlagsTy Flags = Outs[i].Flags; 718 if (!Flags.isByVal()) 719 continue; 720 721 SDValue Arg = OutVals[i]; 722 unsigned Size = Flags.getByValSize(); 723 unsigned Align = Flags.getByValAlign(); 724 725 int FI = MFI->CreateStackObject(Size, Align, false); 726 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 727 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 728 729 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, 730 false, // isVolatile, 731 (Size <= 32), // AlwaysInline if size <= 32 732 MachinePointerInfo(), MachinePointerInfo()); 733 ByValArgs.push_back(FIPtr); 734 } 735 736 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true), 737 dl); 738 739 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 740 SmallVector<SDValue, 8> MemOpChains; 741 742 const unsigned StackOffset = 92; 743 bool hasStructRetAttr = false; 744 // Walk the register/memloc assignments, inserting copies/loads. 745 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size(); 746 i != e; 747 ++i, ++realArgIdx) { 748 CCValAssign &VA = ArgLocs[i]; 749 SDValue Arg = OutVals[realArgIdx]; 750 751 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 752 753 // Use local copy if it is a byval arg. 754 if (Flags.isByVal()) 755 Arg = ByValArgs[byvalArgIdx++]; 756 757 // Promote the value if needed. 758 switch (VA.getLocInfo()) { 759 default: llvm_unreachable("Unknown loc info!"); 760 case CCValAssign::Full: break; 761 case CCValAssign::SExt: 762 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 763 break; 764 case CCValAssign::ZExt: 765 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 766 break; 767 case CCValAssign::AExt: 768 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 769 break; 770 case CCValAssign::BCvt: 771 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 772 break; 773 } 774 775 if (Flags.isSRet()) { 776 assert(VA.needsCustom()); 777 // store SRet argument in %sp+64 778 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 779 SDValue PtrOff = DAG.getIntPtrConstant(64); 780 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 781 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 782 MachinePointerInfo(), 783 false, false, 0)); 784 hasStructRetAttr = true; 785 continue; 786 } 787 788 if (VA.needsCustom()) { 789 assert(VA.getLocVT() == MVT::f64); 790 791 if (VA.isMemLoc()) { 792 unsigned Offset = VA.getLocMemOffset() + StackOffset; 793 // if it is double-word aligned, just store. 794 if (Offset % 8 == 0) { 795 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 796 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 797 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 798 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 799 MachinePointerInfo(), 800 false, false, 0)); 801 continue; 802 } 803 } 804 805 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 806 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 807 Arg, StackPtr, MachinePointerInfo(), 808 false, false, 0); 809 // Sparc is big-endian, so the high part comes first. 810 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 811 MachinePointerInfo(), false, false, false, 0); 812 // Increment the pointer to the other half. 813 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 814 DAG.getIntPtrConstant(4)); 815 // Load the low part. 816 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 817 MachinePointerInfo(), false, false, false, 0); 818 819 if (VA.isRegLoc()) { 820 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); 821 assert(i+1 != e); 822 CCValAssign &NextVA = ArgLocs[++i]; 823 if (NextVA.isRegLoc()) { 824 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 825 } else { 826 // Store the low part in stack. 827 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; 828 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 829 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 830 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 831 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 832 MachinePointerInfo(), 833 false, false, 0)); 834 } 835 } else { 836 unsigned Offset = VA.getLocMemOffset() + StackOffset; 837 // Store the high part. 838 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 839 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 840 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 841 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, 842 MachinePointerInfo(), 843 false, false, 0)); 844 // Store the low part. 845 PtrOff = DAG.getIntPtrConstant(Offset+4); 846 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 847 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 848 MachinePointerInfo(), 849 false, false, 0)); 850 } 851 continue; 852 } 853 854 // Arguments that can be passed on register must be kept at 855 // RegsToPass vector 856 if (VA.isRegLoc()) { 857 if (VA.getLocVT() != MVT::f32) { 858 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 859 continue; 860 } 861 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 862 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 863 continue; 864 } 865 866 assert(VA.isMemLoc()); 867 868 // Create a store off the stack pointer for this argument. 869 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 870 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); 871 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 872 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 873 MachinePointerInfo(), 874 false, false, 0)); 875 } 876 877 878 // Emit all stores, make sure the occur before any copies into physregs. 879 if (!MemOpChains.empty()) 880 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 881 &MemOpChains[0], MemOpChains.size()); 882 883 // Build a sequence of copy-to-reg nodes chained together with token 884 // chain and flag operands which copy the outgoing args into registers. 885 // The InFlag in necessary since all emitted instructions must be 886 // stuck together. 887 SDValue InFlag; 888 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 889 unsigned Reg = toCallerWindow(RegsToPass[i].first); 890 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 891 InFlag = Chain.getValue(1); 892 } 893 894 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0; 895 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); 896 897 // If the callee is a GlobalAddress node (quite common, every direct call is) 898 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 899 // Likewise ExternalSymbol -> TargetExternalSymbol. 900 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_) 901 ? SparcMCExpr::VK_Sparc_WPLT30 : 0); 902 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 903 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32, 0, TF); 904 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 905 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32, TF); 906 907 // Returns a chain & a flag for retval copy to use 908 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 909 SmallVector<SDValue, 8> Ops; 910 Ops.push_back(Chain); 911 Ops.push_back(Callee); 912 if (hasStructRetAttr) 913 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); 914 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 915 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first), 916 RegsToPass[i].second.getValueType())); 917 918 // Add a register mask operand representing the call-preserved registers. 919 const SparcRegisterInfo *TRI = 920 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo(); 921 const uint32_t *Mask = ((hasReturnsTwice) 922 ? TRI->getRTCallPreservedMask(CallConv) 923 : TRI->getCallPreservedMask(CallConv)); 924 assert(Mask && "Missing call preserved mask for calling convention"); 925 Ops.push_back(DAG.getRegisterMask(Mask)); 926 927 if (InFlag.getNode()) 928 Ops.push_back(InFlag); 929 930 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 931 InFlag = Chain.getValue(1); 932 933 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 934 DAG.getIntPtrConstant(0, true), InFlag, dl); 935 InFlag = Chain.getValue(1); 936 937 // Assign locations to each value returned by this call. 938 SmallVector<CCValAssign, 16> RVLocs; 939 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), 940 DAG.getTarget(), RVLocs, *DAG.getContext()); 941 942 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 943 944 // Copy all of the result registers out of their specified physreg. 945 for (unsigned i = 0; i != RVLocs.size(); ++i) { 946 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), 947 RVLocs[i].getValVT(), InFlag).getValue(1); 948 InFlag = Chain.getValue(2); 949 InVals.push_back(Chain.getValue(0)); 950 } 951 952 return Chain; 953} 954 955// This functions returns true if CalleeName is a ABI function that returns 956// a long double (fp128). 957static bool isFP128ABICall(const char *CalleeName) 958{ 959 static const char *const ABICalls[] = 960 { "_Q_add", "_Q_sub", "_Q_mul", "_Q_div", 961 "_Q_sqrt", "_Q_neg", 962 "_Q_itoq", "_Q_stoq", "_Q_dtoq", "_Q_utoq", 963 "_Q_lltoq", "_Q_ulltoq", 964 0 965 }; 966 for (const char * const *I = ABICalls; *I != 0; ++I) 967 if (strcmp(CalleeName, *I) == 0) 968 return true; 969 return false; 970} 971 972unsigned 973SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const 974{ 975 const Function *CalleeFn = 0; 976 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 977 CalleeFn = dyn_cast<Function>(G->getGlobal()); 978 } else if (ExternalSymbolSDNode *E = 979 dyn_cast<ExternalSymbolSDNode>(Callee)) { 980 const Function *Fn = DAG.getMachineFunction().getFunction(); 981 const Module *M = Fn->getParent(); 982 const char *CalleeName = E->getSymbol(); 983 CalleeFn = M->getFunction(CalleeName); 984 if (!CalleeFn && isFP128ABICall(CalleeName)) 985 return 16; // Return sizeof(fp128) 986 } 987 988 if (!CalleeFn) 989 return 0; 990 991 assert(CalleeFn->hasStructRetAttr() && 992 "Callee does not have the StructRet attribute."); 993 994 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType()); 995 Type *ElementTy = Ty->getElementType(); 996 return getDataLayout()->getTypeAllocSize(ElementTy); 997} 998 999 1000// Fixup floating point arguments in the ... part of a varargs call. 1001// 1002// The SPARC v9 ABI requires that floating point arguments are treated the same 1003// as integers when calling a varargs function. This does not apply to the 1004// fixed arguments that are part of the function's prototype. 1005// 1006// This function post-processes a CCValAssign array created by 1007// AnalyzeCallOperands(). 1008static void fixupVariableFloatArgs(SmallVectorImpl<CCValAssign> &ArgLocs, 1009 ArrayRef<ISD::OutputArg> Outs) { 1010 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1011 const CCValAssign &VA = ArgLocs[i]; 1012 MVT ValTy = VA.getLocVT(); 1013 // FIXME: What about f32 arguments? C promotes them to f64 when calling 1014 // varargs functions. 1015 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) 1016 continue; 1017 // The fixed arguments to a varargs function still go in FP registers. 1018 if (Outs[VA.getValNo()].IsFixed) 1019 continue; 1020 1021 // This floating point argument should be reassigned. 1022 CCValAssign NewVA; 1023 1024 // Determine the offset into the argument array. 1025 unsigned firstReg = (ValTy == MVT::f64) ? SP::D0 : SP::Q0; 1026 unsigned argSize = (ValTy == MVT::f64) ? 8 : 16; 1027 unsigned Offset = argSize * (VA.getLocReg() - firstReg); 1028 assert(Offset < 16*8 && "Offset out of range, bad register enum?"); 1029 1030 if (Offset < 6*8) { 1031 // This argument should go in %i0-%i5. 1032 unsigned IReg = SP::I0 + Offset/8; 1033 if (ValTy == MVT::f64) 1034 // Full register, just bitconvert into i64. 1035 NewVA = CCValAssign::getReg(VA.getValNo(), VA.getValVT(), 1036 IReg, MVT::i64, CCValAssign::BCvt); 1037 else { 1038 assert(ValTy == MVT::f128 && "Unexpected type!"); 1039 // Full register, just bitconvert into i128 -- We will lower this into 1040 // two i64s in LowerCall_64. 1041 NewVA = CCValAssign::getCustomReg(VA.getValNo(), VA.getValVT(), 1042 IReg, MVT::i128, CCValAssign::BCvt); 1043 } 1044 } else { 1045 // This needs to go to memory, we're out of integer registers. 1046 NewVA = CCValAssign::getMem(VA.getValNo(), VA.getValVT(), 1047 Offset, VA.getLocVT(), VA.getLocInfo()); 1048 } 1049 ArgLocs[i] = NewVA; 1050 } 1051} 1052 1053// Lower a call for the 64-bit ABI. 1054SDValue 1055SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 1056 SmallVectorImpl<SDValue> &InVals) const { 1057 SelectionDAG &DAG = CLI.DAG; 1058 SDLoc DL = CLI.DL; 1059 SDValue Chain = CLI.Chain; 1060 1061 // Sparc target does not yet support tail call optimization. 1062 CLI.IsTailCall = false; 1063 1064 // Analyze operands of the call, assigning locations to each operand. 1065 SmallVector<CCValAssign, 16> ArgLocs; 1066 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 1067 DAG.getTarget(), ArgLocs, *DAG.getContext()); 1068 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64); 1069 1070 // Get the size of the outgoing arguments stack space requirement. 1071 // The stack offset computed by CC_Sparc64 includes all arguments. 1072 // Called functions expect 6 argument words to exist in the stack frame, used 1073 // or not. 1074 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset()); 1075 1076 // Keep stack frames 16-byte aligned. 1077 ArgsSize = RoundUpToAlignment(ArgsSize, 16); 1078 1079 // Varargs calls require special treatment. 1080 if (CLI.IsVarArg) 1081 fixupVariableFloatArgs(ArgLocs, CLI.Outs); 1082 1083 // Adjust the stack pointer to make room for the arguments. 1084 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls 1085 // with more than 6 arguments. 1086 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true), 1087 DL); 1088 1089 // Collect the set of registers to pass to the function and their values. 1090 // This will be emitted as a sequence of CopyToReg nodes glued to the call 1091 // instruction. 1092 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 1093 1094 // Collect chains from all the memory opeations that copy arguments to the 1095 // stack. They must follow the stack pointer adjustment above and precede the 1096 // call instruction itself. 1097 SmallVector<SDValue, 8> MemOpChains; 1098 1099 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1100 const CCValAssign &VA = ArgLocs[i]; 1101 SDValue Arg = CLI.OutVals[i]; 1102 1103 // Promote the value if needed. 1104 switch (VA.getLocInfo()) { 1105 default: 1106 llvm_unreachable("Unknown location info!"); 1107 case CCValAssign::Full: 1108 break; 1109 case CCValAssign::SExt: 1110 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); 1111 break; 1112 case CCValAssign::ZExt: 1113 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); 1114 break; 1115 case CCValAssign::AExt: 1116 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); 1117 break; 1118 case CCValAssign::BCvt: 1119 // fixupVariableFloatArgs() may create bitcasts from f128 to i128. But 1120 // SPARC does not support i128 natively. Lower it into two i64, see below. 1121 if (!VA.needsCustom() || VA.getValVT() != MVT::f128 1122 || VA.getLocVT() != MVT::i128) 1123 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); 1124 break; 1125 } 1126 1127 if (VA.isRegLoc()) { 1128 if (VA.needsCustom() && VA.getValVT() == MVT::f128 1129 && VA.getLocVT() == MVT::i128) { 1130 // Store and reload into the interger register reg and reg+1. 1131 unsigned Offset = 8 * (VA.getLocReg() - SP::I0); 1132 unsigned StackOffset = Offset + Subtarget->getStackPointerBias() + 128; 1133 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); 1134 SDValue HiPtrOff = DAG.getIntPtrConstant(StackOffset); 1135 HiPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 1136 HiPtrOff); 1137 SDValue LoPtrOff = DAG.getIntPtrConstant(StackOffset + 8); 1138 LoPtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, 1139 LoPtrOff); 1140 1141 // Store to %sp+BIAS+128+Offset 1142 SDValue Store = DAG.getStore(Chain, DL, Arg, HiPtrOff, 1143 MachinePointerInfo(), 1144 false, false, 0); 1145 // Load into Reg and Reg+1 1146 SDValue Hi64 = DAG.getLoad(MVT::i64, DL, Store, HiPtrOff, 1147 MachinePointerInfo(), 1148 false, false, false, 0); 1149 SDValue Lo64 = DAG.getLoad(MVT::i64, DL, Store, LoPtrOff, 1150 MachinePointerInfo(), 1151 false, false, false, 0); 1152 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), 1153 Hi64)); 1154 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()+1), 1155 Lo64)); 1156 continue; 1157 } 1158 1159 // The custom bit on an i32 return value indicates that it should be 1160 // passed in the high bits of the register. 1161 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 1162 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, 1163 DAG.getConstant(32, MVT::i32)); 1164 1165 // The next value may go in the low bits of the same register. 1166 // Handle both at once. 1167 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && 1168 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { 1169 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, 1170 CLI.OutVals[i+1]); 1171 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); 1172 // Skip the next value, it's already done. 1173 ++i; 1174 } 1175 } 1176 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); 1177 continue; 1178 } 1179 1180 assert(VA.isMemLoc()); 1181 1182 // Create a store off the stack pointer for this argument. 1183 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); 1184 // The argument area starts at %fp+BIAS+128 in the callee frame, 1185 // %sp+BIAS+128 in ours. 1186 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + 1187 Subtarget->getStackPointerBias() + 1188 128); 1189 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); 1190 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff, 1191 MachinePointerInfo(), 1192 false, false, 0)); 1193 } 1194 1195 // Emit all stores, make sure they occur before the call. 1196 if (!MemOpChains.empty()) 1197 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 1198 &MemOpChains[0], MemOpChains.size()); 1199 1200 // Build a sequence of CopyToReg nodes glued together with token chain and 1201 // glue operands which copy the outgoing args into registers. The InGlue is 1202 // necessary since all emitted instructions must be stuck together in order 1203 // to pass the live physical registers. 1204 SDValue InGlue; 1205 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1206 Chain = DAG.getCopyToReg(Chain, DL, 1207 RegsToPass[i].first, RegsToPass[i].second, InGlue); 1208 InGlue = Chain.getValue(1); 1209 } 1210 1211 // If the callee is a GlobalAddress node (quite common, every direct call is) 1212 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1213 // Likewise ExternalSymbol -> TargetExternalSymbol. 1214 SDValue Callee = CLI.Callee; 1215 bool hasReturnsTwice = hasReturnsTwiceAttr(DAG, Callee, CLI.CS); 1216 unsigned TF = ((getTargetMachine().getRelocationModel() == Reloc::PIC_) 1217 ? SparcMCExpr::VK_Sparc_WPLT30 : 0); 1218 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1219 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy(), 0, 1220 TF); 1221 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 1222 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy(), TF); 1223 1224 // Build the operands for the call instruction itself. 1225 SmallVector<SDValue, 8> Ops; 1226 Ops.push_back(Chain); 1227 Ops.push_back(Callee); 1228 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1229 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1230 RegsToPass[i].second.getValueType())); 1231 1232 // Add a register mask operand representing the call-preserved registers. 1233 const SparcRegisterInfo *TRI = 1234 ((const SparcTargetMachine&)getTargetMachine()).getRegisterInfo(); 1235 const uint32_t *Mask = ((hasReturnsTwice) 1236 ? TRI->getRTCallPreservedMask(CLI.CallConv) 1237 : TRI->getCallPreservedMask(CLI.CallConv)); 1238 assert(Mask && "Missing call preserved mask for calling convention"); 1239 Ops.push_back(DAG.getRegisterMask(Mask)); 1240 1241 // Make sure the CopyToReg nodes are glued to the call instruction which 1242 // consumes the registers. 1243 if (InGlue.getNode()) 1244 Ops.push_back(InGlue); 1245 1246 // Now the call itself. 1247 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1248 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size()); 1249 InGlue = Chain.getValue(1); 1250 1251 // Revert the stack pointer immediately after the call. 1252 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 1253 DAG.getIntPtrConstant(0, true), InGlue, DL); 1254 InGlue = Chain.getValue(1); 1255 1256 // Now extract the return values. This is more or less the same as 1257 // LowerFormalArguments_64. 1258 1259 // Assign locations to each value returned by this call. 1260 SmallVector<CCValAssign, 16> RVLocs; 1261 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 1262 DAG.getTarget(), RVLocs, *DAG.getContext()); 1263 1264 // Set inreg flag manually for codegen generated library calls that 1265 // return float. 1266 if (CLI.Ins.size() == 1 && CLI.Ins[0].VT == MVT::f32 && CLI.CS == 0) 1267 CLI.Ins[0].Flags.setInReg(); 1268 1269 RVInfo.AnalyzeCallResult(CLI.Ins, RetCC_Sparc64); 1270 1271 // Copy all of the result registers out of their specified physreg. 1272 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1273 CCValAssign &VA = RVLocs[i]; 1274 unsigned Reg = toCallerWindow(VA.getLocReg()); 1275 1276 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can 1277 // reside in the same register in the high and low bits. Reuse the 1278 // CopyFromReg previous node to avoid duplicate copies. 1279 SDValue RV; 1280 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1))) 1281 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) 1282 RV = Chain.getValue(0); 1283 1284 // But usually we'll create a new CopyFromReg for a different register. 1285 if (!RV.getNode()) { 1286 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue); 1287 Chain = RV.getValue(1); 1288 InGlue = Chain.getValue(2); 1289 } 1290 1291 // Get the high bits for i32 struct elements. 1292 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 1293 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, 1294 DAG.getConstant(32, MVT::i32)); 1295 1296 // The callee promoted the return value, so insert an Assert?ext SDNode so 1297 // we won't promote the value again in this function. 1298 switch (VA.getLocInfo()) { 1299 case CCValAssign::SExt: 1300 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, 1301 DAG.getValueType(VA.getValVT())); 1302 break; 1303 case CCValAssign::ZExt: 1304 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, 1305 DAG.getValueType(VA.getValVT())); 1306 break; 1307 default: 1308 break; 1309 } 1310 1311 // Truncate the register down to the return value type. 1312 if (VA.isExtInLoc()) 1313 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); 1314 1315 InVals.push_back(RV); 1316 } 1317 1318 return Chain; 1319} 1320 1321//===----------------------------------------------------------------------===// 1322// TargetLowering Implementation 1323//===----------------------------------------------------------------------===// 1324 1325/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 1326/// condition. 1327static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 1328 switch (CC) { 1329 default: llvm_unreachable("Unknown integer condition code!"); 1330 case ISD::SETEQ: return SPCC::ICC_E; 1331 case ISD::SETNE: return SPCC::ICC_NE; 1332 case ISD::SETLT: return SPCC::ICC_L; 1333 case ISD::SETGT: return SPCC::ICC_G; 1334 case ISD::SETLE: return SPCC::ICC_LE; 1335 case ISD::SETGE: return SPCC::ICC_GE; 1336 case ISD::SETULT: return SPCC::ICC_CS; 1337 case ISD::SETULE: return SPCC::ICC_LEU; 1338 case ISD::SETUGT: return SPCC::ICC_GU; 1339 case ISD::SETUGE: return SPCC::ICC_CC; 1340 } 1341} 1342 1343/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 1344/// FCC condition. 1345static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 1346 switch (CC) { 1347 default: llvm_unreachable("Unknown fp condition code!"); 1348 case ISD::SETEQ: 1349 case ISD::SETOEQ: return SPCC::FCC_E; 1350 case ISD::SETNE: 1351 case ISD::SETUNE: return SPCC::FCC_NE; 1352 case ISD::SETLT: 1353 case ISD::SETOLT: return SPCC::FCC_L; 1354 case ISD::SETGT: 1355 case ISD::SETOGT: return SPCC::FCC_G; 1356 case ISD::SETLE: 1357 case ISD::SETOLE: return SPCC::FCC_LE; 1358 case ISD::SETGE: 1359 case ISD::SETOGE: return SPCC::FCC_GE; 1360 case ISD::SETULT: return SPCC::FCC_UL; 1361 case ISD::SETULE: return SPCC::FCC_ULE; 1362 case ISD::SETUGT: return SPCC::FCC_UG; 1363 case ISD::SETUGE: return SPCC::FCC_UGE; 1364 case ISD::SETUO: return SPCC::FCC_U; 1365 case ISD::SETO: return SPCC::FCC_O; 1366 case ISD::SETONE: return SPCC::FCC_LG; 1367 case ISD::SETUEQ: return SPCC::FCC_UE; 1368 } 1369} 1370 1371SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 1372 : TargetLowering(TM, new SparcELFTargetObjectFile()) { 1373 Subtarget = &TM.getSubtarget<SparcSubtarget>(); 1374 1375 // Set up the register classes. 1376 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); 1377 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); 1378 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); 1379 addRegisterClass(MVT::f128, &SP::QFPRegsRegClass); 1380 if (Subtarget->is64Bit()) 1381 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); 1382 1383 // Turn FP extload into load/fextend 1384 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 1385 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); 1386 1387 // Sparc doesn't have i1 sign extending load 1388 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 1389 1390 // Turn FP truncstore into trunc + store. 1391 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 1392 setTruncStoreAction(MVT::f128, MVT::f32, Expand); 1393 setTruncStoreAction(MVT::f128, MVT::f64, Expand); 1394 1395 // Custom legalize GlobalAddress nodes into LO/HI parts. 1396 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom); 1397 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom); 1398 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom); 1399 setOperationAction(ISD::BlockAddress, getPointerTy(), Custom); 1400 1401 // Sparc doesn't have sext_inreg, replace them with shl/sra 1402 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 1403 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 1404 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 1405 1406 // Sparc has no REM or DIVREM operations. 1407 setOperationAction(ISD::UREM, MVT::i32, Expand); 1408 setOperationAction(ISD::SREM, MVT::i32, Expand); 1409 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 1410 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 1411 1412 // ... nor does SparcV9. 1413 if (Subtarget->is64Bit()) { 1414 setOperationAction(ISD::UREM, MVT::i64, Expand); 1415 setOperationAction(ISD::SREM, MVT::i64, Expand); 1416 setOperationAction(ISD::SDIVREM, MVT::i64, Expand); 1417 setOperationAction(ISD::UDIVREM, MVT::i64, Expand); 1418 } 1419 1420 // Custom expand fp<->sint 1421 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 1422 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 1423 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); 1424 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); 1425 1426 // Custom Expand fp<->uint 1427 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); 1428 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); 1429 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom); 1430 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); 1431 1432 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 1433 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 1434 1435 // Sparc has no select or setcc: expand to SELECT_CC. 1436 setOperationAction(ISD::SELECT, MVT::i32, Expand); 1437 setOperationAction(ISD::SELECT, MVT::f32, Expand); 1438 setOperationAction(ISD::SELECT, MVT::f64, Expand); 1439 setOperationAction(ISD::SELECT, MVT::f128, Expand); 1440 1441 setOperationAction(ISD::SETCC, MVT::i32, Expand); 1442 setOperationAction(ISD::SETCC, MVT::f32, Expand); 1443 setOperationAction(ISD::SETCC, MVT::f64, Expand); 1444 setOperationAction(ISD::SETCC, MVT::f128, Expand); 1445 1446 // Sparc doesn't have BRCOND either, it has BR_CC. 1447 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 1448 setOperationAction(ISD::BRIND, MVT::Other, Expand); 1449 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 1450 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 1451 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 1452 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 1453 setOperationAction(ISD::BR_CC, MVT::f128, Custom); 1454 1455 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 1456 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 1457 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 1458 setOperationAction(ISD::SELECT_CC, MVT::f128, Custom); 1459 1460 if (Subtarget->is64Bit()) { 1461 setOperationAction(ISD::ADDC, MVT::i64, Custom); 1462 setOperationAction(ISD::ADDE, MVT::i64, Custom); 1463 setOperationAction(ISD::SUBC, MVT::i64, Custom); 1464 setOperationAction(ISD::SUBE, MVT::i64, Custom); 1465 setOperationAction(ISD::BITCAST, MVT::f64, Expand); 1466 setOperationAction(ISD::BITCAST, MVT::i64, Expand); 1467 setOperationAction(ISD::SELECT, MVT::i64, Expand); 1468 setOperationAction(ISD::SETCC, MVT::i64, Expand); 1469 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 1470 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 1471 1472 setOperationAction(ISD::CTPOP, MVT::i64, 1473 Subtarget->usePopc() ? Legal : Expand); 1474 setOperationAction(ISD::CTTZ , MVT::i64, Expand); 1475 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand); 1476 setOperationAction(ISD::CTLZ , MVT::i64, Expand); 1477 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand); 1478 setOperationAction(ISD::BSWAP, MVT::i64, Expand); 1479 setOperationAction(ISD::ROTL , MVT::i64, Expand); 1480 setOperationAction(ISD::ROTR , MVT::i64, Expand); 1481 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Custom); 1482 } 1483 1484 // ATOMICs. 1485 // FIXME: We insert fences for each atomics and generate sub-optimal code 1486 // for PSO/TSO. Also, implement other atomicrmw operations. 1487 1488 setInsertFencesForAtomic(true); 1489 1490 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Legal); 1491 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, 1492 (Subtarget->isV9() ? Legal: Expand)); 1493 1494 1495 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Legal); 1496 1497 // Custom Lower Atomic LOAD/STORE 1498 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom); 1499 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom); 1500 1501 if (Subtarget->is64Bit()) { 1502 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Legal); 1503 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Legal); 1504 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 1505 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom); 1506 } 1507 1508 if (!Subtarget->isV9()) { 1509 // SparcV8 does not have FNEGD and FABSD. 1510 setOperationAction(ISD::FNEG, MVT::f64, Custom); 1511 setOperationAction(ISD::FABS, MVT::f64, Custom); 1512 } 1513 1514 setOperationAction(ISD::FSIN , MVT::f128, Expand); 1515 setOperationAction(ISD::FCOS , MVT::f128, Expand); 1516 setOperationAction(ISD::FSINCOS, MVT::f128, Expand); 1517 setOperationAction(ISD::FREM , MVT::f128, Expand); 1518 setOperationAction(ISD::FMA , MVT::f128, Expand); 1519 setOperationAction(ISD::FSIN , MVT::f64, Expand); 1520 setOperationAction(ISD::FCOS , MVT::f64, Expand); 1521 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 1522 setOperationAction(ISD::FREM , MVT::f64, Expand); 1523 setOperationAction(ISD::FMA , MVT::f64, Expand); 1524 setOperationAction(ISD::FSIN , MVT::f32, Expand); 1525 setOperationAction(ISD::FCOS , MVT::f32, Expand); 1526 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 1527 setOperationAction(ISD::FREM , MVT::f32, Expand); 1528 setOperationAction(ISD::FMA , MVT::f32, Expand); 1529 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 1530 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 1531 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 1532 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 1533 setOperationAction(ISD::ROTL , MVT::i32, Expand); 1534 setOperationAction(ISD::ROTR , MVT::i32, Expand); 1535 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 1536 setOperationAction(ISD::FCOPYSIGN, MVT::f128, Expand); 1537 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 1538 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 1539 setOperationAction(ISD::FPOW , MVT::f128, Expand); 1540 setOperationAction(ISD::FPOW , MVT::f64, Expand); 1541 setOperationAction(ISD::FPOW , MVT::f32, Expand); 1542 1543 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 1544 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 1545 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 1546 1547 // FIXME: Sparc provides these multiplies, but we don't have them yet. 1548 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 1549 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 1550 1551 if (Subtarget->is64Bit()) { 1552 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); 1553 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); 1554 setOperationAction(ISD::MULHU, MVT::i64, Expand); 1555 setOperationAction(ISD::MULHS, MVT::i64, Expand); 1556 1557 setOperationAction(ISD::UMULO, MVT::i64, Custom); 1558 setOperationAction(ISD::SMULO, MVT::i64, Custom); 1559 1560 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); 1561 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); 1562 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand); 1563 } 1564 1565 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 1566 setOperationAction(ISD::VASTART , MVT::Other, Custom); 1567 // VAARG needs to be lowered to not do unaligned accesses for doubles. 1568 setOperationAction(ISD::VAARG , MVT::Other, Custom); 1569 1570 setOperationAction(ISD::TRAP , MVT::Other, Legal); 1571 1572 // Use the default implementation. 1573 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 1574 setOperationAction(ISD::VAEND , MVT::Other, Expand); 1575 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 1576 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 1577 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 1578 1579 setExceptionPointerRegister(SP::I0); 1580 setExceptionSelectorRegister(SP::I1); 1581 1582 setStackPointerRegisterToSaveRestore(SP::O6); 1583 1584 setOperationAction(ISD::CTPOP, MVT::i32, 1585 Subtarget->usePopc() ? Legal : Expand); 1586 1587 if (Subtarget->isV9() && Subtarget->hasHardQuad()) { 1588 setOperationAction(ISD::LOAD, MVT::f128, Legal); 1589 setOperationAction(ISD::STORE, MVT::f128, Legal); 1590 } else { 1591 setOperationAction(ISD::LOAD, MVT::f128, Custom); 1592 setOperationAction(ISD::STORE, MVT::f128, Custom); 1593 } 1594 1595 if (Subtarget->hasHardQuad()) { 1596 setOperationAction(ISD::FADD, MVT::f128, Legal); 1597 setOperationAction(ISD::FSUB, MVT::f128, Legal); 1598 setOperationAction(ISD::FMUL, MVT::f128, Legal); 1599 setOperationAction(ISD::FDIV, MVT::f128, Legal); 1600 setOperationAction(ISD::FSQRT, MVT::f128, Legal); 1601 setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal); 1602 setOperationAction(ISD::FP_ROUND, MVT::f64, Legal); 1603 if (Subtarget->isV9()) { 1604 setOperationAction(ISD::FNEG, MVT::f128, Legal); 1605 setOperationAction(ISD::FABS, MVT::f128, Legal); 1606 } else { 1607 setOperationAction(ISD::FNEG, MVT::f128, Custom); 1608 setOperationAction(ISD::FABS, MVT::f128, Custom); 1609 } 1610 1611 if (!Subtarget->is64Bit()) { 1612 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll"); 1613 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull"); 1614 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq"); 1615 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq"); 1616 } 1617 1618 } else { 1619 // Custom legalize f128 operations. 1620 1621 setOperationAction(ISD::FADD, MVT::f128, Custom); 1622 setOperationAction(ISD::FSUB, MVT::f128, Custom); 1623 setOperationAction(ISD::FMUL, MVT::f128, Custom); 1624 setOperationAction(ISD::FDIV, MVT::f128, Custom); 1625 setOperationAction(ISD::FSQRT, MVT::f128, Custom); 1626 setOperationAction(ISD::FNEG, MVT::f128, Custom); 1627 setOperationAction(ISD::FABS, MVT::f128, Custom); 1628 1629 setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom); 1630 setOperationAction(ISD::FP_ROUND, MVT::f64, Custom); 1631 setOperationAction(ISD::FP_ROUND, MVT::f32, Custom); 1632 1633 // Setup Runtime library names. 1634 if (Subtarget->is64Bit()) { 1635 setLibcallName(RTLIB::ADD_F128, "_Qp_add"); 1636 setLibcallName(RTLIB::SUB_F128, "_Qp_sub"); 1637 setLibcallName(RTLIB::MUL_F128, "_Qp_mul"); 1638 setLibcallName(RTLIB::DIV_F128, "_Qp_div"); 1639 setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt"); 1640 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi"); 1641 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui"); 1642 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq"); 1643 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq"); 1644 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox"); 1645 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux"); 1646 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq"); 1647 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq"); 1648 setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq"); 1649 setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq"); 1650 setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos"); 1651 setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod"); 1652 } else { 1653 setLibcallName(RTLIB::ADD_F128, "_Q_add"); 1654 setLibcallName(RTLIB::SUB_F128, "_Q_sub"); 1655 setLibcallName(RTLIB::MUL_F128, "_Q_mul"); 1656 setLibcallName(RTLIB::DIV_F128, "_Q_div"); 1657 setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt"); 1658 setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi"); 1659 setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou"); 1660 setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq"); 1661 setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Q_utoq"); 1662 setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Q_qtoll"); 1663 setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Q_qtoull"); 1664 setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Q_lltoq"); 1665 setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Q_ulltoq"); 1666 setLibcallName(RTLIB::FPEXT_F32_F128, "_Q_stoq"); 1667 setLibcallName(RTLIB::FPEXT_F64_F128, "_Q_dtoq"); 1668 setLibcallName(RTLIB::FPROUND_F128_F32, "_Q_qtos"); 1669 setLibcallName(RTLIB::FPROUND_F128_F64, "_Q_qtod"); 1670 } 1671 } 1672 1673 setMinFunctionAlignment(2); 1674 1675 computeRegisterProperties(); 1676} 1677 1678const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 1679 switch (Opcode) { 1680 default: return 0; 1681 case SPISD::CMPICC: return "SPISD::CMPICC"; 1682 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 1683 case SPISD::BRICC: return "SPISD::BRICC"; 1684 case SPISD::BRXCC: return "SPISD::BRXCC"; 1685 case SPISD::BRFCC: return "SPISD::BRFCC"; 1686 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 1687 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC"; 1688 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 1689 case SPISD::Hi: return "SPISD::Hi"; 1690 case SPISD::Lo: return "SPISD::Lo"; 1691 case SPISD::FTOI: return "SPISD::FTOI"; 1692 case SPISD::ITOF: return "SPISD::ITOF"; 1693 case SPISD::FTOX: return "SPISD::FTOX"; 1694 case SPISD::XTOF: return "SPISD::XTOF"; 1695 case SPISD::CALL: return "SPISD::CALL"; 1696 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 1697 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; 1698 case SPISD::FLUSHW: return "SPISD::FLUSHW"; 1699 case SPISD::TLS_ADD: return "SPISD::TLS_ADD"; 1700 case SPISD::TLS_LD: return "SPISD::TLS_LD"; 1701 case SPISD::TLS_CALL: return "SPISD::TLS_CALL"; 1702 } 1703} 1704 1705EVT SparcTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const { 1706 if (!VT.isVector()) 1707 return MVT::i32; 1708 return VT.changeVectorElementTypeToInteger(); 1709} 1710 1711/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 1712/// be zero. Op is expected to be a target specific node. Used by DAG 1713/// combiner. 1714void SparcTargetLowering::computeMaskedBitsForTargetNode 1715 (const SDValue Op, 1716 APInt &KnownZero, 1717 APInt &KnownOne, 1718 const SelectionDAG &DAG, 1719 unsigned Depth) const { 1720 APInt KnownZero2, KnownOne2; 1721 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 1722 1723 switch (Op.getOpcode()) { 1724 default: break; 1725 case SPISD::SELECT_ICC: 1726 case SPISD::SELECT_XCC: 1727 case SPISD::SELECT_FCC: 1728 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); 1729 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); 1730 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1731 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1732 1733 // Only known if known in both the LHS and RHS. 1734 KnownOne &= KnownOne2; 1735 KnownZero &= KnownZero2; 1736 break; 1737 } 1738} 1739 1740// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 1741// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 1742static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 1743 ISD::CondCode CC, unsigned &SPCC) { 1744 if (isa<ConstantSDNode>(RHS) && 1745 cast<ConstantSDNode>(RHS)->isNullValue() && 1746 CC == ISD::SETNE && 1747 (((LHS.getOpcode() == SPISD::SELECT_ICC || 1748 LHS.getOpcode() == SPISD::SELECT_XCC) && 1749 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 1750 (LHS.getOpcode() == SPISD::SELECT_FCC && 1751 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 1752 isa<ConstantSDNode>(LHS.getOperand(0)) && 1753 isa<ConstantSDNode>(LHS.getOperand(1)) && 1754 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && 1755 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { 1756 SDValue CMPCC = LHS.getOperand(3); 1757 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 1758 LHS = CMPCC.getOperand(0); 1759 RHS = CMPCC.getOperand(1); 1760 } 1761} 1762 1763// Convert to a target node and set target flags. 1764SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF, 1765 SelectionDAG &DAG) const { 1766 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) 1767 return DAG.getTargetGlobalAddress(GA->getGlobal(), 1768 SDLoc(GA), 1769 GA->getValueType(0), 1770 GA->getOffset(), TF); 1771 1772 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) 1773 return DAG.getTargetConstantPool(CP->getConstVal(), 1774 CP->getValueType(0), 1775 CP->getAlignment(), 1776 CP->getOffset(), TF); 1777 1778 if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) 1779 return DAG.getTargetBlockAddress(BA->getBlockAddress(), 1780 Op.getValueType(), 1781 0, 1782 TF); 1783 1784 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) 1785 return DAG.getTargetExternalSymbol(ES->getSymbol(), 1786 ES->getValueType(0), TF); 1787 1788 llvm_unreachable("Unhandled address SDNode"); 1789} 1790 1791// Split Op into high and low parts according to HiTF and LoTF. 1792// Return an ADD node combining the parts. 1793SDValue SparcTargetLowering::makeHiLoPair(SDValue Op, 1794 unsigned HiTF, unsigned LoTF, 1795 SelectionDAG &DAG) const { 1796 SDLoc DL(Op); 1797 EVT VT = Op.getValueType(); 1798 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG)); 1799 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG)); 1800 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); 1801} 1802 1803// Build SDNodes for producing an address from a GlobalAddress, ConstantPool, 1804// or ExternalSymbol SDNode. 1805SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const { 1806 SDLoc DL(Op); 1807 EVT VT = getPointerTy(); 1808 1809 // Handle PIC mode first. 1810 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1811 // This is the pic32 code model, the GOT is known to be smaller than 4GB. 1812 SDValue HiLo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_GOT22, 1813 SparcMCExpr::VK_Sparc_GOT10, DAG); 1814 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT); 1815 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo); 1816 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this 1817 // function has calls. 1818 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1819 MFI->setHasCalls(true); 1820 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr, 1821 MachinePointerInfo::getGOT(), false, false, false, 0); 1822 } 1823 1824 // This is one of the absolute code models. 1825 switch(getTargetMachine().getCodeModel()) { 1826 default: 1827 llvm_unreachable("Unsupported absolute code model"); 1828 case CodeModel::Small: 1829 // abs32. 1830 return makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI, 1831 SparcMCExpr::VK_Sparc_LO, DAG); 1832 case CodeModel::Medium: { 1833 // abs44. 1834 SDValue H44 = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_H44, 1835 SparcMCExpr::VK_Sparc_M44, DAG); 1836 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32)); 1837 SDValue L44 = withTargetFlags(Op, SparcMCExpr::VK_Sparc_L44, DAG); 1838 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44); 1839 return DAG.getNode(ISD::ADD, DL, VT, H44, L44); 1840 } 1841 case CodeModel::Large: { 1842 // abs64. 1843 SDValue Hi = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HH, 1844 SparcMCExpr::VK_Sparc_HM, DAG); 1845 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32)); 1846 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI, 1847 SparcMCExpr::VK_Sparc_LO, DAG); 1848 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); 1849 } 1850 } 1851} 1852 1853SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, 1854 SelectionDAG &DAG) const { 1855 return makeAddress(Op, DAG); 1856} 1857 1858SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, 1859 SelectionDAG &DAG) const { 1860 return makeAddress(Op, DAG); 1861} 1862 1863SDValue SparcTargetLowering::LowerBlockAddress(SDValue Op, 1864 SelectionDAG &DAG) const { 1865 return makeAddress(Op, DAG); 1866} 1867 1868SDValue SparcTargetLowering::LowerGlobalTLSAddress(SDValue Op, 1869 SelectionDAG &DAG) const { 1870 1871 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1872 SDLoc DL(GA); 1873 const GlobalValue *GV = GA->getGlobal(); 1874 EVT PtrVT = getPointerTy(); 1875 1876 TLSModel::Model model = getTargetMachine().getTLSModel(GV); 1877 1878 if (model == TLSModel::GeneralDynamic || model == TLSModel::LocalDynamic) { 1879 unsigned HiTF = ((model == TLSModel::GeneralDynamic) 1880 ? SparcMCExpr::VK_Sparc_TLS_GD_HI22 1881 : SparcMCExpr::VK_Sparc_TLS_LDM_HI22); 1882 unsigned LoTF = ((model == TLSModel::GeneralDynamic) 1883 ? SparcMCExpr::VK_Sparc_TLS_GD_LO10 1884 : SparcMCExpr::VK_Sparc_TLS_LDM_LO10); 1885 unsigned addTF = ((model == TLSModel::GeneralDynamic) 1886 ? SparcMCExpr::VK_Sparc_TLS_GD_ADD 1887 : SparcMCExpr::VK_Sparc_TLS_LDM_ADD); 1888 unsigned callTF = ((model == TLSModel::GeneralDynamic) 1889 ? SparcMCExpr::VK_Sparc_TLS_GD_CALL 1890 : SparcMCExpr::VK_Sparc_TLS_LDM_CALL); 1891 1892 SDValue HiLo = makeHiLoPair(Op, HiTF, LoTF, DAG); 1893 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT); 1894 SDValue Argument = DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Base, HiLo, 1895 withTargetFlags(Op, addTF, DAG)); 1896 1897 SDValue Chain = DAG.getEntryNode(); 1898 SDValue InFlag; 1899 1900 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(1, true), DL); 1901 Chain = DAG.getCopyToReg(Chain, DL, SP::O0, Argument, InFlag); 1902 InFlag = Chain.getValue(1); 1903 SDValue Callee = DAG.getTargetExternalSymbol("__tls_get_addr", PtrVT); 1904 SDValue Symbol = withTargetFlags(Op, callTF, DAG); 1905 1906 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1907 SmallVector<SDValue, 4> Ops; 1908 Ops.push_back(Chain); 1909 Ops.push_back(Callee); 1910 Ops.push_back(Symbol); 1911 Ops.push_back(DAG.getRegister(SP::O0, PtrVT)); 1912 const uint32_t *Mask = getTargetMachine() 1913 .getRegisterInfo()->getCallPreservedMask(CallingConv::C); 1914 assert(Mask && "Missing call preserved mask for calling convention"); 1915 Ops.push_back(DAG.getRegisterMask(Mask)); 1916 Ops.push_back(InFlag); 1917 Chain = DAG.getNode(SPISD::TLS_CALL, DL, NodeTys, &Ops[0], Ops.size()); 1918 InFlag = Chain.getValue(1); 1919 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(1, true), 1920 DAG.getIntPtrConstant(0, true), InFlag, DL); 1921 InFlag = Chain.getValue(1); 1922 SDValue Ret = DAG.getCopyFromReg(Chain, DL, SP::O0, PtrVT, InFlag); 1923 1924 if (model != TLSModel::LocalDynamic) 1925 return Ret; 1926 1927 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT, 1928 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_HIX22, DAG)); 1929 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT, 1930 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_LOX10, DAG)); 1931 HiLo = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); 1932 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, Ret, HiLo, 1933 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LDO_ADD, DAG)); 1934 } 1935 1936 if (model == TLSModel::InitialExec) { 1937 unsigned ldTF = ((PtrVT == MVT::i64)? SparcMCExpr::VK_Sparc_TLS_IE_LDX 1938 : SparcMCExpr::VK_Sparc_TLS_IE_LD); 1939 1940 SDValue Base = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, PtrVT); 1941 1942 // GLOBAL_BASE_REG codegen'ed with call. Inform MFI that this 1943 // function has calls. 1944 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1945 MFI->setHasCalls(true); 1946 1947 SDValue TGA = makeHiLoPair(Op, 1948 SparcMCExpr::VK_Sparc_TLS_IE_HI22, 1949 SparcMCExpr::VK_Sparc_TLS_IE_LO10, DAG); 1950 SDValue Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Base, TGA); 1951 SDValue Offset = DAG.getNode(SPISD::TLS_LD, 1952 DL, PtrVT, Ptr, 1953 withTargetFlags(Op, ldTF, DAG)); 1954 return DAG.getNode(SPISD::TLS_ADD, DL, PtrVT, 1955 DAG.getRegister(SP::G7, PtrVT), Offset, 1956 withTargetFlags(Op, 1957 SparcMCExpr::VK_Sparc_TLS_IE_ADD, DAG)); 1958 } 1959 1960 assert(model == TLSModel::LocalExec); 1961 SDValue Hi = DAG.getNode(SPISD::Hi, DL, PtrVT, 1962 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_HIX22, DAG)); 1963 SDValue Lo = DAG.getNode(SPISD::Lo, DL, PtrVT, 1964 withTargetFlags(Op, SparcMCExpr::VK_Sparc_TLS_LE_LOX10, DAG)); 1965 SDValue Offset = DAG.getNode(ISD::XOR, DL, PtrVT, Hi, Lo); 1966 1967 return DAG.getNode(ISD::ADD, DL, PtrVT, 1968 DAG.getRegister(SP::G7, PtrVT), Offset); 1969} 1970 1971SDValue 1972SparcTargetLowering::LowerF128_LibCallArg(SDValue Chain, ArgListTy &Args, 1973 SDValue Arg, SDLoc DL, 1974 SelectionDAG &DAG) const { 1975 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1976 EVT ArgVT = Arg.getValueType(); 1977 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1978 1979 ArgListEntry Entry; 1980 Entry.Node = Arg; 1981 Entry.Ty = ArgTy; 1982 1983 if (ArgTy->isFP128Ty()) { 1984 // Create a stack object and pass the pointer to the library function. 1985 int FI = MFI->CreateStackObject(16, 8, false); 1986 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 1987 Chain = DAG.getStore(Chain, 1988 DL, 1989 Entry.Node, 1990 FIPtr, 1991 MachinePointerInfo(), 1992 false, 1993 false, 1994 8); 1995 1996 Entry.Node = FIPtr; 1997 Entry.Ty = PointerType::getUnqual(ArgTy); 1998 } 1999 Args.push_back(Entry); 2000 return Chain; 2001} 2002 2003SDValue 2004SparcTargetLowering::LowerF128Op(SDValue Op, SelectionDAG &DAG, 2005 const char *LibFuncName, 2006 unsigned numArgs) const { 2007 2008 ArgListTy Args; 2009 2010 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2011 2012 SDValue Callee = DAG.getExternalSymbol(LibFuncName, getPointerTy()); 2013 Type *RetTy = Op.getValueType().getTypeForEVT(*DAG.getContext()); 2014 Type *RetTyABI = RetTy; 2015 SDValue Chain = DAG.getEntryNode(); 2016 SDValue RetPtr; 2017 2018 if (RetTy->isFP128Ty()) { 2019 // Create a Stack Object to receive the return value of type f128. 2020 ArgListEntry Entry; 2021 int RetFI = MFI->CreateStackObject(16, 8, false); 2022 RetPtr = DAG.getFrameIndex(RetFI, getPointerTy()); 2023 Entry.Node = RetPtr; 2024 Entry.Ty = PointerType::getUnqual(RetTy); 2025 if (!Subtarget->is64Bit()) 2026 Entry.isSRet = true; 2027 Entry.isReturned = false; 2028 Args.push_back(Entry); 2029 RetTyABI = Type::getVoidTy(*DAG.getContext()); 2030 } 2031 2032 assert(Op->getNumOperands() >= numArgs && "Not enough operands!"); 2033 for (unsigned i = 0, e = numArgs; i != e; ++i) { 2034 Chain = LowerF128_LibCallArg(Chain, Args, Op.getOperand(i), SDLoc(Op), DAG); 2035 } 2036 TargetLowering:: 2037 CallLoweringInfo CLI(Chain, 2038 RetTyABI, 2039 false, false, false, false, 2040 0, CallingConv::C, 2041 false, false, true, 2042 Callee, Args, DAG, SDLoc(Op)); 2043 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); 2044 2045 // chain is in second result. 2046 if (RetTyABI == RetTy) 2047 return CallInfo.first; 2048 2049 assert (RetTy->isFP128Ty() && "Unexpected return type!"); 2050 2051 Chain = CallInfo.second; 2052 2053 // Load RetPtr to get the return value. 2054 return DAG.getLoad(Op.getValueType(), 2055 SDLoc(Op), 2056 Chain, 2057 RetPtr, 2058 MachinePointerInfo(), 2059 false, false, false, 8); 2060} 2061 2062SDValue 2063SparcTargetLowering::LowerF128Compare(SDValue LHS, SDValue RHS, 2064 unsigned &SPCC, 2065 SDLoc DL, 2066 SelectionDAG &DAG) const { 2067 2068 const char *LibCall = 0; 2069 bool is64Bit = Subtarget->is64Bit(); 2070 switch(SPCC) { 2071 default: llvm_unreachable("Unhandled conditional code!"); 2072 case SPCC::FCC_E : LibCall = is64Bit? "_Qp_feq" : "_Q_feq"; break; 2073 case SPCC::FCC_NE : LibCall = is64Bit? "_Qp_fne" : "_Q_fne"; break; 2074 case SPCC::FCC_L : LibCall = is64Bit? "_Qp_flt" : "_Q_flt"; break; 2075 case SPCC::FCC_G : LibCall = is64Bit? "_Qp_fgt" : "_Q_fgt"; break; 2076 case SPCC::FCC_LE : LibCall = is64Bit? "_Qp_fle" : "_Q_fle"; break; 2077 case SPCC::FCC_GE : LibCall = is64Bit? "_Qp_fge" : "_Q_fge"; break; 2078 case SPCC::FCC_UL : 2079 case SPCC::FCC_ULE: 2080 case SPCC::FCC_UG : 2081 case SPCC::FCC_UGE: 2082 case SPCC::FCC_U : 2083 case SPCC::FCC_O : 2084 case SPCC::FCC_LG : 2085 case SPCC::FCC_UE : LibCall = is64Bit? "_Qp_cmp" : "_Q_cmp"; break; 2086 } 2087 2088 SDValue Callee = DAG.getExternalSymbol(LibCall, getPointerTy()); 2089 Type *RetTy = Type::getInt32Ty(*DAG.getContext()); 2090 ArgListTy Args; 2091 SDValue Chain = DAG.getEntryNode(); 2092 Chain = LowerF128_LibCallArg(Chain, Args, LHS, DL, DAG); 2093 Chain = LowerF128_LibCallArg(Chain, Args, RHS, DL, DAG); 2094 2095 TargetLowering:: 2096 CallLoweringInfo CLI(Chain, 2097 RetTy, 2098 false, false, false, false, 2099 0, CallingConv::C, 2100 false, false, true, 2101 Callee, Args, DAG, DL); 2102 2103 std::pair<SDValue, SDValue> CallInfo = LowerCallTo(CLI); 2104 2105 // result is in first, and chain is in second result. 2106 SDValue Result = CallInfo.first; 2107 2108 switch(SPCC) { 2109 default: { 2110 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2111 SPCC = SPCC::ICC_NE; 2112 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2113 } 2114 case SPCC::FCC_UL : { 2115 SDValue Mask = DAG.getTargetConstant(1, Result.getValueType()); 2116 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); 2117 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2118 SPCC = SPCC::ICC_NE; 2119 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2120 } 2121 case SPCC::FCC_ULE: { 2122 SDValue RHS = DAG.getTargetConstant(2, Result.getValueType()); 2123 SPCC = SPCC::ICC_NE; 2124 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2125 } 2126 case SPCC::FCC_UG : { 2127 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType()); 2128 SPCC = SPCC::ICC_G; 2129 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2130 } 2131 case SPCC::FCC_UGE: { 2132 SDValue RHS = DAG.getTargetConstant(1, Result.getValueType()); 2133 SPCC = SPCC::ICC_NE; 2134 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2135 } 2136 2137 case SPCC::FCC_U : { 2138 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType()); 2139 SPCC = SPCC::ICC_E; 2140 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2141 } 2142 case SPCC::FCC_O : { 2143 SDValue RHS = DAG.getTargetConstant(3, Result.getValueType()); 2144 SPCC = SPCC::ICC_NE; 2145 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2146 } 2147 case SPCC::FCC_LG : { 2148 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); 2149 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); 2150 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2151 SPCC = SPCC::ICC_NE; 2152 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2153 } 2154 case SPCC::FCC_UE : { 2155 SDValue Mask = DAG.getTargetConstant(3, Result.getValueType()); 2156 Result = DAG.getNode(ISD::AND, DL, Result.getValueType(), Result, Mask); 2157 SDValue RHS = DAG.getTargetConstant(0, Result.getValueType()); 2158 SPCC = SPCC::ICC_E; 2159 return DAG.getNode(SPISD::CMPICC, DL, MVT::Glue, Result, RHS); 2160 } 2161 } 2162} 2163 2164static SDValue 2165LowerF128_FPEXTEND(SDValue Op, SelectionDAG &DAG, 2166 const SparcTargetLowering &TLI) { 2167 2168 if (Op.getOperand(0).getValueType() == MVT::f64) 2169 return TLI.LowerF128Op(Op, DAG, 2170 TLI.getLibcallName(RTLIB::FPEXT_F64_F128), 1); 2171 2172 if (Op.getOperand(0).getValueType() == MVT::f32) 2173 return TLI.LowerF128Op(Op, DAG, 2174 TLI.getLibcallName(RTLIB::FPEXT_F32_F128), 1); 2175 2176 llvm_unreachable("fpextend with non-float operand!"); 2177 return SDValue(0, 0); 2178} 2179 2180static SDValue 2181LowerF128_FPROUND(SDValue Op, SelectionDAG &DAG, 2182 const SparcTargetLowering &TLI) { 2183 // FP_ROUND on f64 and f32 are legal. 2184 if (Op.getOperand(0).getValueType() != MVT::f128) 2185 return Op; 2186 2187 if (Op.getValueType() == MVT::f64) 2188 return TLI.LowerF128Op(Op, DAG, 2189 TLI.getLibcallName(RTLIB::FPROUND_F128_F64), 1); 2190 if (Op.getValueType() == MVT::f32) 2191 return TLI.LowerF128Op(Op, DAG, 2192 TLI.getLibcallName(RTLIB::FPROUND_F128_F32), 1); 2193 2194 llvm_unreachable("fpround to non-float!"); 2195 return SDValue(0, 0); 2196} 2197 2198static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG, 2199 const SparcTargetLowering &TLI, 2200 bool hasHardQuad) { 2201 SDLoc dl(Op); 2202 EVT VT = Op.getValueType(); 2203 assert(VT == MVT::i32 || VT == MVT::i64); 2204 2205 // Expand f128 operations to fp128 abi calls. 2206 if (Op.getOperand(0).getValueType() == MVT::f128 2207 && (!hasHardQuad || !TLI.isTypeLegal(VT))) { 2208 const char *libName = TLI.getLibcallName(VT == MVT::i32 2209 ? RTLIB::FPTOSINT_F128_I32 2210 : RTLIB::FPTOSINT_F128_I64); 2211 return TLI.LowerF128Op(Op, DAG, libName, 1); 2212 } 2213 2214 // Expand if the resulting type is illegal. 2215 if (!TLI.isTypeLegal(VT)) 2216 return SDValue(0, 0); 2217 2218 // Otherwise, Convert the fp value to integer in an FP register. 2219 if (VT == MVT::i32) 2220 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 2221 else 2222 Op = DAG.getNode(SPISD::FTOX, dl, MVT::f64, Op.getOperand(0)); 2223 2224 return DAG.getNode(ISD::BITCAST, dl, VT, Op); 2225} 2226 2227static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG, 2228 const SparcTargetLowering &TLI, 2229 bool hasHardQuad) { 2230 SDLoc dl(Op); 2231 EVT OpVT = Op.getOperand(0).getValueType(); 2232 assert(OpVT == MVT::i32 || (OpVT == MVT::i64)); 2233 2234 EVT floatVT = (OpVT == MVT::i32) ? MVT::f32 : MVT::f64; 2235 2236 // Expand f128 operations to fp128 ABI calls. 2237 if (Op.getValueType() == MVT::f128 2238 && (!hasHardQuad || !TLI.isTypeLegal(OpVT))) { 2239 const char *libName = TLI.getLibcallName(OpVT == MVT::i32 2240 ? RTLIB::SINTTOFP_I32_F128 2241 : RTLIB::SINTTOFP_I64_F128); 2242 return TLI.LowerF128Op(Op, DAG, libName, 1); 2243 } 2244 2245 // Expand if the operand type is illegal. 2246 if (!TLI.isTypeLegal(OpVT)) 2247 return SDValue(0, 0); 2248 2249 // Otherwise, Convert the int value to FP in an FP register. 2250 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, floatVT, Op.getOperand(0)); 2251 unsigned opcode = (OpVT == MVT::i32)? SPISD::ITOF : SPISD::XTOF; 2252 return DAG.getNode(opcode, dl, Op.getValueType(), Tmp); 2253} 2254 2255static SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG, 2256 const SparcTargetLowering &TLI, 2257 bool hasHardQuad) { 2258 SDLoc dl(Op); 2259 EVT VT = Op.getValueType(); 2260 2261 // Expand if it does not involve f128 or the target has support for 2262 // quad floating point instructions and the resulting type is legal. 2263 if (Op.getOperand(0).getValueType() != MVT::f128 || 2264 (hasHardQuad && TLI.isTypeLegal(VT))) 2265 return SDValue(0, 0); 2266 2267 assert(VT == MVT::i32 || VT == MVT::i64); 2268 2269 return TLI.LowerF128Op(Op, DAG, 2270 TLI.getLibcallName(VT == MVT::i32 2271 ? RTLIB::FPTOUINT_F128_I32 2272 : RTLIB::FPTOUINT_F128_I64), 2273 1); 2274} 2275 2276static SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG, 2277 const SparcTargetLowering &TLI, 2278 bool hasHardQuad) { 2279 SDLoc dl(Op); 2280 EVT OpVT = Op.getOperand(0).getValueType(); 2281 assert(OpVT == MVT::i32 || OpVT == MVT::i64); 2282 2283 // Expand if it does not involve f128 or the target has support for 2284 // quad floating point instructions and the operand type is legal. 2285 if (Op.getValueType() != MVT::f128 || (hasHardQuad && TLI.isTypeLegal(OpVT))) 2286 return SDValue(0, 0); 2287 2288 return TLI.LowerF128Op(Op, DAG, 2289 TLI.getLibcallName(OpVT == MVT::i32 2290 ? RTLIB::UINTTOFP_I32_F128 2291 : RTLIB::UINTTOFP_I64_F128), 2292 1); 2293} 2294 2295static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, 2296 const SparcTargetLowering &TLI, 2297 bool hasHardQuad) { 2298 SDValue Chain = Op.getOperand(0); 2299 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 2300 SDValue LHS = Op.getOperand(2); 2301 SDValue RHS = Op.getOperand(3); 2302 SDValue Dest = Op.getOperand(4); 2303 SDLoc dl(Op); 2304 unsigned Opc, SPCC = ~0U; 2305 2306 // If this is a br_cc of a "setcc", and if the setcc got lowered into 2307 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 2308 LookThroughSetCC(LHS, RHS, CC, SPCC); 2309 2310 // Get the condition flag. 2311 SDValue CompareFlag; 2312 if (LHS.getValueType().isInteger()) { 2313 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); 2314 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 2315 // 32-bit compares use the icc flags, 64-bit uses the xcc flags. 2316 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC; 2317 } else { 2318 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { 2319 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2320 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG); 2321 Opc = SPISD::BRICC; 2322 } else { 2323 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 2324 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2325 Opc = SPISD::BRFCC; 2326 } 2327 } 2328 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 2329 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 2330} 2331 2332static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, 2333 const SparcTargetLowering &TLI, 2334 bool hasHardQuad) { 2335 SDValue LHS = Op.getOperand(0); 2336 SDValue RHS = Op.getOperand(1); 2337 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 2338 SDValue TrueVal = Op.getOperand(2); 2339 SDValue FalseVal = Op.getOperand(3); 2340 SDLoc dl(Op); 2341 unsigned Opc, SPCC = ~0U; 2342 2343 // If this is a select_cc of a "setcc", and if the setcc got lowered into 2344 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 2345 LookThroughSetCC(LHS, RHS, CC, SPCC); 2346 2347 SDValue CompareFlag; 2348 if (LHS.getValueType().isInteger()) { 2349 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, MVT::Glue, LHS, RHS); 2350 Opc = LHS.getValueType() == MVT::i32 ? 2351 SPISD::SELECT_ICC : SPISD::SELECT_XCC; 2352 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 2353 } else { 2354 if (!hasHardQuad && LHS.getValueType() == MVT::f128) { 2355 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2356 CompareFlag = TLI.LowerF128Compare(LHS, RHS, SPCC, dl, DAG); 2357 Opc = SPISD::SELECT_ICC; 2358 } else { 2359 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 2360 Opc = SPISD::SELECT_FCC; 2361 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 2362 } 2363 } 2364 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 2365 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 2366} 2367 2368static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 2369 const SparcTargetLowering &TLI) { 2370 MachineFunction &MF = DAG.getMachineFunction(); 2371 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 2372 2373 // Need frame address to find the address of VarArgsFrameIndex. 2374 MF.getFrameInfo()->setFrameAddressIsTaken(true); 2375 2376 // vastart just stores the address of the VarArgsFrameIndex slot into the 2377 // memory location argument. 2378 SDLoc DL(Op); 2379 SDValue Offset = 2380 DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), 2381 DAG.getRegister(SP::I6, TLI.getPointerTy()), 2382 DAG.getIntPtrConstant(FuncInfo->getVarArgsFrameOffset())); 2383 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 2384 return DAG.getStore(Op.getOperand(0), DL, Offset, Op.getOperand(1), 2385 MachinePointerInfo(SV), false, false, 0); 2386} 2387 2388static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 2389 SDNode *Node = Op.getNode(); 2390 EVT VT = Node->getValueType(0); 2391 SDValue InChain = Node->getOperand(0); 2392 SDValue VAListPtr = Node->getOperand(1); 2393 EVT PtrVT = VAListPtr.getValueType(); 2394 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2395 SDLoc DL(Node); 2396 SDValue VAList = DAG.getLoad(PtrVT, DL, InChain, VAListPtr, 2397 MachinePointerInfo(SV), false, false, false, 0); 2398 // Increment the pointer, VAList, to the next vaarg. 2399 SDValue NextPtr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList, 2400 DAG.getIntPtrConstant(VT.getSizeInBits()/8)); 2401 // Store the incremented VAList to the legalized pointer. 2402 InChain = DAG.getStore(VAList.getValue(1), DL, NextPtr, 2403 VAListPtr, MachinePointerInfo(SV), false, false, 0); 2404 // Load the actual argument out of the pointer VAList. 2405 // We can't count on greater alignment than the word size. 2406 return DAG.getLoad(VT, DL, InChain, VAList, MachinePointerInfo(), 2407 false, false, false, 2408 std::min(PtrVT.getSizeInBits(), VT.getSizeInBits())/8); 2409} 2410 2411static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG, 2412 const SparcSubtarget *Subtarget) { 2413 SDValue Chain = Op.getOperand(0); // Legalize the chain. 2414 SDValue Size = Op.getOperand(1); // Legalize the size. 2415 EVT VT = Size->getValueType(0); 2416 SDLoc dl(Op); 2417 2418 unsigned SPReg = SP::O6; 2419 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 2420 SDValue NewSP = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 2421 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 2422 2423 // The resultant pointer is actually 16 words from the bottom of the stack, 2424 // to provide a register spill area. 2425 unsigned regSpillArea = Subtarget->is64Bit() ? 128 : 96; 2426 regSpillArea += Subtarget->getStackPointerBias(); 2427 2428 SDValue NewVal = DAG.getNode(ISD::ADD, dl, VT, NewSP, 2429 DAG.getConstant(regSpillArea, VT)); 2430 SDValue Ops[2] = { NewVal, Chain }; 2431 return DAG.getMergeValues(Ops, 2, dl); 2432} 2433 2434 2435static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { 2436 SDLoc dl(Op); 2437 SDValue Chain = DAG.getNode(SPISD::FLUSHW, 2438 dl, MVT::Other, DAG.getEntryNode()); 2439 return Chain; 2440} 2441 2442static SDValue getFRAMEADDR(uint64_t depth, SDValue Op, SelectionDAG &DAG, 2443 const SparcSubtarget *Subtarget) { 2444 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 2445 MFI->setFrameAddressIsTaken(true); 2446 2447 EVT VT = Op.getValueType(); 2448 SDLoc dl(Op); 2449 unsigned FrameReg = SP::I6; 2450 unsigned stackBias = Subtarget->getStackPointerBias(); 2451 2452 SDValue FrameAddr; 2453 2454 if (depth == 0) { 2455 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 2456 if (Subtarget->is64Bit()) 2457 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, 2458 DAG.getIntPtrConstant(stackBias)); 2459 return FrameAddr; 2460 } 2461 2462 // flush first to make sure the windowed registers' values are in stack 2463 SDValue Chain = getFLUSHW(Op, DAG); 2464 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); 2465 2466 unsigned Offset = (Subtarget->is64Bit()) ? (stackBias + 112) : 56; 2467 2468 while (depth--) { 2469 SDValue Ptr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, 2470 DAG.getIntPtrConstant(Offset)); 2471 FrameAddr = DAG.getLoad(VT, dl, Chain, Ptr, MachinePointerInfo(), 2472 false, false, false, 0); 2473 } 2474 if (Subtarget->is64Bit()) 2475 FrameAddr = DAG.getNode(ISD::ADD, dl, VT, FrameAddr, 2476 DAG.getIntPtrConstant(stackBias)); 2477 return FrameAddr; 2478} 2479 2480 2481static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG, 2482 const SparcSubtarget *Subtarget) { 2483 2484 uint64_t depth = Op.getConstantOperandVal(0); 2485 2486 return getFRAMEADDR(depth, Op, DAG, Subtarget); 2487 2488} 2489 2490static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG, 2491 const SparcTargetLowering &TLI, 2492 const SparcSubtarget *Subtarget) { 2493 MachineFunction &MF = DAG.getMachineFunction(); 2494 MachineFrameInfo *MFI = MF.getFrameInfo(); 2495 MFI->setReturnAddressIsTaken(true); 2496 2497 if (TLI.verifyReturnAddressArgumentIsConstant(Op, DAG)) 2498 return SDValue(); 2499 2500 EVT VT = Op.getValueType(); 2501 SDLoc dl(Op); 2502 uint64_t depth = Op.getConstantOperandVal(0); 2503 2504 SDValue RetAddr; 2505 if (depth == 0) { 2506 unsigned RetReg = MF.addLiveIn(SP::I7, 2507 TLI.getRegClassFor(TLI.getPointerTy())); 2508 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); 2509 return RetAddr; 2510 } 2511 2512 // Need frame address to find return address of the caller. 2513 SDValue FrameAddr = getFRAMEADDR(depth - 1, Op, DAG, Subtarget); 2514 2515 unsigned Offset = (Subtarget->is64Bit()) ? 120 : 60; 2516 SDValue Ptr = DAG.getNode(ISD::ADD, 2517 dl, VT, 2518 FrameAddr, 2519 DAG.getIntPtrConstant(Offset)); 2520 RetAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), Ptr, 2521 MachinePointerInfo(), false, false, false, 0); 2522 2523 return RetAddr; 2524} 2525 2526static SDValue LowerF64Op(SDValue Op, SelectionDAG &DAG, unsigned opcode) 2527{ 2528 SDLoc dl(Op); 2529 2530 assert(Op.getValueType() == MVT::f64 && "LowerF64Op called on non-double!"); 2531 assert(opcode == ISD::FNEG || opcode == ISD::FABS); 2532 2533 // Lower fneg/fabs on f64 to fneg/fabs on f32. 2534 // fneg f64 => fneg f32:sub_even, fmov f32:sub_odd. 2535 // fabs f64 => fabs f32:sub_even, fmov f32:sub_odd. 2536 2537 SDValue SrcReg64 = Op.getOperand(0); 2538 SDValue Hi32 = DAG.getTargetExtractSubreg(SP::sub_even, dl, MVT::f32, 2539 SrcReg64); 2540 SDValue Lo32 = DAG.getTargetExtractSubreg(SP::sub_odd, dl, MVT::f32, 2541 SrcReg64); 2542 2543 Hi32 = DAG.getNode(opcode, dl, MVT::f32, Hi32); 2544 2545 SDValue DstReg64 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, 2546 dl, MVT::f64), 0); 2547 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_even, dl, MVT::f64, 2548 DstReg64, Hi32); 2549 DstReg64 = DAG.getTargetInsertSubreg(SP::sub_odd, dl, MVT::f64, 2550 DstReg64, Lo32); 2551 return DstReg64; 2552} 2553 2554// Lower a f128 load into two f64 loads. 2555static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG) 2556{ 2557 SDLoc dl(Op); 2558 LoadSDNode *LdNode = dyn_cast<LoadSDNode>(Op.getNode()); 2559 assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF 2560 && "Unexpected node type"); 2561 2562 unsigned alignment = LdNode->getAlignment(); 2563 if (alignment > 8) 2564 alignment = 8; 2565 2566 SDValue Hi64 = DAG.getLoad(MVT::f64, 2567 dl, 2568 LdNode->getChain(), 2569 LdNode->getBasePtr(), 2570 LdNode->getPointerInfo(), 2571 false, false, false, alignment); 2572 EVT addrVT = LdNode->getBasePtr().getValueType(); 2573 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, 2574 LdNode->getBasePtr(), 2575 DAG.getConstant(8, addrVT)); 2576 SDValue Lo64 = DAG.getLoad(MVT::f64, 2577 dl, 2578 LdNode->getChain(), 2579 LoPtr, 2580 LdNode->getPointerInfo(), 2581 false, false, false, alignment); 2582 2583 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); 2584 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); 2585 2586 SDNode *InFP128 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, 2587 dl, MVT::f128); 2588 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, 2589 MVT::f128, 2590 SDValue(InFP128, 0), 2591 Hi64, 2592 SubRegEven); 2593 InFP128 = DAG.getMachineNode(TargetOpcode::INSERT_SUBREG, dl, 2594 MVT::f128, 2595 SDValue(InFP128, 0), 2596 Lo64, 2597 SubRegOdd); 2598 SDValue OutChains[2] = { SDValue(Hi64.getNode(), 1), 2599 SDValue(Lo64.getNode(), 1) }; 2600 SDValue OutChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2601 &OutChains[0], 2); 2602 SDValue Ops[2] = {SDValue(InFP128,0), OutChain}; 2603 return DAG.getMergeValues(Ops, 2, dl); 2604} 2605 2606// Lower a f128 store into two f64 stores. 2607static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) { 2608 SDLoc dl(Op); 2609 StoreSDNode *StNode = dyn_cast<StoreSDNode>(Op.getNode()); 2610 assert(StNode && StNode->getOffset().getOpcode() == ISD::UNDEF 2611 && "Unexpected node type"); 2612 SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32); 2613 SDValue SubRegOdd = DAG.getTargetConstant(SP::sub_odd64, MVT::i32); 2614 2615 SDNode *Hi64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, 2616 dl, 2617 MVT::f64, 2618 StNode->getValue(), 2619 SubRegEven); 2620 SDNode *Lo64 = DAG.getMachineNode(TargetOpcode::EXTRACT_SUBREG, 2621 dl, 2622 MVT::f64, 2623 StNode->getValue(), 2624 SubRegOdd); 2625 2626 unsigned alignment = StNode->getAlignment(); 2627 if (alignment > 8) 2628 alignment = 8; 2629 2630 SDValue OutChains[2]; 2631 OutChains[0] = DAG.getStore(StNode->getChain(), 2632 dl, 2633 SDValue(Hi64, 0), 2634 StNode->getBasePtr(), 2635 MachinePointerInfo(), 2636 false, false, alignment); 2637 EVT addrVT = StNode->getBasePtr().getValueType(); 2638 SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT, 2639 StNode->getBasePtr(), 2640 DAG.getConstant(8, addrVT)); 2641 OutChains[1] = DAG.getStore(StNode->getChain(), 2642 dl, 2643 SDValue(Lo64, 0), 2644 LoPtr, 2645 MachinePointerInfo(), 2646 false, false, alignment); 2647 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2648 &OutChains[0], 2); 2649} 2650 2651static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) { 2652 assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) 2653 && "invalid opcode"); 2654 2655 if (Op.getValueType() == MVT::f64) 2656 return LowerF64Op(Op, DAG, Op.getOpcode()); 2657 if (Op.getValueType() != MVT::f128) 2658 return Op; 2659 2660 // Lower fabs/fneg on f128 to fabs/fneg on f64 2661 // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64 2662 2663 SDLoc dl(Op); 2664 SDValue SrcReg128 = Op.getOperand(0); 2665 SDValue Hi64 = DAG.getTargetExtractSubreg(SP::sub_even64, dl, MVT::f64, 2666 SrcReg128); 2667 SDValue Lo64 = DAG.getTargetExtractSubreg(SP::sub_odd64, dl, MVT::f64, 2668 SrcReg128); 2669 if (isV9) 2670 Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64); 2671 else 2672 Hi64 = LowerF64Op(Hi64, DAG, Op.getOpcode()); 2673 2674 SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, 2675 dl, MVT::f128), 0); 2676 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_even64, dl, MVT::f128, 2677 DstReg128, Hi64); 2678 DstReg128 = DAG.getTargetInsertSubreg(SP::sub_odd64, dl, MVT::f128, 2679 DstReg128, Lo64); 2680 return DstReg128; 2681} 2682 2683static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 2684 2685 if (Op.getValueType() != MVT::i64) 2686 return Op; 2687 2688 SDLoc dl(Op); 2689 SDValue Src1 = Op.getOperand(0); 2690 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1); 2691 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1, 2692 DAG.getConstant(32, MVT::i64)); 2693 Src1Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1Hi); 2694 2695 SDValue Src2 = Op.getOperand(1); 2696 SDValue Src2Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2); 2697 SDValue Src2Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src2, 2698 DAG.getConstant(32, MVT::i64)); 2699 Src2Hi = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src2Hi); 2700 2701 2702 bool hasChain = false; 2703 unsigned hiOpc = Op.getOpcode(); 2704 switch (Op.getOpcode()) { 2705 default: llvm_unreachable("Invalid opcode"); 2706 case ISD::ADDC: hiOpc = ISD::ADDE; break; 2707 case ISD::ADDE: hasChain = true; break; 2708 case ISD::SUBC: hiOpc = ISD::SUBE; break; 2709 case ISD::SUBE: hasChain = true; break; 2710 } 2711 SDValue Lo; 2712 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Glue); 2713 if (hasChain) { 2714 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo, 2715 Op.getOperand(2)); 2716 } else { 2717 Lo = DAG.getNode(Op.getOpcode(), dl, VTs, Src1Lo, Src2Lo); 2718 } 2719 SDValue Hi = DAG.getNode(hiOpc, dl, VTs, Src1Hi, Src2Hi, Lo.getValue(1)); 2720 SDValue Carry = Hi.getValue(1); 2721 2722 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Lo); 2723 Hi = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i64, Hi); 2724 Hi = DAG.getNode(ISD::SHL, dl, MVT::i64, Hi, 2725 DAG.getConstant(32, MVT::i64)); 2726 2727 SDValue Dst = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, Lo); 2728 SDValue Ops[2] = { Dst, Carry }; 2729 return DAG.getMergeValues(Ops, 2, dl); 2730} 2731 2732// Custom lower UMULO/SMULO for SPARC. This code is similar to ExpandNode() 2733// in LegalizeDAG.cpp except the order of arguments to the library function. 2734static SDValue LowerUMULO_SMULO(SDValue Op, SelectionDAG &DAG, 2735 const SparcTargetLowering &TLI) 2736{ 2737 unsigned opcode = Op.getOpcode(); 2738 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); 2739 2740 bool isSigned = (opcode == ISD::SMULO); 2741 EVT VT = MVT::i64; 2742 EVT WideVT = MVT::i128; 2743 SDLoc dl(Op); 2744 SDValue LHS = Op.getOperand(0); 2745 2746 if (LHS.getValueType() != VT) 2747 return Op; 2748 2749 SDValue ShiftAmt = DAG.getConstant(63, VT); 2750 2751 SDValue RHS = Op.getOperand(1); 2752 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, LHS, ShiftAmt); 2753 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, MVT::i64, RHS, ShiftAmt); 2754 SDValue Args[] = { HiLHS, LHS, HiRHS, RHS }; 2755 2756 SDValue MulResult = TLI.makeLibCall(DAG, 2757 RTLIB::MUL_I128, WideVT, 2758 Args, 4, isSigned, dl).first; 2759 SDValue BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, 2760 MulResult, DAG.getIntPtrConstant(0)); 2761 SDValue TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, 2762 MulResult, DAG.getIntPtrConstant(1)); 2763 if (isSigned) { 2764 SDValue Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, ShiftAmt); 2765 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, Tmp1, ISD::SETNE); 2766 } else { 2767 TopHalf = DAG.getSetCC(dl, MVT::i32, TopHalf, DAG.getConstant(0, VT), 2768 ISD::SETNE); 2769 } 2770 // MulResult is a node with an illegal type. Because such things are not 2771 // generally permitted during this phase of legalization, delete the 2772 // node. The above EXTRACT_ELEMENT nodes should have been folded. 2773 DAG.DeleteNode(MulResult.getNode()); 2774 2775 SDValue Ops[2] = { BottomHalf, TopHalf } ; 2776 return DAG.getMergeValues(Ops, 2, dl); 2777} 2778 2779static SDValue LowerATOMIC_LOAD_STORE(SDValue Op, SelectionDAG &DAG) { 2780 // Monotonic load/stores are legal. 2781 if (cast<AtomicSDNode>(Op)->getOrdering() <= Monotonic) 2782 return Op; 2783 2784 // Otherwise, expand with a fence. 2785 return SDValue(); 2786} 2787 2788 2789SDValue SparcTargetLowering:: 2790LowerOperation(SDValue Op, SelectionDAG &DAG) const { 2791 2792 bool hasHardQuad = Subtarget->hasHardQuad(); 2793 bool isV9 = Subtarget->isV9(); 2794 2795 switch (Op.getOpcode()) { 2796 default: llvm_unreachable("Should not custom lower this!"); 2797 2798 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG, *this, 2799 Subtarget); 2800 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG, 2801 Subtarget); 2802 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 2803 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 2804 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 2805 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 2806 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG, *this, 2807 hasHardQuad); 2808 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG, *this, 2809 hasHardQuad); 2810 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG, *this, 2811 hasHardQuad); 2812 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG, *this, 2813 hasHardQuad); 2814 case ISD::BR_CC: return LowerBR_CC(Op, DAG, *this, 2815 hasHardQuad); 2816 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG, *this, 2817 hasHardQuad); 2818 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 2819 case ISD::VAARG: return LowerVAARG(Op, DAG); 2820 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG, 2821 Subtarget); 2822 2823 case ISD::LOAD: return LowerF128Load(Op, DAG); 2824 case ISD::STORE: return LowerF128Store(Op, DAG); 2825 case ISD::FADD: return LowerF128Op(Op, DAG, 2826 getLibcallName(RTLIB::ADD_F128), 2); 2827 case ISD::FSUB: return LowerF128Op(Op, DAG, 2828 getLibcallName(RTLIB::SUB_F128), 2); 2829 case ISD::FMUL: return LowerF128Op(Op, DAG, 2830 getLibcallName(RTLIB::MUL_F128), 2); 2831 case ISD::FDIV: return LowerF128Op(Op, DAG, 2832 getLibcallName(RTLIB::DIV_F128), 2); 2833 case ISD::FSQRT: return LowerF128Op(Op, DAG, 2834 getLibcallName(RTLIB::SQRT_F128),1); 2835 case ISD::FABS: 2836 case ISD::FNEG: return LowerFNEGorFABS(Op, DAG, isV9); 2837 case ISD::FP_EXTEND: return LowerF128_FPEXTEND(Op, DAG, *this); 2838 case ISD::FP_ROUND: return LowerF128_FPROUND(Op, DAG, *this); 2839 case ISD::ADDC: 2840 case ISD::ADDE: 2841 case ISD::SUBC: 2842 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 2843 case ISD::UMULO: 2844 case ISD::SMULO: return LowerUMULO_SMULO(Op, DAG, *this); 2845 case ISD::ATOMIC_LOAD: 2846 case ISD::ATOMIC_STORE: return LowerATOMIC_LOAD_STORE(Op, DAG); 2847 } 2848} 2849 2850MachineBasicBlock * 2851SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 2852 MachineBasicBlock *BB) const { 2853 switch (MI->getOpcode()) { 2854 default: llvm_unreachable("Unknown SELECT_CC!"); 2855 case SP::SELECT_CC_Int_ICC: 2856 case SP::SELECT_CC_FP_ICC: 2857 case SP::SELECT_CC_DFP_ICC: 2858 case SP::SELECT_CC_QFP_ICC: 2859 return expandSelectCC(MI, BB, SP::BCOND); 2860 case SP::SELECT_CC_Int_FCC: 2861 case SP::SELECT_CC_FP_FCC: 2862 case SP::SELECT_CC_DFP_FCC: 2863 case SP::SELECT_CC_QFP_FCC: 2864 return expandSelectCC(MI, BB, SP::FBCOND); 2865 2866 case SP::ATOMIC_LOAD_ADD_32: 2867 return expandAtomicRMW(MI, BB, SP::ADDrr); 2868 case SP::ATOMIC_LOAD_ADD_64: 2869 return expandAtomicRMW(MI, BB, SP::ADDXrr); 2870 case SP::ATOMIC_LOAD_SUB_32: 2871 return expandAtomicRMW(MI, BB, SP::SUBrr); 2872 case SP::ATOMIC_LOAD_SUB_64: 2873 return expandAtomicRMW(MI, BB, SP::SUBXrr); 2874 case SP::ATOMIC_LOAD_AND_32: 2875 return expandAtomicRMW(MI, BB, SP::ANDrr); 2876 case SP::ATOMIC_LOAD_AND_64: 2877 return expandAtomicRMW(MI, BB, SP::ANDXrr); 2878 case SP::ATOMIC_LOAD_OR_32: 2879 return expandAtomicRMW(MI, BB, SP::ORrr); 2880 case SP::ATOMIC_LOAD_OR_64: 2881 return expandAtomicRMW(MI, BB, SP::ORXrr); 2882 case SP::ATOMIC_LOAD_XOR_32: 2883 return expandAtomicRMW(MI, BB, SP::XORrr); 2884 case SP::ATOMIC_LOAD_XOR_64: 2885 return expandAtomicRMW(MI, BB, SP::XORXrr); 2886 case SP::ATOMIC_LOAD_NAND_32: 2887 return expandAtomicRMW(MI, BB, SP::ANDrr); 2888 case SP::ATOMIC_LOAD_NAND_64: 2889 return expandAtomicRMW(MI, BB, SP::ANDXrr); 2890 2891 case SP::ATOMIC_SWAP_64: 2892 return expandAtomicRMW(MI, BB, 0); 2893 2894 case SP::ATOMIC_LOAD_MAX_32: 2895 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_G); 2896 case SP::ATOMIC_LOAD_MAX_64: 2897 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_G); 2898 case SP::ATOMIC_LOAD_MIN_32: 2899 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LE); 2900 case SP::ATOMIC_LOAD_MIN_64: 2901 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LE); 2902 case SP::ATOMIC_LOAD_UMAX_32: 2903 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_GU); 2904 case SP::ATOMIC_LOAD_UMAX_64: 2905 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_GU); 2906 case SP::ATOMIC_LOAD_UMIN_32: 2907 return expandAtomicRMW(MI, BB, SP::MOVICCrr, SPCC::ICC_LEU); 2908 case SP::ATOMIC_LOAD_UMIN_64: 2909 return expandAtomicRMW(MI, BB, SP::MOVXCCrr, SPCC::ICC_LEU); 2910 } 2911} 2912 2913MachineBasicBlock* 2914SparcTargetLowering::expandSelectCC(MachineInstr *MI, 2915 MachineBasicBlock *BB, 2916 unsigned BROpcode) const { 2917 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 2918 DebugLoc dl = MI->getDebugLoc(); 2919 unsigned CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 2920 2921 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 2922 // control-flow pattern. The incoming instruction knows the destination vreg 2923 // to set, the condition code register to branch on, the true/false values to 2924 // select between, and a branch opcode to use. 2925 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2926 MachineFunction::iterator It = BB; 2927 ++It; 2928 2929 // thisMBB: 2930 // ... 2931 // TrueVal = ... 2932 // [f]bCC copy1MBB 2933 // fallthrough --> copy0MBB 2934 MachineBasicBlock *thisMBB = BB; 2935 MachineFunction *F = BB->getParent(); 2936 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 2937 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 2938 F->insert(It, copy0MBB); 2939 F->insert(It, sinkMBB); 2940 2941 // Transfer the remainder of BB and its successor edges to sinkMBB. 2942 sinkMBB->splice(sinkMBB->begin(), BB, 2943 std::next(MachineBasicBlock::iterator(MI)), 2944 BB->end()); 2945 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 2946 2947 // Add the true and fallthrough blocks as its successors. 2948 BB->addSuccessor(copy0MBB); 2949 BB->addSuccessor(sinkMBB); 2950 2951 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 2952 2953 // copy0MBB: 2954 // %FalseValue = ... 2955 // # fallthrough to sinkMBB 2956 BB = copy0MBB; 2957 2958 // Update machine-CFG edges 2959 BB->addSuccessor(sinkMBB); 2960 2961 // sinkMBB: 2962 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 2963 // ... 2964 BB = sinkMBB; 2965 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 2966 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 2967 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 2968 2969 MI->eraseFromParent(); // The pseudo instruction is gone now. 2970 return BB; 2971} 2972 2973MachineBasicBlock* 2974SparcTargetLowering::expandAtomicRMW(MachineInstr *MI, 2975 MachineBasicBlock *MBB, 2976 unsigned Opcode, 2977 unsigned CondCode) const { 2978 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 2979 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 2980 DebugLoc DL = MI->getDebugLoc(); 2981 2982 // MI is an atomic read-modify-write instruction of the form: 2983 // 2984 // rd = atomicrmw<op> addr, rs2 2985 // 2986 // All three operands are registers. 2987 unsigned DestReg = MI->getOperand(0).getReg(); 2988 unsigned AddrReg = MI->getOperand(1).getReg(); 2989 unsigned Rs2Reg = MI->getOperand(2).getReg(); 2990 2991 // SelectionDAG has already inserted memory barriers before and after MI, so 2992 // we simply have to implement the operatiuon in terms of compare-and-swap. 2993 // 2994 // %val0 = load %addr 2995 // loop: 2996 // %val = phi %val0, %dest 2997 // %upd = op %val, %rs2 2998 // %dest = cas %addr, %val, %upd 2999 // cmp %val, %dest 3000 // bne loop 3001 // done: 3002 // 3003 bool is64Bit = SP::I64RegsRegClass.hasSubClassEq(MRI.getRegClass(DestReg)); 3004 const TargetRegisterClass *ValueRC = 3005 is64Bit ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; 3006 unsigned Val0Reg = MRI.createVirtualRegister(ValueRC); 3007 3008 BuildMI(*MBB, MI, DL, TII.get(is64Bit ? SP::LDXri : SP::LDri), Val0Reg) 3009 .addReg(AddrReg).addImm(0); 3010 3011 // Split the basic block MBB before MI and insert the loop block in the hole. 3012 MachineFunction::iterator MFI = MBB; 3013 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 3014 MachineFunction *MF = MBB->getParent(); 3015 MachineBasicBlock *LoopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3016 MachineBasicBlock *DoneMBB = MF->CreateMachineBasicBlock(LLVM_BB); 3017 ++MFI; 3018 MF->insert(MFI, LoopMBB); 3019 MF->insert(MFI, DoneMBB); 3020 3021 // Move MI and following instructions to DoneMBB. 3022 DoneMBB->splice(DoneMBB->begin(), MBB, MI, MBB->end()); 3023 DoneMBB->transferSuccessorsAndUpdatePHIs(MBB); 3024 3025 // Connect the CFG again. 3026 MBB->addSuccessor(LoopMBB); 3027 LoopMBB->addSuccessor(LoopMBB); 3028 LoopMBB->addSuccessor(DoneMBB); 3029 3030 // Build the loop block. 3031 unsigned ValReg = MRI.createVirtualRegister(ValueRC); 3032 // Opcode == 0 means try to write Rs2Reg directly (ATOMIC_SWAP). 3033 unsigned UpdReg = (Opcode ? MRI.createVirtualRegister(ValueRC) : Rs2Reg); 3034 3035 BuildMI(LoopMBB, DL, TII.get(SP::PHI), ValReg) 3036 .addReg(Val0Reg).addMBB(MBB) 3037 .addReg(DestReg).addMBB(LoopMBB); 3038 3039 if (CondCode) { 3040 // This is one of the min/max operations. We need a CMPrr followed by a 3041 // MOVXCC/MOVICC. 3042 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(Rs2Reg); 3043 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg) 3044 .addReg(ValReg).addReg(Rs2Reg).addImm(CondCode); 3045 } else if (Opcode) { 3046 BuildMI(LoopMBB, DL, TII.get(Opcode), UpdReg) 3047 .addReg(ValReg).addReg(Rs2Reg); 3048 } 3049 3050 if (MI->getOpcode() == SP::ATOMIC_LOAD_NAND_32 || 3051 MI->getOpcode() == SP::ATOMIC_LOAD_NAND_64) { 3052 unsigned TmpReg = UpdReg; 3053 UpdReg = MRI.createVirtualRegister(ValueRC); 3054 BuildMI(LoopMBB, DL, TII.get(SP::XORri), UpdReg).addReg(TmpReg).addImm(-1); 3055 } 3056 3057 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::CASXrr : SP::CASrr), DestReg) 3058 .addReg(AddrReg).addReg(ValReg).addReg(UpdReg) 3059 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 3060 BuildMI(LoopMBB, DL, TII.get(SP::CMPrr)).addReg(ValReg).addReg(DestReg); 3061 BuildMI(LoopMBB, DL, TII.get(is64Bit ? SP::BPXCC : SP::BCOND)) 3062 .addMBB(LoopMBB).addImm(SPCC::ICC_NE); 3063 3064 MI->eraseFromParent(); 3065 return DoneMBB; 3066} 3067 3068//===----------------------------------------------------------------------===// 3069// Sparc Inline Assembly Support 3070//===----------------------------------------------------------------------===// 3071 3072/// getConstraintType - Given a constraint letter, return the type of 3073/// constraint it is for this target. 3074SparcTargetLowering::ConstraintType 3075SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 3076 if (Constraint.size() == 1) { 3077 switch (Constraint[0]) { 3078 default: break; 3079 case 'r': return C_RegisterClass; 3080 case 'I': // SIMM13 3081 return C_Other; 3082 } 3083 } 3084 3085 return TargetLowering::getConstraintType(Constraint); 3086} 3087 3088TargetLowering::ConstraintWeight SparcTargetLowering:: 3089getSingleConstraintMatchWeight(AsmOperandInfo &info, 3090 const char *constraint) const { 3091 ConstraintWeight weight = CW_Invalid; 3092 Value *CallOperandVal = info.CallOperandVal; 3093 // If we don't have a value, we can't do a match, 3094 // but allow it at the lowest weight. 3095 if (CallOperandVal == NULL) 3096 return CW_Default; 3097 3098 // Look at the constraint type. 3099 switch (*constraint) { 3100 default: 3101 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 3102 break; 3103 case 'I': // SIMM13 3104 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 3105 if (isInt<13>(C->getSExtValue())) 3106 weight = CW_Constant; 3107 } 3108 break; 3109 } 3110 return weight; 3111} 3112 3113/// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 3114/// vector. If it is invalid, don't add anything to Ops. 3115void SparcTargetLowering:: 3116LowerAsmOperandForConstraint(SDValue Op, 3117 std::string &Constraint, 3118 std::vector<SDValue> &Ops, 3119 SelectionDAG &DAG) const { 3120 SDValue Result(0, 0); 3121 3122 // Only support length 1 constraints for now. 3123 if (Constraint.length() > 1) 3124 return; 3125 3126 char ConstraintLetter = Constraint[0]; 3127 switch (ConstraintLetter) { 3128 default: break; 3129 case 'I': 3130 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 3131 if (isInt<13>(C->getSExtValue())) { 3132 Result = DAG.getTargetConstant(C->getSExtValue(), Op.getValueType()); 3133 break; 3134 } 3135 return; 3136 } 3137 } 3138 3139 if (Result.getNode()) { 3140 Ops.push_back(Result); 3141 return; 3142 } 3143 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 3144} 3145 3146std::pair<unsigned, const TargetRegisterClass*> 3147SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 3148 MVT VT) const { 3149 if (Constraint.size() == 1) { 3150 switch (Constraint[0]) { 3151 case 'r': 3152 return std::make_pair(0U, &SP::IntRegsRegClass); 3153 } 3154 } else if (!Constraint.empty() && Constraint.size() <= 5 3155 && Constraint[0] == '{' && *(Constraint.end()-1) == '}') { 3156 // constraint = '{r<d>}' 3157 // Remove the braces from around the name. 3158 StringRef name(Constraint.data()+1, Constraint.size()-2); 3159 // Handle register aliases: 3160 // r0-r7 -> g0-g7 3161 // r8-r15 -> o0-o7 3162 // r16-r23 -> l0-l7 3163 // r24-r31 -> i0-i7 3164 uint64_t intVal = 0; 3165 if (name.substr(0, 1).equals("r") 3166 && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) { 3167 const char regTypes[] = { 'g', 'o', 'l', 'i' }; 3168 char regType = regTypes[intVal/8]; 3169 char regIdx = '0' + (intVal % 8); 3170 char tmp[] = { '{', regType, regIdx, '}', 0 }; 3171 std::string newConstraint = std::string(tmp); 3172 return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT); 3173 } 3174 } 3175 3176 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 3177} 3178 3179bool 3180SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 3181 // The Sparc target isn't yet aware of offsets. 3182 return false; 3183} 3184 3185void SparcTargetLowering::ReplaceNodeResults(SDNode *N, 3186 SmallVectorImpl<SDValue>& Results, 3187 SelectionDAG &DAG) const { 3188 3189 SDLoc dl(N); 3190 3191 RTLIB::Libcall libCall = RTLIB::UNKNOWN_LIBCALL; 3192 3193 switch (N->getOpcode()) { 3194 default: 3195 llvm_unreachable("Do not know how to custom type legalize this operation!"); 3196 3197 case ISD::FP_TO_SINT: 3198 case ISD::FP_TO_UINT: 3199 // Custom lower only if it involves f128 or i64. 3200 if (N->getOperand(0).getValueType() != MVT::f128 3201 || N->getValueType(0) != MVT::i64) 3202 return; 3203 libCall = ((N->getOpcode() == ISD::FP_TO_SINT) 3204 ? RTLIB::FPTOSINT_F128_I64 3205 : RTLIB::FPTOUINT_F128_I64); 3206 3207 Results.push_back(LowerF128Op(SDValue(N, 0), 3208 DAG, 3209 getLibcallName(libCall), 3210 1)); 3211 return; 3212 3213 case ISD::SINT_TO_FP: 3214 case ISD::UINT_TO_FP: 3215 // Custom lower only if it involves f128 or i64. 3216 if (N->getValueType(0) != MVT::f128 3217 || N->getOperand(0).getValueType() != MVT::i64) 3218 return; 3219 3220 libCall = ((N->getOpcode() == ISD::SINT_TO_FP) 3221 ? RTLIB::SINTTOFP_I64_F128 3222 : RTLIB::UINTTOFP_I64_F128); 3223 3224 Results.push_back(LowerF128Op(SDValue(N, 0), 3225 DAG, 3226 getLibcallName(libCall), 3227 1)); 3228 return; 3229 } 3230} 3231