SparcISelLowering.cpp revision 7a2bdde0a0eebcd2125055e0eacaca040f0b766c
1 2//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 3// 4// The LLVM Compiler Infrastructure 5// 6// This file is distributed under the University of Illinois Open Source 7// License. See LICENSE.TXT for details. 8// 9//===----------------------------------------------------------------------===// 10// 11// This file implements the interfaces that Sparc uses to lower LLVM code into a 12// selection DAG. 13// 14//===----------------------------------------------------------------------===// 15 16#include "SparcISelLowering.h" 17#include "SparcTargetMachine.h" 18#include "SparcMachineFunctionInfo.h" 19#include "llvm/DerivedTypes.h" 20#include "llvm/Function.h" 21#include "llvm/Module.h" 22#include "llvm/CodeGen/CallingConvLower.h" 23#include "llvm/CodeGen/MachineFrameInfo.h" 24#include "llvm/CodeGen/MachineFunction.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineRegisterInfo.h" 27#include "llvm/CodeGen/SelectionDAG.h" 28#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 29#include "llvm/ADT/VectorExtras.h" 30#include "llvm/Support/ErrorHandling.h" 31using namespace llvm; 32 33 34//===----------------------------------------------------------------------===// 35// Calling Convention Implementation 36//===----------------------------------------------------------------------===// 37 38static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, 39 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 40 ISD::ArgFlagsTy &ArgFlags, CCState &State) 41{ 42 assert (ArgFlags.isSRet()); 43 44 //Assign SRet argument 45 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 46 0, 47 LocVT, LocInfo)); 48 return true; 49} 50 51static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, 52 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 53 ISD::ArgFlagsTy &ArgFlags, CCState &State) 54{ 55 static const unsigned RegList[] = { 56 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 57 }; 58 //Try to get first reg 59 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 60 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 61 } else { 62 //Assign whole thing in stack 63 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 64 State.AllocateStack(8,4), 65 LocVT, LocInfo)); 66 return true; 67 } 68 69 //Try to get second reg 70 if (unsigned Reg = State.AllocateReg(RegList, 6)) 71 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 72 else 73 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 74 State.AllocateStack(4,4), 75 LocVT, LocInfo)); 76 return true; 77} 78 79#include "SparcGenCallingConv.inc" 80 81SDValue 82SparcTargetLowering::LowerReturn(SDValue Chain, 83 CallingConv::ID CallConv, bool isVarArg, 84 const SmallVectorImpl<ISD::OutputArg> &Outs, 85 const SmallVectorImpl<SDValue> &OutVals, 86 DebugLoc dl, SelectionDAG &DAG) const { 87 88 MachineFunction &MF = DAG.getMachineFunction(); 89 90 // CCValAssign - represent the assignment of the return value to locations. 91 SmallVector<CCValAssign, 16> RVLocs; 92 93 // CCState - Info about the registers and stack slot. 94 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), 95 RVLocs, *DAG.getContext()); 96 97 // Analize return values. 98 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 99 100 // If this is the first return lowered for this function, add the regs to the 101 // liveout set for the function. 102 if (MF.getRegInfo().liveout_empty()) { 103 for (unsigned i = 0; i != RVLocs.size(); ++i) 104 if (RVLocs[i].isRegLoc()) 105 MF.getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 106 } 107 108 SDValue Flag; 109 110 // Copy the result values into the output registers. 111 for (unsigned i = 0; i != RVLocs.size(); ++i) { 112 CCValAssign &VA = RVLocs[i]; 113 assert(VA.isRegLoc() && "Can only return in registers!"); 114 115 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 116 OutVals[i], Flag); 117 118 // Guarantee that all emitted copies are stuck together with flags. 119 Flag = Chain.getValue(1); 120 } 121 122 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot 123 // If the function returns a struct, copy the SRetReturnReg to I0 124 if (MF.getFunction()->hasStructRetAttr()) { 125 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 126 unsigned Reg = SFI->getSRetReturnReg(); 127 if (!Reg) 128 llvm_unreachable("sret virtual register not created in the entry block"); 129 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 130 Chain = DAG.getCopyToReg(Chain, dl, SP::I0, Val, Flag); 131 Flag = Chain.getValue(1); 132 if (MF.getRegInfo().liveout_empty()) 133 MF.getRegInfo().addLiveOut(SP::I0); 134 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp 135 } 136 137 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32); 138 139 if (Flag.getNode()) 140 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, 141 RetAddrOffsetNode, Flag); 142 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, 143 RetAddrOffsetNode); 144} 145 146/// LowerFormalArguments - V8 uses a very simple ABI, where all values are 147/// passed in either one or two GPRs, including FP values. TODO: we should 148/// pass FP values in FP registers for fastcc functions. 149SDValue 150SparcTargetLowering::LowerFormalArguments(SDValue Chain, 151 CallingConv::ID CallConv, bool isVarArg, 152 const SmallVectorImpl<ISD::InputArg> 153 &Ins, 154 DebugLoc dl, SelectionDAG &DAG, 155 SmallVectorImpl<SDValue> &InVals) 156 const { 157 158 MachineFunction &MF = DAG.getMachineFunction(); 159 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 160 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 161 162 // Assign locations to all of the incoming arguments. 163 SmallVector<CCValAssign, 16> ArgLocs; 164 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), 165 ArgLocs, *DAG.getContext()); 166 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 167 168 const unsigned StackOffset = 92; 169 170 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 171 CCValAssign &VA = ArgLocs[i]; 172 173 if (i == 0 && Ins[i].Flags.isSRet()) { 174 //Get SRet from [%fp+64] 175 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); 176 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 177 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 178 MachinePointerInfo(), 179 false, false, 0); 180 InVals.push_back(Arg); 181 continue; 182 } 183 184 if (VA.isRegLoc()) { 185 EVT RegVT = VA.getLocVT(); 186 187 if (VA.needsCustom()) { 188 assert(VA.getLocVT() == MVT::f64); 189 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 190 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 191 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 192 193 assert(i+1 < e); 194 CCValAssign &NextVA = ArgLocs[++i]; 195 196 SDValue LoVal; 197 if (NextVA.isMemLoc()) { 198 int FrameIdx = MF.getFrameInfo()-> 199 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); 200 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 201 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 202 MachinePointerInfo(), 203 false, false, 0); 204 } else { 205 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), 206 &SP::IntRegsRegClass); 207 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); 208 } 209 SDValue WholeValue = 210 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 211 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 212 InVals.push_back(WholeValue); 213 continue; 214 } 215 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 216 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 217 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 218 if (VA.getLocVT() == MVT::f32) 219 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 220 else if (VA.getLocVT() != MVT::i32) { 221 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 222 DAG.getValueType(VA.getLocVT())); 223 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); 224 } 225 InVals.push_back(Arg); 226 continue; 227 } 228 229 assert(VA.isMemLoc()); 230 231 unsigned Offset = VA.getLocMemOffset()+StackOffset; 232 233 if (VA.needsCustom()) { 234 assert(VA.getValVT() == MVT::f64); 235 //If it is double-word aligned, just load. 236 if (Offset % 8 == 0) { 237 int FI = MF.getFrameInfo()->CreateFixedObject(8, 238 Offset, 239 true); 240 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 241 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 242 MachinePointerInfo(), 243 false,false, 0); 244 InVals.push_back(Load); 245 continue; 246 } 247 248 int FI = MF.getFrameInfo()->CreateFixedObject(4, 249 Offset, 250 true); 251 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 252 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 253 MachinePointerInfo(), 254 false, false, 0); 255 int FI2 = MF.getFrameInfo()->CreateFixedObject(4, 256 Offset+4, 257 true); 258 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy()); 259 260 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, 261 MachinePointerInfo(), 262 false, false, 0); 263 264 SDValue WholeValue = 265 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 266 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 267 InVals.push_back(WholeValue); 268 continue; 269 } 270 271 int FI = MF.getFrameInfo()->CreateFixedObject(4, 272 Offset, 273 true); 274 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 275 SDValue Load ; 276 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { 277 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 278 MachinePointerInfo(), 279 false, false, 0); 280 } else { 281 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 282 // Sparc is big endian, so add an offset based on the ObjectVT. 283 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); 284 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 285 DAG.getConstant(Offset, MVT::i32)); 286 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, 287 MachinePointerInfo(), 288 VA.getValVT(), false, false,0); 289 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); 290 } 291 InVals.push_back(Load); 292 } 293 294 if (MF.getFunction()->hasStructRetAttr()) { 295 //Copy the SRet Argument to SRetReturnReg 296 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 297 unsigned Reg = SFI->getSRetReturnReg(); 298 if (!Reg) { 299 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); 300 SFI->setSRetReturnReg(Reg); 301 } 302 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 303 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 304 } 305 306 // Store remaining ArgRegs to the stack if this is a varargs function. 307 if (isVarArg) { 308 static const unsigned ArgRegs[] = { 309 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 310 }; 311 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); 312 const unsigned *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; 313 unsigned ArgOffset = CCInfo.getNextStackOffset(); 314 if (NumAllocated == 6) 315 ArgOffset += StackOffset; 316 else { 317 assert(!ArgOffset); 318 ArgOffset = 68+4*NumAllocated; 319 } 320 321 // Remember the vararg offset for the va_start implementation. 322 FuncInfo->setVarArgsFrameOffset(ArgOffset); 323 324 std::vector<SDValue> OutChains; 325 326 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 327 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 328 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 329 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 330 331 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 332 true); 333 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 334 335 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, 336 MachinePointerInfo(), 337 false, false, 0)); 338 ArgOffset += 4; 339 } 340 341 if (!OutChains.empty()) { 342 OutChains.push_back(Chain); 343 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 344 &OutChains[0], OutChains.size()); 345 } 346 } 347 348 return Chain; 349} 350 351SDValue 352SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, 353 CallingConv::ID CallConv, bool isVarArg, 354 bool &isTailCall, 355 const SmallVectorImpl<ISD::OutputArg> &Outs, 356 const SmallVectorImpl<SDValue> &OutVals, 357 const SmallVectorImpl<ISD::InputArg> &Ins, 358 DebugLoc dl, SelectionDAG &DAG, 359 SmallVectorImpl<SDValue> &InVals) const { 360 // Sparc target does not yet support tail call optimization. 361 isTailCall = false; 362 363 // Analyze operands of the call, assigning locations to each operand. 364 SmallVector<CCValAssign, 16> ArgLocs; 365 CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs, 366 *DAG.getContext()); 367 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 368 369 // Get the size of the outgoing arguments stack space requirement. 370 unsigned ArgsSize = CCInfo.getNextStackOffset(); 371 372 // Keep stack frames 8-byte aligned. 373 ArgsSize = (ArgsSize+7) & ~7; 374 375 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 376 377 //Create local copies for byval args. 378 SmallVector<SDValue, 8> ByValArgs; 379 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 380 ISD::ArgFlagsTy Flags = Outs[i].Flags; 381 if (!Flags.isByVal()) 382 continue; 383 384 SDValue Arg = OutVals[i]; 385 unsigned Size = Flags.getByValSize(); 386 unsigned Align = Flags.getByValAlign(); 387 388 int FI = MFI->CreateStackObject(Size, Align, false); 389 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 390 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 391 392 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, 393 false, //isVolatile, 394 (Size <= 32), //AlwaysInline if size <= 32 395 MachinePointerInfo(), MachinePointerInfo()); 396 ByValArgs.push_back(FIPtr); 397 } 398 399 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 400 401 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 402 SmallVector<SDValue, 8> MemOpChains; 403 404 const unsigned StackOffset = 92; 405 bool hasStructRetAttr = false; 406 // Walk the register/memloc assignments, inserting copies/loads. 407 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size(); 408 i != e; 409 ++i, ++realArgIdx) { 410 CCValAssign &VA = ArgLocs[i]; 411 SDValue Arg = OutVals[realArgIdx]; 412 413 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 414 415 //Use local copy if it is a byval arg. 416 if (Flags.isByVal()) 417 Arg = ByValArgs[byvalArgIdx++]; 418 419 // Promote the value if needed. 420 switch (VA.getLocInfo()) { 421 default: llvm_unreachable("Unknown loc info!"); 422 case CCValAssign::Full: break; 423 case CCValAssign::SExt: 424 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 425 break; 426 case CCValAssign::ZExt: 427 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 428 break; 429 case CCValAssign::AExt: 430 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 431 break; 432 case CCValAssign::BCvt: 433 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 434 break; 435 } 436 437 if (Flags.isSRet()) { 438 assert(VA.needsCustom()); 439 // store SRet argument in %sp+64 440 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 441 SDValue PtrOff = DAG.getIntPtrConstant(64); 442 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 443 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 444 MachinePointerInfo(), 445 false, false, 0)); 446 hasStructRetAttr = true; 447 continue; 448 } 449 450 if (VA.needsCustom()) { 451 assert(VA.getLocVT() == MVT::f64); 452 453 if (VA.isMemLoc()) { 454 unsigned Offset = VA.getLocMemOffset() + StackOffset; 455 //if it is double-word aligned, just store. 456 if (Offset % 8 == 0) { 457 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 458 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 459 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 460 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 461 MachinePointerInfo(), 462 false, false, 0)); 463 continue; 464 } 465 } 466 467 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 468 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 469 Arg, StackPtr, MachinePointerInfo(), 470 false, false, 0); 471 // Sparc is big-endian, so the high part comes first. 472 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 473 MachinePointerInfo(), false, false, 0); 474 // Increment the pointer to the other half. 475 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 476 DAG.getIntPtrConstant(4)); 477 // Load the low part. 478 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 479 MachinePointerInfo(), false, false, 0); 480 481 if (VA.isRegLoc()) { 482 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); 483 assert(i+1 != e); 484 CCValAssign &NextVA = ArgLocs[++i]; 485 if (NextVA.isRegLoc()) { 486 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 487 } else { 488 //Store the low part in stack. 489 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; 490 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 491 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 492 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 493 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 494 MachinePointerInfo(), 495 false, false, 0)); 496 } 497 } else { 498 unsigned Offset = VA.getLocMemOffset() + StackOffset; 499 // Store the high part. 500 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 501 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 502 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 503 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, 504 MachinePointerInfo(), 505 false, false, 0)); 506 // Store the low part. 507 PtrOff = DAG.getIntPtrConstant(Offset+4); 508 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 509 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 510 MachinePointerInfo(), 511 false, false, 0)); 512 } 513 continue; 514 } 515 516 // Arguments that can be passed on register must be kept at 517 // RegsToPass vector 518 if (VA.isRegLoc()) { 519 if (VA.getLocVT() != MVT::f32) { 520 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 521 continue; 522 } 523 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 524 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 525 continue; 526 } 527 528 assert(VA.isMemLoc()); 529 530 // Create a store off the stack pointer for this argument. 531 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 532 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); 533 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 534 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 535 MachinePointerInfo(), 536 false, false, 0)); 537 } 538 539 540 // Emit all stores, make sure the occur before any copies into physregs. 541 if (!MemOpChains.empty()) 542 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 543 &MemOpChains[0], MemOpChains.size()); 544 545 // Build a sequence of copy-to-reg nodes chained together with token 546 // chain and flag operands which copy the outgoing args into registers. 547 // The InFlag in necessary since all emitted instructions must be 548 // stuck together. 549 SDValue InFlag; 550 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 551 unsigned Reg = RegsToPass[i].first; 552 // Remap I0->I7 -> O0->O7. 553 if (Reg >= SP::I0 && Reg <= SP::I7) 554 Reg = Reg-SP::I0+SP::O0; 555 556 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 557 InFlag = Chain.getValue(1); 558 } 559 560 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0; 561 562 // If the callee is a GlobalAddress node (quite common, every direct call is) 563 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 564 // Likewise ExternalSymbol -> TargetExternalSymbol. 565 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 566 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 567 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 568 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 569 570 // Returns a chain & a flag for retval copy to use 571 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 572 SmallVector<SDValue, 8> Ops; 573 Ops.push_back(Chain); 574 Ops.push_back(Callee); 575 if (hasStructRetAttr) 576 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); 577 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 578 unsigned Reg = RegsToPass[i].first; 579 if (Reg >= SP::I0 && Reg <= SP::I7) 580 Reg = Reg-SP::I0+SP::O0; 581 582 Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType())); 583 } 584 if (InFlag.getNode()) 585 Ops.push_back(InFlag); 586 587 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 588 InFlag = Chain.getValue(1); 589 590 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 591 DAG.getIntPtrConstant(0, true), InFlag); 592 InFlag = Chain.getValue(1); 593 594 // Assign locations to each value returned by this call. 595 SmallVector<CCValAssign, 16> RVLocs; 596 CCState RVInfo(CallConv, isVarArg, DAG.getTarget(), 597 RVLocs, *DAG.getContext()); 598 599 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 600 601 // Copy all of the result registers out of their specified physreg. 602 for (unsigned i = 0; i != RVLocs.size(); ++i) { 603 unsigned Reg = RVLocs[i].getLocReg(); 604 605 // Remap I0->I7 -> O0->O7. 606 if (Reg >= SP::I0 && Reg <= SP::I7) 607 Reg = Reg-SP::I0+SP::O0; 608 609 Chain = DAG.getCopyFromReg(Chain, dl, Reg, 610 RVLocs[i].getValVT(), InFlag).getValue(1); 611 InFlag = Chain.getValue(2); 612 InVals.push_back(Chain.getValue(0)); 613 } 614 615 return Chain; 616} 617 618unsigned 619SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const 620{ 621 const Function *CalleeFn = 0; 622 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 623 CalleeFn = dyn_cast<Function>(G->getGlobal()); 624 } else if (ExternalSymbolSDNode *E = 625 dyn_cast<ExternalSymbolSDNode>(Callee)) { 626 const Function *Fn = DAG.getMachineFunction().getFunction(); 627 const Module *M = Fn->getParent(); 628 CalleeFn = M->getFunction(E->getSymbol()); 629 } 630 631 if (!CalleeFn) 632 return 0; 633 634 assert(CalleeFn->hasStructRetAttr() && 635 "Callee does not have the StructRet attribute."); 636 637 const PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType()); 638 const Type *ElementTy = Ty->getElementType(); 639 return getTargetData()->getTypeAllocSize(ElementTy); 640} 641 642//===----------------------------------------------------------------------===// 643// TargetLowering Implementation 644//===----------------------------------------------------------------------===// 645 646/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 647/// condition. 648static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 649 switch (CC) { 650 default: llvm_unreachable("Unknown integer condition code!"); 651 case ISD::SETEQ: return SPCC::ICC_E; 652 case ISD::SETNE: return SPCC::ICC_NE; 653 case ISD::SETLT: return SPCC::ICC_L; 654 case ISD::SETGT: return SPCC::ICC_G; 655 case ISD::SETLE: return SPCC::ICC_LE; 656 case ISD::SETGE: return SPCC::ICC_GE; 657 case ISD::SETULT: return SPCC::ICC_CS; 658 case ISD::SETULE: return SPCC::ICC_LEU; 659 case ISD::SETUGT: return SPCC::ICC_GU; 660 case ISD::SETUGE: return SPCC::ICC_CC; 661 } 662} 663 664/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 665/// FCC condition. 666static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 667 switch (CC) { 668 default: llvm_unreachable("Unknown fp condition code!"); 669 case ISD::SETEQ: 670 case ISD::SETOEQ: return SPCC::FCC_E; 671 case ISD::SETNE: 672 case ISD::SETUNE: return SPCC::FCC_NE; 673 case ISD::SETLT: 674 case ISD::SETOLT: return SPCC::FCC_L; 675 case ISD::SETGT: 676 case ISD::SETOGT: return SPCC::FCC_G; 677 case ISD::SETLE: 678 case ISD::SETOLE: return SPCC::FCC_LE; 679 case ISD::SETGE: 680 case ISD::SETOGE: return SPCC::FCC_GE; 681 case ISD::SETULT: return SPCC::FCC_UL; 682 case ISD::SETULE: return SPCC::FCC_ULE; 683 case ISD::SETUGT: return SPCC::FCC_UG; 684 case ISD::SETUGE: return SPCC::FCC_UGE; 685 case ISD::SETUO: return SPCC::FCC_U; 686 case ISD::SETO: return SPCC::FCC_O; 687 case ISD::SETONE: return SPCC::FCC_LG; 688 case ISD::SETUEQ: return SPCC::FCC_UE; 689 } 690} 691 692SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 693 : TargetLowering(TM, new TargetLoweringObjectFileELF()) { 694 695 // Set up the register classes. 696 addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); 697 addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); 698 addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); 699 700 // Turn FP extload into load/fextend 701 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 702 // Sparc doesn't have i1 sign extending load 703 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 704 // Turn FP truncstore into trunc + store. 705 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 706 707 // Custom legalize GlobalAddress nodes into LO/HI parts. 708 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 709 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 710 setOperationAction(ISD::ConstantPool , MVT::i32, Custom); 711 712 // Sparc doesn't have sext_inreg, replace them with shl/sra 713 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 714 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 715 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 716 717 // Sparc has no REM or DIVREM operations. 718 setOperationAction(ISD::UREM, MVT::i32, Expand); 719 setOperationAction(ISD::SREM, MVT::i32, Expand); 720 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 721 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 722 723 // Custom expand fp<->sint 724 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 725 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 726 727 // Expand fp<->uint 728 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 729 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 730 731 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 732 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 733 734 // Sparc has no select or setcc: expand to SELECT_CC. 735 setOperationAction(ISD::SELECT, MVT::i32, Expand); 736 setOperationAction(ISD::SELECT, MVT::f32, Expand); 737 setOperationAction(ISD::SELECT, MVT::f64, Expand); 738 setOperationAction(ISD::SETCC, MVT::i32, Expand); 739 setOperationAction(ISD::SETCC, MVT::f32, Expand); 740 setOperationAction(ISD::SETCC, MVT::f64, Expand); 741 742 // Sparc doesn't have BRCOND either, it has BR_CC. 743 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 744 setOperationAction(ISD::BRIND, MVT::Other, Expand); 745 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 746 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 747 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 748 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 749 750 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 751 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 752 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 753 754 // SPARC has no intrinsics for these particular operations. 755 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 756 757 setOperationAction(ISD::FSIN , MVT::f64, Expand); 758 setOperationAction(ISD::FCOS , MVT::f64, Expand); 759 setOperationAction(ISD::FREM , MVT::f64, Expand); 760 setOperationAction(ISD::FSIN , MVT::f32, Expand); 761 setOperationAction(ISD::FCOS , MVT::f32, Expand); 762 setOperationAction(ISD::FREM , MVT::f32, Expand); 763 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 764 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 765 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 766 setOperationAction(ISD::ROTL , MVT::i32, Expand); 767 setOperationAction(ISD::ROTR , MVT::i32, Expand); 768 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 769 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 770 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 771 setOperationAction(ISD::FPOW , MVT::f64, Expand); 772 setOperationAction(ISD::FPOW , MVT::f32, Expand); 773 774 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 775 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 776 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 777 778 // FIXME: Sparc provides these multiplies, but we don't have them yet. 779 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 780 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 781 782 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 783 784 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 785 setOperationAction(ISD::VASTART , MVT::Other, Custom); 786 // VAARG needs to be lowered to not do unaligned accesses for doubles. 787 setOperationAction(ISD::VAARG , MVT::Other, Custom); 788 789 // Use the default implementation. 790 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 791 setOperationAction(ISD::VAEND , MVT::Other, Expand); 792 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 793 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 794 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 795 796 // No debug info support yet. 797 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 798 799 setStackPointerRegisterToSaveRestore(SP::O6); 800 801 if (TM.getSubtarget<SparcSubtarget>().isV9()) 802 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 803 804 computeRegisterProperties(); 805} 806 807const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 808 switch (Opcode) { 809 default: return 0; 810 case SPISD::CMPICC: return "SPISD::CMPICC"; 811 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 812 case SPISD::BRICC: return "SPISD::BRICC"; 813 case SPISD::BRFCC: return "SPISD::BRFCC"; 814 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 815 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 816 case SPISD::Hi: return "SPISD::Hi"; 817 case SPISD::Lo: return "SPISD::Lo"; 818 case SPISD::FTOI: return "SPISD::FTOI"; 819 case SPISD::ITOF: return "SPISD::ITOF"; 820 case SPISD::CALL: return "SPISD::CALL"; 821 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 822 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; 823 case SPISD::FLUSHW: return "SPISD::FLUSHW"; 824 } 825} 826 827/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 828/// be zero. Op is expected to be a target specific node. Used by DAG 829/// combiner. 830void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 831 const APInt &Mask, 832 APInt &KnownZero, 833 APInt &KnownOne, 834 const SelectionDAG &DAG, 835 unsigned Depth) const { 836 APInt KnownZero2, KnownOne2; 837 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 838 839 switch (Op.getOpcode()) { 840 default: break; 841 case SPISD::SELECT_ICC: 842 case SPISD::SELECT_FCC: 843 DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne, 844 Depth+1); 845 DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2, 846 Depth+1); 847 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 848 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 849 850 // Only known if known in both the LHS and RHS. 851 KnownOne &= KnownOne2; 852 KnownZero &= KnownZero2; 853 break; 854 } 855} 856 857// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 858// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 859static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 860 ISD::CondCode CC, unsigned &SPCC) { 861 if (isa<ConstantSDNode>(RHS) && 862 cast<ConstantSDNode>(RHS)->isNullValue() && 863 CC == ISD::SETNE && 864 ((LHS.getOpcode() == SPISD::SELECT_ICC && 865 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 866 (LHS.getOpcode() == SPISD::SELECT_FCC && 867 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 868 isa<ConstantSDNode>(LHS.getOperand(0)) && 869 isa<ConstantSDNode>(LHS.getOperand(1)) && 870 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && 871 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { 872 SDValue CMPCC = LHS.getOperand(3); 873 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 874 LHS = CMPCC.getOperand(0); 875 RHS = CMPCC.getOperand(1); 876 } 877} 878 879SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, 880 SelectionDAG &DAG) const { 881 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 882 // FIXME there isn't really any debug info here 883 DebugLoc dl = Op.getDebugLoc(); 884 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32); 885 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA); 886 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA); 887 888 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 889 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 890 891 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 892 getPointerTy()); 893 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 894 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 895 GlobalBase, RelAddr); 896 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 897 AbsAddr, MachinePointerInfo(), false, false, 0); 898} 899 900SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, 901 SelectionDAG &DAG) const { 902 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 903 // FIXME there isn't really any debug info here 904 DebugLoc dl = Op.getDebugLoc(); 905 const Constant *C = N->getConstVal(); 906 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); 907 SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP); 908 SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP); 909 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) 910 return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 911 912 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl, 913 getPointerTy()); 914 SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); 915 SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, 916 GlobalBase, RelAddr); 917 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 918 AbsAddr, MachinePointerInfo(), false, false, 0); 919} 920 921static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 922 DebugLoc dl = Op.getDebugLoc(); 923 // Convert the fp value to integer in an FP register. 924 assert(Op.getValueType() == MVT::i32); 925 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 926 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 927} 928 929static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 930 DebugLoc dl = Op.getDebugLoc(); 931 assert(Op.getOperand(0).getValueType() == MVT::i32); 932 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 933 // Convert the int value to FP in an FP register. 934 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp); 935} 936 937static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 938 SDValue Chain = Op.getOperand(0); 939 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 940 SDValue LHS = Op.getOperand(2); 941 SDValue RHS = Op.getOperand(3); 942 SDValue Dest = Op.getOperand(4); 943 DebugLoc dl = Op.getDebugLoc(); 944 unsigned Opc, SPCC = ~0U; 945 946 // If this is a br_cc of a "setcc", and if the setcc got lowered into 947 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 948 LookThroughSetCC(LHS, RHS, CC, SPCC); 949 950 // Get the condition flag. 951 SDValue CompareFlag; 952 if (LHS.getValueType() == MVT::i32) { 953 std::vector<EVT> VTs; 954 VTs.push_back(MVT::i32); 955 VTs.push_back(MVT::Glue); 956 SDValue Ops[2] = { LHS, RHS }; 957 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 958 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 959 Opc = SPISD::BRICC; 960 } else { 961 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 962 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 963 Opc = SPISD::BRFCC; 964 } 965 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 966 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 967} 968 969static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 970 SDValue LHS = Op.getOperand(0); 971 SDValue RHS = Op.getOperand(1); 972 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 973 SDValue TrueVal = Op.getOperand(2); 974 SDValue FalseVal = Op.getOperand(3); 975 DebugLoc dl = Op.getDebugLoc(); 976 unsigned Opc, SPCC = ~0U; 977 978 // If this is a select_cc of a "setcc", and if the setcc got lowered into 979 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 980 LookThroughSetCC(LHS, RHS, CC, SPCC); 981 982 SDValue CompareFlag; 983 if (LHS.getValueType() == MVT::i32) { 984 std::vector<EVT> VTs; 985 VTs.push_back(LHS.getValueType()); // subcc returns a value 986 VTs.push_back(MVT::Glue); 987 SDValue Ops[2] = { LHS, RHS }; 988 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 989 Opc = SPISD::SELECT_ICC; 990 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 991 } else { 992 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 993 Opc = SPISD::SELECT_FCC; 994 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 995 } 996 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 997 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 998} 999 1000static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 1001 const SparcTargetLowering &TLI) { 1002 MachineFunction &MF = DAG.getMachineFunction(); 1003 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 1004 1005 // vastart just stores the address of the VarArgsFrameIndex slot into the 1006 // memory location argument. 1007 DebugLoc dl = Op.getDebugLoc(); 1008 SDValue Offset = 1009 DAG.getNode(ISD::ADD, dl, MVT::i32, 1010 DAG.getRegister(SP::I6, MVT::i32), 1011 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(), 1012 MVT::i32)); 1013 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1014 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), 1015 MachinePointerInfo(SV), false, false, 0); 1016} 1017 1018static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 1019 SDNode *Node = Op.getNode(); 1020 EVT VT = Node->getValueType(0); 1021 SDValue InChain = Node->getOperand(0); 1022 SDValue VAListPtr = Node->getOperand(1); 1023 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1024 DebugLoc dl = Node->getDebugLoc(); 1025 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, 1026 MachinePointerInfo(SV), false, false, 0); 1027 // Increment the pointer, VAList, to the next vaarg 1028 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, 1029 DAG.getConstant(VT.getSizeInBits()/8, 1030 MVT::i32)); 1031 // Store the incremented VAList to the legalized pointer 1032 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr, 1033 VAListPtr, MachinePointerInfo(SV), false, false, 0); 1034 // Load the actual argument out of the pointer VAList, unless this is an 1035 // f64 load. 1036 if (VT != MVT::f64) 1037 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(), 1038 false, false, 0); 1039 1040 // Otherwise, load it as i64, then do a bitconvert. 1041 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(), 1042 false, false, 0); 1043 1044 // Bit-Convert the value to f64. 1045 SDValue Ops[2] = { 1046 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V), 1047 V.getValue(1) 1048 }; 1049 return DAG.getMergeValues(Ops, 2, dl); 1050} 1051 1052static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { 1053 SDValue Chain = Op.getOperand(0); // Legalize the chain. 1054 SDValue Size = Op.getOperand(1); // Legalize the size. 1055 DebugLoc dl = Op.getDebugLoc(); 1056 1057 unsigned SPReg = SP::O6; 1058 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 1059 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value 1060 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 1061 1062 // The resultant pointer is actually 16 words from the bottom of the stack, 1063 // to provide a register spill area. 1064 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, 1065 DAG.getConstant(96, MVT::i32)); 1066 SDValue Ops[2] = { NewVal, Chain }; 1067 return DAG.getMergeValues(Ops, 2, dl); 1068} 1069 1070 1071static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { 1072 DebugLoc dl = Op.getDebugLoc(); 1073 SDValue Chain = DAG.getNode(SPISD::FLUSHW, 1074 dl, MVT::Other, DAG.getEntryNode()); 1075 return Chain; 1076} 1077 1078static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 1079 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1080 MFI->setFrameAddressIsTaken(true); 1081 1082 EVT VT = Op.getValueType(); 1083 DebugLoc dl = Op.getDebugLoc(); 1084 unsigned FrameReg = SP::I6; 1085 1086 uint64_t depth = Op.getConstantOperandVal(0); 1087 1088 SDValue FrameAddr; 1089 if (depth == 0) 1090 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 1091 else { 1092 // flush first to make sure the windowed registers' values are in stack 1093 SDValue Chain = getFLUSHW(Op, DAG); 1094 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); 1095 1096 for (uint64_t i = 0; i != depth; ++i) { 1097 SDValue Ptr = DAG.getNode(ISD::ADD, 1098 dl, MVT::i32, 1099 FrameAddr, DAG.getIntPtrConstant(56)); 1100 FrameAddr = DAG.getLoad(MVT::i32, dl, 1101 Chain, 1102 Ptr, 1103 MachinePointerInfo(), false, false, 0); 1104 } 1105 } 1106 return FrameAddr; 1107} 1108 1109static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 1110 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1111 MFI->setReturnAddressIsTaken(true); 1112 1113 EVT VT = Op.getValueType(); 1114 DebugLoc dl = Op.getDebugLoc(); 1115 unsigned RetReg = SP::I7; 1116 1117 uint64_t depth = Op.getConstantOperandVal(0); 1118 1119 SDValue RetAddr; 1120 if (depth == 0) 1121 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); 1122 else { 1123 // flush first to make sure the windowed registers' values are in stack 1124 SDValue Chain = getFLUSHW(Op, DAG); 1125 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT); 1126 1127 for (uint64_t i = 0; i != depth; ++i) { 1128 SDValue Ptr = DAG.getNode(ISD::ADD, 1129 dl, MVT::i32, 1130 RetAddr, 1131 DAG.getIntPtrConstant((i == depth-1)?60:56)); 1132 RetAddr = DAG.getLoad(MVT::i32, dl, 1133 Chain, 1134 Ptr, 1135 MachinePointerInfo(), false, false, 0); 1136 } 1137 } 1138 return RetAddr; 1139} 1140 1141SDValue SparcTargetLowering:: 1142LowerOperation(SDValue Op, SelectionDAG &DAG) const { 1143 switch (Op.getOpcode()) { 1144 default: llvm_unreachable("Should not custom lower this!"); 1145 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1146 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1147 case ISD::GlobalTLSAddress: 1148 llvm_unreachable("TLS not implemented for Sparc."); 1149 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 1150 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1151 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 1152 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 1153 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 1154 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1155 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 1156 case ISD::VAARG: return LowerVAARG(Op, DAG); 1157 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 1158 } 1159} 1160 1161MachineBasicBlock * 1162SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1163 MachineBasicBlock *BB) const { 1164 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1165 unsigned BROpcode; 1166 unsigned CC; 1167 DebugLoc dl = MI->getDebugLoc(); 1168 // Figure out the conditional branch opcode to use for this select_cc. 1169 switch (MI->getOpcode()) { 1170 default: llvm_unreachable("Unknown SELECT_CC!"); 1171 case SP::SELECT_CC_Int_ICC: 1172 case SP::SELECT_CC_FP_ICC: 1173 case SP::SELECT_CC_DFP_ICC: 1174 BROpcode = SP::BCOND; 1175 break; 1176 case SP::SELECT_CC_Int_FCC: 1177 case SP::SELECT_CC_FP_FCC: 1178 case SP::SELECT_CC_DFP_FCC: 1179 BROpcode = SP::FBCOND; 1180 break; 1181 } 1182 1183 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 1184 1185 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1186 // control-flow pattern. The incoming instruction knows the destination vreg 1187 // to set, the condition code register to branch on, the true/false values to 1188 // select between, and a branch opcode to use. 1189 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1190 MachineFunction::iterator It = BB; 1191 ++It; 1192 1193 // thisMBB: 1194 // ... 1195 // TrueVal = ... 1196 // [f]bCC copy1MBB 1197 // fallthrough --> copy0MBB 1198 MachineBasicBlock *thisMBB = BB; 1199 MachineFunction *F = BB->getParent(); 1200 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1201 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1202 F->insert(It, copy0MBB); 1203 F->insert(It, sinkMBB); 1204 1205 // Transfer the remainder of BB and its successor edges to sinkMBB. 1206 sinkMBB->splice(sinkMBB->begin(), BB, 1207 llvm::next(MachineBasicBlock::iterator(MI)), 1208 BB->end()); 1209 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1210 1211 // Add the true and fallthrough blocks as its successors. 1212 BB->addSuccessor(copy0MBB); 1213 BB->addSuccessor(sinkMBB); 1214 1215 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 1216 1217 // copy0MBB: 1218 // %FalseValue = ... 1219 // # fallthrough to sinkMBB 1220 BB = copy0MBB; 1221 1222 // Update machine-CFG edges 1223 BB->addSuccessor(sinkMBB); 1224 1225 // sinkMBB: 1226 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1227 // ... 1228 BB = sinkMBB; 1229 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 1230 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1231 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1232 1233 MI->eraseFromParent(); // The pseudo instruction is gone now. 1234 return BB; 1235} 1236 1237//===----------------------------------------------------------------------===// 1238// Sparc Inline Assembly Support 1239//===----------------------------------------------------------------------===// 1240 1241/// getConstraintType - Given a constraint letter, return the type of 1242/// constraint it is for this target. 1243SparcTargetLowering::ConstraintType 1244SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 1245 if (Constraint.size() == 1) { 1246 switch (Constraint[0]) { 1247 default: break; 1248 case 'r': return C_RegisterClass; 1249 } 1250 } 1251 1252 return TargetLowering::getConstraintType(Constraint); 1253} 1254 1255std::pair<unsigned, const TargetRegisterClass*> 1256SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1257 EVT VT) const { 1258 if (Constraint.size() == 1) { 1259 switch (Constraint[0]) { 1260 case 'r': 1261 return std::make_pair(0U, SP::IntRegsRegisterClass); 1262 } 1263 } 1264 1265 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1266} 1267 1268std::vector<unsigned> SparcTargetLowering:: 1269getRegClassForInlineAsmConstraint(const std::string &Constraint, 1270 EVT VT) const { 1271 if (Constraint.size() != 1) 1272 return std::vector<unsigned>(); 1273 1274 switch (Constraint[0]) { 1275 default: break; 1276 case 'r': 1277 return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3, 1278 SP::L4, SP::L5, SP::L6, SP::L7, 1279 SP::I0, SP::I1, SP::I2, SP::I3, 1280 SP::I4, SP::I5, 1281 SP::O0, SP::O1, SP::O2, SP::O3, 1282 SP::O4, SP::O5, SP::O7, 0); 1283 } 1284 1285 return std::vector<unsigned>(); 1286} 1287 1288bool 1289SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1290 // The Sparc target isn't yet aware of offsets. 1291 return false; 1292} 1293 1294/// getFunctionAlignment - Return the Log2 alignment of this function. 1295unsigned SparcTargetLowering::getFunctionAlignment(const Function *) const { 1296 return 2; 1297} 1298