SparcISelLowering.cpp revision 7d2ad624fa749a6d3edac0d94e9c107989c16304 
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "SparcISelLowering.h"
16#include "SparcTargetMachine.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24#include "llvm/ADT/VectorExtras.h"
25using namespace llvm;
26
27
28//===----------------------------------------------------------------------===//
29// Calling Convention Implementation
30//===----------------------------------------------------------------------===//
31
32#include "SparcGenCallingConv.inc"
33
34static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) {
35  // CCValAssign - represent the assignment of the return value to locations.
36  SmallVector<CCValAssign, 16> RVLocs;
37  unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
38  bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
39
40  // CCState - Info about the registers and stack slot.
41  CCState CCInfo(CC, isVarArg, DAG.getTarget(), RVLocs);
42
43  // Analize return values of ISD::RET
44  CCInfo.AnalyzeReturn(Op.getNode(), RetCC_Sparc32);
45
46  // If this is the first return lowered for this function, add the regs to the
47  // liveout set for the function.
48  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
49    for (unsigned i = 0; i != RVLocs.size(); ++i)
50      if (RVLocs[i].isRegLoc())
51        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
52  }
53
54  SDValue Chain = Op.getOperand(0);
55  SDValue Flag;
56
57  // Copy the result values into the output registers.
58  for (unsigned i = 0; i != RVLocs.size(); ++i) {
59    CCValAssign &VA = RVLocs[i];
60    assert(VA.isRegLoc() && "Can only return in registers!");
61
62    // ISD::RET => ret chain, (regnum1,val1), ...
63    // So i*2+1 index only the regnums.
64    Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
65
66    // Guarantee that all emitted copies are stuck together with flags.
67    Flag = Chain.getValue(1);
68  }
69
70  if (Flag.getNode())
71    return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain, Flag);
72  return DAG.getNode(SPISD::RET_FLAG, MVT::Other, Chain);
73}
74
75/// LowerArguments - V8 uses a very simple ABI, where all values are passed in
76/// either one or two GPRs, including FP values.  TODO: we should pass FP values
77/// in FP registers for fastcc functions.
78void
79SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG,
80                                    SmallVectorImpl<SDValue> &ArgValues,
81                                    DebugLoc dl) {
82  MachineFunction &MF = DAG.getMachineFunction();
83  MachineRegisterInfo &RegInfo = MF.getRegInfo();
84
85  static const unsigned ArgRegs[] = {
86    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
87  };
88
89  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
90  unsigned ArgOffset = 68;
91
92  SDValue Root = DAG.getRoot();
93  std::vector<SDValue> OutChains;
94
95  for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
96    MVT ObjectVT = getValueType(I->getType());
97
98    switch (ObjectVT.getSimpleVT()) {
99    default: assert(0 && "Unhandled argument type!");
100    case MVT::i1:
101    case MVT::i8:
102    case MVT::i16:
103    case MVT::i32:
104      if (I->use_empty()) {                // Argument is dead.
105        if (CurArgReg < ArgRegEnd) ++CurArgReg;
106        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
107      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
108        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
109        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
110        SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
111        if (ObjectVT != MVT::i32) {
112          unsigned AssertOp = ISD::AssertSext;
113          Arg = DAG.getNode(AssertOp, MVT::i32, Arg,
114                            DAG.getValueType(ObjectVT));
115          Arg = DAG.getNode(ISD::TRUNCATE, ObjectVT, Arg);
116        }
117        ArgValues.push_back(Arg);
118      } else {
119        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
120        SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
121        SDValue Load;
122        if (ObjectVT == MVT::i32) {
123          Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
124        } else {
125          ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
126
127          // Sparc is big endian, so add an offset based on the ObjectVT.
128          unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
129          FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
130                              DAG.getConstant(Offset, MVT::i32));
131          Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
132                                NULL, 0, ObjectVT);
133          Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
134        }
135        ArgValues.push_back(Load);
136      }
137
138      ArgOffset += 4;
139      break;
140    case MVT::f32:
141      if (I->use_empty()) {                // Argument is dead.
142        if (CurArgReg < ArgRegEnd) ++CurArgReg;
143        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
144      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
145        // FP value is passed in an integer register.
146        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
147        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
148        SDValue Arg = DAG.getCopyFromReg(Root, VReg, MVT::i32);
149
150        Arg = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Arg);
151        ArgValues.push_back(Arg);
152      } else {
153        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
154        SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
155        SDValue Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
156        ArgValues.push_back(Load);
157      }
158      ArgOffset += 4;
159      break;
160
161    case MVT::i64:
162    case MVT::f64:
163      if (I->use_empty()) {                // Argument is dead.
164        if (CurArgReg < ArgRegEnd) ++CurArgReg;
165        if (CurArgReg < ArgRegEnd) ++CurArgReg;
166        ArgValues.push_back(DAG.getNode(ISD::UNDEF, ObjectVT));
167      } else {
168        SDValue HiVal;
169        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
170          unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
171          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
172          HiVal = DAG.getCopyFromReg(Root, VRegHi, MVT::i32);
173        } else {
174          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
175          SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
176          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
177        }
178
179        SDValue LoVal;
180        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
181          unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
182          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
183          LoVal = DAG.getCopyFromReg(Root, VRegLo, MVT::i32);
184        } else {
185          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
186          SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
187          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
188        }
189
190        // Compose the two halves together into an i64 unit.
191        SDValue WholeValue =
192          DAG.getNode(ISD::BUILD_PAIR, MVT::i64, LoVal, HiVal);
193
194        // If we want a double, do a bit convert.
195        if (ObjectVT == MVT::f64)
196          WholeValue = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, WholeValue);
197
198        ArgValues.push_back(WholeValue);
199      }
200      ArgOffset += 8;
201      break;
202    }
203  }
204
205  // Store remaining ArgRegs to the stack if this is a varargs function.
206  if (F.isVarArg()) {
207    // Remember the vararg offset for the va_start implementation.
208    VarArgsFrameOffset = ArgOffset;
209
210    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
211      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
212      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
213      SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
214
215      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
216      SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
217
218      OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
219      ArgOffset += 4;
220    }
221  }
222
223  if (!OutChains.empty())
224    DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
225                            &OutChains[0], OutChains.size()));
226}
227
228static SDValue LowerCALL(SDValue Op, SelectionDAG &DAG) {
229  CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
230  unsigned CallingConv = TheCall->getCallingConv();
231  SDValue Chain = TheCall->getChain();
232  SDValue Callee = TheCall->getCallee();
233  bool isVarArg = TheCall->isVarArg();
234
235#if 0
236  // Analyze operands of the call, assigning locations to each operand.
237  SmallVector<CCValAssign, 16> ArgLocs;
238  CCState CCInfo(CallingConv, isVarArg, DAG.getTarget(), ArgLocs);
239  CCInfo.AnalyzeCallOperands(Op.getNode(), CC_Sparc32);
240
241  // Get the size of the outgoing arguments stack space requirement.
242  unsigned ArgsSize = CCInfo.getNextStackOffset();
243  // FIXME: We can't use this until f64 is known to take two GPRs.
244#else
245  (void)CC_Sparc32;
246
247  // Count the size of the outgoing arguments.
248  unsigned ArgsSize = 0;
249  for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
250    switch (TheCall->getArg(i).getValueType().getSimpleVT()) {
251      default: assert(0 && "Unknown value type!");
252      case MVT::i1:
253      case MVT::i8:
254      case MVT::i16:
255      case MVT::i32:
256      case MVT::f32:
257        ArgsSize += 4;
258        break;
259      case MVT::i64:
260      case MVT::f64:
261        ArgsSize += 8;
262        break;
263    }
264  }
265  if (ArgsSize > 4*6)
266    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
267  else
268    ArgsSize = 0;
269#endif
270
271  // Keep stack frames 8-byte aligned.
272  ArgsSize = (ArgsSize+7) & ~7;
273
274  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
275
276  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
277  SmallVector<SDValue, 8> MemOpChains;
278
279#if 0
280  // Walk the register/memloc assignments, inserting copies/loads.
281  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
282    CCValAssign &VA = ArgLocs[i];
283
284    // Arguments start after the 5 first operands of ISD::CALL
285    SDValue Arg = TheCall->getArg(i);
286
287    // Promote the value if needed.
288    switch (VA.getLocInfo()) {
289    default: assert(0 && "Unknown loc info!");
290    case CCValAssign::Full: break;
291    case CCValAssign::SExt:
292      Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
293      break;
294    case CCValAssign::ZExt:
295      Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
296      break;
297    case CCValAssign::AExt:
298      Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
299      break;
300    }
301
302    // Arguments that can be passed on register must be kept at
303    // RegsToPass vector
304    if (VA.isRegLoc()) {
305      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
306      continue;
307    }
308
309    assert(VA.isMemLoc());
310
311    // Create a store off the stack pointer for this argument.
312    SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
313    // FIXME: VERIFY THAT 68 IS RIGHT.
314    SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
315    PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
316    MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
317  }
318
319#else
320  static const unsigned ArgRegs[] = {
321    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
322  };
323  unsigned ArgOffset = 68;
324
325  for (unsigned i = 0, e = TheCall->getNumArgs(); i != e; ++i) {
326    SDValue Val = TheCall->getArg(i);
327    MVT ObjectVT = Val.getValueType();
328    SDValue ValToStore(0, 0);
329    unsigned ObjSize;
330    switch (ObjectVT.getSimpleVT()) {
331    default: assert(0 && "Unhandled argument type!");
332    case MVT::i32:
333      ObjSize = 4;
334
335      if (RegsToPass.size() >= 6) {
336        ValToStore = Val;
337      } else {
338        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
339      }
340      break;
341    case MVT::f32:
342      ObjSize = 4;
343      if (RegsToPass.size() >= 6) {
344        ValToStore = Val;
345      } else {
346        // Convert this to a FP value in an int reg.
347        Val = DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Val);
348        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
349      }
350      break;
351    case MVT::f64: {
352      ObjSize = 8;
353      if (RegsToPass.size() >= 6) {
354        ValToStore = Val;    // Whole thing is passed in memory.
355        break;
356      }
357
358      // Break into top and bottom parts by storing to the stack and loading
359      // out the parts as integers.  Top part goes in a reg.
360      SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
361      SDValue Store = DAG.getStore(DAG.getEntryNode(), Val, StackPtr, NULL, 0);
362      // Sparc is big-endian, so the high part comes first.
363      SDValue Hi = DAG.getLoad(MVT::i32, Store, StackPtr, NULL, 0, 0);
364      // Increment the pointer to the other half.
365      StackPtr = DAG.getNode(ISD::ADD, StackPtr.getValueType(), StackPtr,
366                             DAG.getIntPtrConstant(4));
367      // Load the low part.
368      SDValue Lo = DAG.getLoad(MVT::i32, Store, StackPtr, NULL, 0, 0);
369
370      RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
371
372      if (RegsToPass.size() >= 6) {
373        ValToStore = Lo;
374        ArgOffset += 4;
375        ObjSize = 4;
376      } else {
377        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
378      }
379      break;
380    }
381    case MVT::i64: {
382      ObjSize = 8;
383      if (RegsToPass.size() >= 6) {
384        ValToStore = Val;    // Whole thing is passed in memory.
385        break;
386      }
387
388      // Split the value into top and bottom part.  Top part goes in a reg.
389      SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
390                                 DAG.getConstant(1, MVT::i32));
391      SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
392                                 DAG.getConstant(0, MVT::i32));
393      RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
394
395      if (RegsToPass.size() >= 6) {
396        ValToStore = Lo;
397        ArgOffset += 4;
398        ObjSize = 4;
399      } else {
400        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
401      }
402      break;
403    }
404    }
405
406    if (ValToStore.getNode()) {
407      SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
408      SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
409      PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
410      MemOpChains.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
411    }
412    ArgOffset += ObjSize;
413  }
414#endif
415
416  // Emit all stores, make sure the occur before any copies into physregs.
417  if (!MemOpChains.empty())
418    Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
419                        &MemOpChains[0], MemOpChains.size());
420
421  // Build a sequence of copy-to-reg nodes chained together with token
422  // chain and flag operands which copy the outgoing args into registers.
423  // The InFlag in necessary since all emited instructions must be
424  // stuck together.
425  SDValue InFlag;
426  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
427    unsigned Reg = RegsToPass[i].first;
428    // Remap I0->I7 -> O0->O7.
429    if (Reg >= SP::I0 && Reg <= SP::I7)
430      Reg = Reg-SP::I0+SP::O0;
431
432    Chain = DAG.getCopyToReg(Chain, Reg, RegsToPass[i].second, InFlag);
433    InFlag = Chain.getValue(1);
434  }
435
436  // If the callee is a GlobalAddress node (quite common, every direct call is)
437  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
438  // Likewise ExternalSymbol -> TargetExternalSymbol.
439  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
440    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
441  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
442    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
443
444  std::vector<MVT> NodeTys;
445  NodeTys.push_back(MVT::Other);   // Returns a chain
446  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
447  SDValue Ops[] = { Chain, Callee, InFlag };
448  Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
449  InFlag = Chain.getValue(1);
450
451  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
452                             DAG.getIntPtrConstant(0, true), InFlag);
453  InFlag = Chain.getValue(1);
454
455  // Assign locations to each value returned by this call.
456  SmallVector<CCValAssign, 16> RVLocs;
457  CCState RVInfo(CallingConv, isVarArg, DAG.getTarget(), RVLocs);
458
459  RVInfo.AnalyzeCallResult(TheCall, RetCC_Sparc32);
460  SmallVector<SDValue, 8> ResultVals;
461
462  // Copy all of the result registers out of their specified physreg.
463  for (unsigned i = 0; i != RVLocs.size(); ++i) {
464    unsigned Reg = RVLocs[i].getLocReg();
465
466    // Remap I0->I7 -> O0->O7.
467    if (Reg >= SP::I0 && Reg <= SP::I7)
468      Reg = Reg-SP::I0+SP::O0;
469
470    Chain = DAG.getCopyFromReg(Chain, Reg,
471                               RVLocs[i].getValVT(), InFlag).getValue(1);
472    InFlag = Chain.getValue(2);
473    ResultVals.push_back(Chain.getValue(0));
474  }
475
476  ResultVals.push_back(Chain);
477
478  // Merge everything together with a MERGE_VALUES node.
479  return DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(), &ResultVals[0],
480                     ResultVals.size());
481}
482
483
484
485//===----------------------------------------------------------------------===//
486// TargetLowering Implementation
487//===----------------------------------------------------------------------===//
488
489/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
490/// condition.
491static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
492  switch (CC) {
493  default: assert(0 && "Unknown integer condition code!");
494  case ISD::SETEQ:  return SPCC::ICC_E;
495  case ISD::SETNE:  return SPCC::ICC_NE;
496  case ISD::SETLT:  return SPCC::ICC_L;
497  case ISD::SETGT:  return SPCC::ICC_G;
498  case ISD::SETLE:  return SPCC::ICC_LE;
499  case ISD::SETGE:  return SPCC::ICC_GE;
500  case ISD::SETULT: return SPCC::ICC_CS;
501  case ISD::SETULE: return SPCC::ICC_LEU;
502  case ISD::SETUGT: return SPCC::ICC_GU;
503  case ISD::SETUGE: return SPCC::ICC_CC;
504  }
505}
506
507/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
508/// FCC condition.
509static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
510  switch (CC) {
511  default: assert(0 && "Unknown fp condition code!");
512  case ISD::SETEQ:
513  case ISD::SETOEQ: return SPCC::FCC_E;
514  case ISD::SETNE:
515  case ISD::SETUNE: return SPCC::FCC_NE;
516  case ISD::SETLT:
517  case ISD::SETOLT: return SPCC::FCC_L;
518  case ISD::SETGT:
519  case ISD::SETOGT: return SPCC::FCC_G;
520  case ISD::SETLE:
521  case ISD::SETOLE: return SPCC::FCC_LE;
522  case ISD::SETGE:
523  case ISD::SETOGE: return SPCC::FCC_GE;
524  case ISD::SETULT: return SPCC::FCC_UL;
525  case ISD::SETULE: return SPCC::FCC_ULE;
526  case ISD::SETUGT: return SPCC::FCC_UG;
527  case ISD::SETUGE: return SPCC::FCC_UGE;
528  case ISD::SETUO:  return SPCC::FCC_U;
529  case ISD::SETO:   return SPCC::FCC_O;
530  case ISD::SETONE: return SPCC::FCC_LG;
531  case ISD::SETUEQ: return SPCC::FCC_UE;
532  }
533}
534
535
536SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
537  : TargetLowering(TM) {
538
539  // Set up the register classes.
540  addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
541  addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
542  addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
543
544  // Turn FP extload into load/fextend
545  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
546  // Sparc doesn't have i1 sign extending load
547  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
548  // Turn FP truncstore into trunc + store.
549  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
550
551  // Custom legalize GlobalAddress nodes into LO/HI parts.
552  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
553  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
554  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
555
556  // Sparc doesn't have sext_inreg, replace them with shl/sra
557  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
558  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
559  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
560
561  // Sparc has no REM or DIVREM operations.
562  setOperationAction(ISD::UREM, MVT::i32, Expand);
563  setOperationAction(ISD::SREM, MVT::i32, Expand);
564  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
565  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
566
567  // Custom expand fp<->sint
568  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
569  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
570
571  // Expand fp<->uint
572  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
573  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
574
575  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
576  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
577
578  // Sparc has no select or setcc: expand to SELECT_CC.
579  setOperationAction(ISD::SELECT, MVT::i32, Expand);
580  setOperationAction(ISD::SELECT, MVT::f32, Expand);
581  setOperationAction(ISD::SELECT, MVT::f64, Expand);
582  setOperationAction(ISD::SETCC, MVT::i32, Expand);
583  setOperationAction(ISD::SETCC, MVT::f32, Expand);
584  setOperationAction(ISD::SETCC, MVT::f64, Expand);
585
586  // Sparc doesn't have BRCOND either, it has BR_CC.
587  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
588  setOperationAction(ISD::BRIND, MVT::Other, Expand);
589  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
590  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
591  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
592  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
593
594  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
595  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
596  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
597
598  // SPARC has no intrinsics for these particular operations.
599  setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
600
601  setOperationAction(ISD::FSIN , MVT::f64, Expand);
602  setOperationAction(ISD::FCOS , MVT::f64, Expand);
603  setOperationAction(ISD::FREM , MVT::f64, Expand);
604  setOperationAction(ISD::FSIN , MVT::f32, Expand);
605  setOperationAction(ISD::FCOS , MVT::f32, Expand);
606  setOperationAction(ISD::FREM , MVT::f32, Expand);
607  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
608  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
609  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
610  setOperationAction(ISD::ROTL , MVT::i32, Expand);
611  setOperationAction(ISD::ROTR , MVT::i32, Expand);
612  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
613  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
614  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
615  setOperationAction(ISD::FPOW , MVT::f64, Expand);
616  setOperationAction(ISD::FPOW , MVT::f32, Expand);
617
618  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
619  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
620  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
621
622  // FIXME: Sparc provides these multiplies, but we don't have them yet.
623  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
624  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
625
626  // We don't have line number support yet.
627  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
628  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
629  setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
630  setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
631
632  // RET must be custom lowered, to meet ABI requirements
633  setOperationAction(ISD::RET               , MVT::Other, Custom);
634
635  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
636  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
637  // VAARG needs to be lowered to not do unaligned accesses for doubles.
638  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
639
640  // Use the default implementation.
641  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
642  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
643  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
644  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
645  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
646
647  // No debug info support yet.
648  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
649  setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
650  setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
651  setOperationAction(ISD::DECLARE, MVT::Other, Expand);
652
653  setStackPointerRegisterToSaveRestore(SP::O6);
654
655  if (TM.getSubtarget<SparcSubtarget>().isV9())
656    setOperationAction(ISD::CTPOP, MVT::i32, Legal);
657
658  computeRegisterProperties();
659}
660
661const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
662  switch (Opcode) {
663  default: return 0;
664  case SPISD::CMPICC:     return "SPISD::CMPICC";
665  case SPISD::CMPFCC:     return "SPISD::CMPFCC";
666  case SPISD::BRICC:      return "SPISD::BRICC";
667  case SPISD::BRFCC:      return "SPISD::BRFCC";
668  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
669  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
670  case SPISD::Hi:         return "SPISD::Hi";
671  case SPISD::Lo:         return "SPISD::Lo";
672  case SPISD::FTOI:       return "SPISD::FTOI";
673  case SPISD::ITOF:       return "SPISD::ITOF";
674  case SPISD::CALL:       return "SPISD::CALL";
675  case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
676  }
677}
678
679/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
680/// be zero. Op is expected to be a target specific node. Used by DAG
681/// combiner.
682void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
683                                                         const APInt &Mask,
684                                                         APInt &KnownZero,
685                                                         APInt &KnownOne,
686                                                         const SelectionDAG &DAG,
687                                                         unsigned Depth) const {
688  APInt KnownZero2, KnownOne2;
689  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);   // Don't know anything.
690
691  switch (Op.getOpcode()) {
692  default: break;
693  case SPISD::SELECT_ICC:
694  case SPISD::SELECT_FCC:
695    DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
696                          Depth+1);
697    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
698                          Depth+1);
699    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
700    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
701
702    // Only known if known in both the LHS and RHS.
703    KnownOne &= KnownOne2;
704    KnownZero &= KnownZero2;
705    break;
706  }
707}
708
709// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
710// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
711static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
712                             ISD::CondCode CC, unsigned &SPCC) {
713  if (isa<ConstantSDNode>(RHS) &&
714      cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
715      CC == ISD::SETNE &&
716      ((LHS.getOpcode() == SPISD::SELECT_ICC &&
717        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
718       (LHS.getOpcode() == SPISD::SELECT_FCC &&
719        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
720      isa<ConstantSDNode>(LHS.getOperand(0)) &&
721      isa<ConstantSDNode>(LHS.getOperand(1)) &&
722      cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
723      cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
724    SDValue CMPCC = LHS.getOperand(3);
725    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
726    LHS = CMPCC.getOperand(0);
727    RHS = CMPCC.getOperand(1);
728  }
729}
730
731static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) {
732  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
733  SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
734  SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, GA);
735  SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, GA);
736  return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
737}
738
739static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) {
740  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
741  Constant *C = N->getConstVal();
742  SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
743  SDValue Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
744  SDValue Lo = DAG.getNode(SPISD::Lo, MVT::i32, CP);
745  return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
746}
747
748static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
749  // Convert the fp value to integer in an FP register.
750  assert(Op.getValueType() == MVT::i32);
751  Op = DAG.getNode(SPISD::FTOI, MVT::f32, Op.getOperand(0));
752  return DAG.getNode(ISD::BIT_CONVERT, MVT::i32, Op);
753}
754
755static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
756  assert(Op.getOperand(0).getValueType() == MVT::i32);
757  SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Op.getOperand(0));
758  // Convert the int value to FP in an FP register.
759  return DAG.getNode(SPISD::ITOF, Op.getValueType(), Tmp);
760}
761
762static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
763  SDValue Chain = Op.getOperand(0);
764  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
765  SDValue LHS = Op.getOperand(2);
766  SDValue RHS = Op.getOperand(3);
767  SDValue Dest = Op.getOperand(4);
768  unsigned Opc, SPCC = ~0U;
769
770  // If this is a br_cc of a "setcc", and if the setcc got lowered into
771  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
772  LookThroughSetCC(LHS, RHS, CC, SPCC);
773
774  // Get the condition flag.
775  SDValue CompareFlag;
776  if (LHS.getValueType() == MVT::i32) {
777    std::vector<MVT> VTs;
778    VTs.push_back(MVT::i32);
779    VTs.push_back(MVT::Flag);
780    SDValue Ops[2] = { LHS, RHS };
781    CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
782    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
783    Opc = SPISD::BRICC;
784  } else {
785    CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
786    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
787    Opc = SPISD::BRFCC;
788  }
789  return DAG.getNode(Opc, MVT::Other, Chain, Dest,
790                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
791}
792
793static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
794  SDValue LHS = Op.getOperand(0);
795  SDValue RHS = Op.getOperand(1);
796  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
797  SDValue TrueVal = Op.getOperand(2);
798  SDValue FalseVal = Op.getOperand(3);
799  unsigned Opc, SPCC = ~0U;
800
801  // If this is a select_cc of a "setcc", and if the setcc got lowered into
802  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
803  LookThroughSetCC(LHS, RHS, CC, SPCC);
804
805  SDValue CompareFlag;
806  if (LHS.getValueType() == MVT::i32) {
807    std::vector<MVT> VTs;
808    VTs.push_back(LHS.getValueType());   // subcc returns a value
809    VTs.push_back(MVT::Flag);
810    SDValue Ops[2] = { LHS, RHS };
811    CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
812    Opc = SPISD::SELECT_ICC;
813    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
814  } else {
815    CompareFlag = DAG.getNode(SPISD::CMPFCC, MVT::Flag, LHS, RHS);
816    Opc = SPISD::SELECT_FCC;
817    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
818  }
819  return DAG.getNode(Opc, TrueVal.getValueType(), TrueVal, FalseVal,
820                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
821}
822
823static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
824                              SparcTargetLowering &TLI) {
825  // vastart just stores the address of the VarArgsFrameIndex slot into the
826  // memory location argument.
827  SDValue Offset = DAG.getNode(ISD::ADD, MVT::i32,
828                                 DAG.getRegister(SP::I6, MVT::i32),
829                                 DAG.getConstant(TLI.getVarArgsFrameOffset(),
830                                                 MVT::i32));
831  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
832  return DAG.getStore(Op.getOperand(0), Offset, Op.getOperand(1), SV, 0);
833}
834
835static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
836  SDNode *Node = Op.getNode();
837  MVT VT = Node->getValueType(0);
838  SDValue InChain = Node->getOperand(0);
839  SDValue VAListPtr = Node->getOperand(1);
840  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
841  SDValue VAList = DAG.getLoad(MVT::i32, InChain, VAListPtr, SV, 0);
842  // Increment the pointer, VAList, to the next vaarg
843  SDValue NextPtr = DAG.getNode(ISD::ADD, MVT::i32, VAList,
844                                  DAG.getConstant(VT.getSizeInBits()/8,
845                                                  MVT::i32));
846  // Store the incremented VAList to the legalized pointer
847  InChain = DAG.getStore(VAList.getValue(1), NextPtr,
848                         VAListPtr, SV, 0);
849  // Load the actual argument out of the pointer VAList, unless this is an
850  // f64 load.
851  if (VT != MVT::f64)
852    return DAG.getLoad(VT, InChain, VAList, NULL, 0);
853
854  // Otherwise, load it as i64, then do a bitconvert.
855  SDValue V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
856
857  // Bit-Convert the value to f64.
858  SDValue Ops[2] = {
859    DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
860    V.getValue(1)
861  };
862  return DAG.getMergeValues(Ops, 2);
863}
864
865static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
866  SDValue Chain = Op.getOperand(0);  // Legalize the chain.
867  SDValue Size  = Op.getOperand(1);  // Legalize the size.
868
869  unsigned SPReg = SP::O6;
870  SDValue SP = DAG.getCopyFromReg(Chain, SPReg, MVT::i32);
871  SDValue NewSP = DAG.getNode(ISD::SUB, MVT::i32, SP, Size);    // Value
872  Chain = DAG.getCopyToReg(SP.getValue(1), SPReg, NewSP);      // Output chain
873
874  // The resultant pointer is actually 16 words from the bottom of the stack,
875  // to provide a register spill area.
876  SDValue NewVal = DAG.getNode(ISD::ADD, MVT::i32, NewSP,
877                                 DAG.getConstant(96, MVT::i32));
878  SDValue Ops[2] = { NewVal, Chain };
879  return DAG.getMergeValues(Ops, 2);
880}
881
882
883SDValue SparcTargetLowering::
884LowerOperation(SDValue Op, SelectionDAG &DAG) {
885  switch (Op.getOpcode()) {
886  default: assert(0 && "Should not custom lower this!");
887  // Frame & Return address.  Currently unimplemented
888  case ISD::RETURNADDR: return SDValue();
889  case ISD::FRAMEADDR:  return SDValue();
890  case ISD::GlobalTLSAddress:
891    assert(0 && "TLS not implemented for Sparc.");
892  case ISD::GlobalAddress:      return LowerGLOBALADDRESS(Op, DAG);
893  case ISD::ConstantPool:       return LowerCONSTANTPOOL(Op, DAG);
894  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
895  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);
896  case ISD::BR_CC:              return LowerBR_CC(Op, DAG);
897  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
898  case ISD::VASTART:            return LowerVASTART(Op, DAG, *this);
899  case ISD::VAARG:              return LowerVAARG(Op, DAG);
900  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
901  case ISD::CALL:               return LowerCALL(Op, DAG);
902  case ISD::RET:                return LowerRET(Op, DAG);
903  }
904}
905
906MachineBasicBlock *
907SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
908                                                 MachineBasicBlock *BB) {
909  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
910  unsigned BROpcode;
911  unsigned CC;
912  // Figure out the conditional branch opcode to use for this select_cc.
913  switch (MI->getOpcode()) {
914  default: assert(0 && "Unknown SELECT_CC!");
915  case SP::SELECT_CC_Int_ICC:
916  case SP::SELECT_CC_FP_ICC:
917  case SP::SELECT_CC_DFP_ICC:
918    BROpcode = SP::BCOND;
919    break;
920  case SP::SELECT_CC_Int_FCC:
921  case SP::SELECT_CC_FP_FCC:
922  case SP::SELECT_CC_DFP_FCC:
923    BROpcode = SP::FBCOND;
924    break;
925  }
926
927  CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
928
929  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
930  // control-flow pattern.  The incoming instruction knows the destination vreg
931  // to set, the condition code register to branch on, the true/false values to
932  // select between, and a branch opcode to use.
933  const BasicBlock *LLVM_BB = BB->getBasicBlock();
934  MachineFunction::iterator It = BB;
935  ++It;
936
937  //  thisMBB:
938  //  ...
939  //   TrueVal = ...
940  //   [f]bCC copy1MBB
941  //   fallthrough --> copy0MBB
942  MachineBasicBlock *thisMBB = BB;
943  MachineFunction *F = BB->getParent();
944  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
945  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
946  BuildMI(BB, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
947  F->insert(It, copy0MBB);
948  F->insert(It, sinkMBB);
949  // Update machine-CFG edges by transferring all successors of the current
950  // block to the new block which will contain the Phi node for the select.
951  sinkMBB->transferSuccessors(BB);
952  // Next, add the true and fallthrough blocks as its successors.
953  BB->addSuccessor(copy0MBB);
954  BB->addSuccessor(sinkMBB);
955
956  //  copy0MBB:
957  //   %FalseValue = ...
958  //   # fallthrough to sinkMBB
959  BB = copy0MBB;
960
961  // Update machine-CFG edges
962  BB->addSuccessor(sinkMBB);
963
964  //  sinkMBB:
965  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
966  //  ...
967  BB = sinkMBB;
968  BuildMI(BB, TII.get(SP::PHI), MI->getOperand(0).getReg())
969    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
970    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
971
972  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
973  return BB;
974}
975
976//===----------------------------------------------------------------------===//
977//                         Sparc Inline Assembly Support
978//===----------------------------------------------------------------------===//
979
980/// getConstraintType - Given a constraint letter, return the type of
981/// constraint it is for this target.
982SparcTargetLowering::ConstraintType
983SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
984  if (Constraint.size() == 1) {
985    switch (Constraint[0]) {
986    default:  break;
987    case 'r': return C_RegisterClass;
988    }
989  }
990
991  return TargetLowering::getConstraintType(Constraint);
992}
993
994std::pair<unsigned, const TargetRegisterClass*>
995SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
996                                                  MVT VT) const {
997  if (Constraint.size() == 1) {
998    switch (Constraint[0]) {
999    case 'r':
1000      return std::make_pair(0U, SP::IntRegsRegisterClass);
1001    }
1002  }
1003
1004  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1005}
1006
1007std::vector<unsigned> SparcTargetLowering::
1008getRegClassForInlineAsmConstraint(const std::string &Constraint,
1009                                  MVT VT) const {
1010  if (Constraint.size() != 1)
1011    return std::vector<unsigned>();
1012
1013  switch (Constraint[0]) {
1014  default: break;
1015  case 'r':
1016    return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3,
1017                                 SP::L4, SP::L5, SP::L6, SP::L7,
1018                                 SP::I0, SP::I1, SP::I2, SP::I3,
1019                                 SP::I4, SP::I5,
1020                                 SP::O0, SP::O1, SP::O2, SP::O3,
1021                                 SP::O4, SP::O5, SP::O7, 0);
1022  }
1023
1024  return std::vector<unsigned>();
1025}
1026
1027bool
1028SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1029  // The Sparc target isn't yet aware of offsets.
1030  return false;
1031}
1032