SparcISelLowering.cpp revision ce31910eae5bd4896fa6c27798e7b26885691d3b
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the interfaces that Sparc uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
15#include "SparcISelLowering.h"
16#include "SparcTargetMachine.h"
17#include "llvm/Function.h"
18#include "llvm/CodeGen/CallingConvLower.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineRegisterInfo.h"
23#include "llvm/CodeGen/SelectionDAG.h"
24#include "llvm/Target/TargetLoweringObjectFile.h"
25#include "llvm/ADT/VectorExtras.h"
26#include "llvm/Support/ErrorHandling.h"
27using namespace llvm;
28
29
30//===----------------------------------------------------------------------===//
31// Calling Convention Implementation
32//===----------------------------------------------------------------------===//
33
34#include "SparcGenCallingConv.inc"
35
36SDValue
37SparcTargetLowering::LowerReturn(SDValue Chain,
38                                 CallingConv::ID CallConv, bool isVarArg,
39                                 const SmallVectorImpl<ISD::OutputArg> &Outs,
40                                 DebugLoc dl, SelectionDAG &DAG) {
41
42  // CCValAssign - represent the assignment of the return value to locations.
43  SmallVector<CCValAssign, 16> RVLocs;
44
45  // CCState - Info about the registers and stack slot.
46  CCState CCInfo(CallConv, isVarArg, DAG.getTarget(),
47                 RVLocs, *DAG.getContext());
48
49  // Analize return values.
50  CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
51
52  // If this is the first return lowered for this function, add the regs to the
53  // liveout set for the function.
54  if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
55    for (unsigned i = 0; i != RVLocs.size(); ++i)
56      if (RVLocs[i].isRegLoc())
57        DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
58  }
59
60  SDValue Flag;
61
62  // Copy the result values into the output registers.
63  for (unsigned i = 0; i != RVLocs.size(); ++i) {
64    CCValAssign &VA = RVLocs[i];
65    assert(VA.isRegLoc() && "Can only return in registers!");
66
67    Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
68                             Outs[i].Val, Flag);
69
70    // Guarantee that all emitted copies are stuck together with flags.
71    Flag = Chain.getValue(1);
72  }
73
74  if (Flag.getNode())
75    return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
76  return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain);
77}
78
79/// LowerFormalArguments - V8 uses a very simple ABI, where all values are
80/// passed in either one or two GPRs, including FP values.  TODO: we should
81/// pass FP values in FP registers for fastcc functions.
82SDValue
83SparcTargetLowering::LowerFormalArguments(SDValue Chain,
84                                          CallingConv::ID CallConv, bool isVarArg,
85                                          const SmallVectorImpl<ISD::InputArg>
86                                            &Ins,
87                                          DebugLoc dl, SelectionDAG &DAG,
88                                          SmallVectorImpl<SDValue> &InVals) {
89
90  MachineFunction &MF = DAG.getMachineFunction();
91  MachineRegisterInfo &RegInfo = MF.getRegInfo();
92
93  // Assign locations to all of the incoming arguments.
94  SmallVector<CCValAssign, 16> ArgLocs;
95  CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
96                 ArgLocs, *DAG.getContext());
97  CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32);
98
99  static const unsigned ArgRegs[] = {
100    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
101  };
102  const unsigned *CurArgReg = ArgRegs, *ArgRegEnd = ArgRegs+6;
103  unsigned ArgOffset = 68;
104
105  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
106    SDValue ArgValue;
107    CCValAssign &VA = ArgLocs[i];
108    // FIXME: We ignore the register assignments of AnalyzeFormalArguments
109    // because it doesn't know how to split a double into two i32 registers.
110    EVT ObjectVT = VA.getValVT();
111    switch (ObjectVT.getSimpleVT().SimpleTy) {
112    default: llvm_unreachable("Unhandled argument type!");
113    case MVT::i1:
114    case MVT::i8:
115    case MVT::i16:
116    case MVT::i32:
117      if (!Ins[i].Used) {                  // Argument is dead.
118        if (CurArgReg < ArgRegEnd) ++CurArgReg;
119        InVals.push_back(DAG.getUNDEF(ObjectVT));
120      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
121        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
122        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
123        SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
124        if (ObjectVT != MVT::i32) {
125          unsigned AssertOp = ISD::AssertSext;
126          Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg,
127                            DAG.getValueType(ObjectVT));
128          Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg);
129        }
130        InVals.push_back(Arg);
131      } else {
132        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
133        SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
134        SDValue Load;
135        if (ObjectVT == MVT::i32) {
136          Load = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0);
137        } else {
138          ISD::LoadExtType LoadOp = ISD::SEXTLOAD;
139
140          // Sparc is big endian, so add an offset based on the ObjectVT.
141          unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8);
142          FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr,
143                              DAG.getConstant(Offset, MVT::i32));
144          Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr,
145                                NULL, 0, ObjectVT);
146          Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load);
147        }
148        InVals.push_back(Load);
149      }
150
151      ArgOffset += 4;
152      break;
153    case MVT::f32:
154      if (!Ins[i].Used) {                  // Argument is dead.
155        if (CurArgReg < ArgRegEnd) ++CurArgReg;
156        InVals.push_back(DAG.getUNDEF(ObjectVT));
157      } else if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
158        // FP value is passed in an integer register.
159        unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
160        MF.getRegInfo().addLiveIn(*CurArgReg++, VReg);
161        SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
162
163        Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg);
164        InVals.push_back(Arg);
165      } else {
166        int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
167        SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
168        SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr, NULL, 0);
169        InVals.push_back(Load);
170      }
171      ArgOffset += 4;
172      break;
173
174    case MVT::i64:
175    case MVT::f64:
176      if (!Ins[i].Used) {                // Argument is dead.
177        if (CurArgReg < ArgRegEnd) ++CurArgReg;
178        if (CurArgReg < ArgRegEnd) ++CurArgReg;
179        InVals.push_back(DAG.getUNDEF(ObjectVT));
180      } else {
181        SDValue HiVal;
182        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
183          unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
184          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi);
185          HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32);
186        } else {
187          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
188          SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
189          HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0);
190        }
191
192        SDValue LoVal;
193        if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
194          unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
195          MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo);
196          LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, MVT::i32);
197        } else {
198          int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
199          SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
200          LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0);
201        }
202
203        // Compose the two halves together into an i64 unit.
204        SDValue WholeValue =
205          DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal);
206
207        // If we want a double, do a bit convert.
208        if (ObjectVT == MVT::f64)
209          WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue);
210
211        InVals.push_back(WholeValue);
212      }
213      ArgOffset += 8;
214      break;
215    }
216  }
217
218  // Store remaining ArgRegs to the stack if this is a varargs function.
219  if (isVarArg) {
220    // Remember the vararg offset for the va_start implementation.
221    VarArgsFrameOffset = ArgOffset;
222
223    std::vector<SDValue> OutChains;
224
225    for (; CurArgReg != ArgRegEnd; ++CurArgReg) {
226      unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
227      MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
228      SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
229
230      int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
231      SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
232
233      OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0));
234      ArgOffset += 4;
235    }
236
237    if (!OutChains.empty()) {
238      OutChains.push_back(Chain);
239      Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
240                          &OutChains[0], OutChains.size());
241    }
242  }
243
244  return Chain;
245}
246
247SDValue
248SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
249                               CallingConv::ID CallConv, bool isVarArg,
250                               bool isTailCall,
251                               const SmallVectorImpl<ISD::OutputArg> &Outs,
252                               const SmallVectorImpl<ISD::InputArg> &Ins,
253                               DebugLoc dl, SelectionDAG &DAG,
254                               SmallVectorImpl<SDValue> &InVals) {
255
256#if 0
257  // Analyze operands of the call, assigning locations to each operand.
258  SmallVector<CCValAssign, 16> ArgLocs;
259  CCState CCInfo(CallConv, isVarArg, DAG.getTarget(), ArgLocs);
260  CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32);
261
262  // Get the size of the outgoing arguments stack space requirement.
263  unsigned ArgsSize = CCInfo.getNextStackOffset();
264  // FIXME: We can't use this until f64 is known to take two GPRs.
265#else
266  (void)CC_Sparc32;
267
268  // Count the size of the outgoing arguments.
269  unsigned ArgsSize = 0;
270  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
271    switch (Outs[i].Val.getValueType().getSimpleVT().SimpleTy) {
272      default: llvm_unreachable("Unknown value type!");
273      case MVT::i1:
274      case MVT::i8:
275      case MVT::i16:
276      case MVT::i32:
277      case MVT::f32:
278        ArgsSize += 4;
279        break;
280      case MVT::i64:
281      case MVT::f64:
282        ArgsSize += 8;
283        break;
284    }
285  }
286  if (ArgsSize > 4*6)
287    ArgsSize -= 4*6;    // Space for first 6 arguments is prereserved.
288  else
289    ArgsSize = 0;
290#endif
291
292  // Keep stack frames 8-byte aligned.
293  ArgsSize = (ArgsSize+7) & ~7;
294
295  Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true));
296
297  SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
298  SmallVector<SDValue, 8> MemOpChains;
299
300#if 0
301  // Walk the register/memloc assignments, inserting copies/loads.
302  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
303    CCValAssign &VA = ArgLocs[i];
304    SDValue Arg = Outs[i].Val;
305
306    // Promote the value if needed.
307    switch (VA.getLocInfo()) {
308    default: llvm_unreachable("Unknown loc info!");
309    case CCValAssign::Full: break;
310    case CCValAssign::SExt:
311      Arg = DAG.getNode(ISD::SIGN_EXTEND, VA.getLocVT(), Arg);
312      break;
313    case CCValAssign::ZExt:
314      Arg = DAG.getNode(ISD::ZERO_EXTEND, VA.getLocVT(), Arg);
315      break;
316    case CCValAssign::AExt:
317      Arg = DAG.getNode(ISD::ANY_EXTEND, VA.getLocVT(), Arg);
318      break;
319    }
320
321    // Arguments that can be passed on register must be kept at
322    // RegsToPass vector
323    if (VA.isRegLoc()) {
324      RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
325      continue;
326    }
327
328    assert(VA.isMemLoc());
329
330    // Create a store off the stack pointer for this argument.
331    SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
332    // FIXME: VERIFY THAT 68 IS RIGHT.
333    SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68);
334    PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
335    MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
336  }
337
338#else
339  static const unsigned ArgRegs[] = {
340    SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5
341  };
342  unsigned ArgOffset = 68;
343
344  for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
345    SDValue Val = Outs[i].Val;
346    EVT ObjectVT = Val.getValueType();
347    SDValue ValToStore(0, 0);
348    unsigned ObjSize;
349    switch (ObjectVT.getSimpleVT().SimpleTy) {
350    default: llvm_unreachable("Unhandled argument type!");
351    case MVT::i32:
352      ObjSize = 4;
353
354      if (RegsToPass.size() >= 6) {
355        ValToStore = Val;
356      } else {
357        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
358      }
359      break;
360    case MVT::f32:
361      ObjSize = 4;
362      if (RegsToPass.size() >= 6) {
363        ValToStore = Val;
364      } else {
365        // Convert this to a FP value in an int reg.
366        Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val);
367        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val));
368      }
369      break;
370    case MVT::f64: {
371      ObjSize = 8;
372      if (RegsToPass.size() >= 6) {
373        ValToStore = Val;    // Whole thing is passed in memory.
374        break;
375      }
376
377      // Break into top and bottom parts by storing to the stack and loading
378      // out the parts as integers.  Top part goes in a reg.
379      SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32);
380      SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
381                                   Val, StackPtr, NULL, 0);
382      // Sparc is big-endian, so the high part comes first.
383      SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
384      // Increment the pointer to the other half.
385      StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr,
386                             DAG.getIntPtrConstant(4));
387      // Load the low part.
388      SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0);
389
390      RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
391
392      if (RegsToPass.size() >= 6) {
393        ValToStore = Lo;
394        ArgOffset += 4;
395        ObjSize = 4;
396      } else {
397        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
398      }
399      break;
400    }
401    case MVT::i64: {
402      ObjSize = 8;
403      if (RegsToPass.size() >= 6) {
404        ValToStore = Val;    // Whole thing is passed in memory.
405        break;
406      }
407
408      // Split the value into top and bottom part.  Top part goes in a reg.
409      SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
410                                 DAG.getConstant(1, MVT::i32));
411      SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val,
412                                 DAG.getConstant(0, MVT::i32));
413      RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi));
414
415      if (RegsToPass.size() >= 6) {
416        ValToStore = Lo;
417        ArgOffset += 4;
418        ObjSize = 4;
419      } else {
420        RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Lo));
421      }
422      break;
423    }
424    }
425
426    if (ValToStore.getNode()) {
427      SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32);
428      SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32);
429      PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff);
430      MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore,
431                                         PtrOff, NULL, 0));
432    }
433    ArgOffset += ObjSize;
434  }
435#endif
436
437  // Emit all stores, make sure the occur before any copies into physregs.
438  if (!MemOpChains.empty())
439    Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
440                        &MemOpChains[0], MemOpChains.size());
441
442  // Build a sequence of copy-to-reg nodes chained together with token
443  // chain and flag operands which copy the outgoing args into registers.
444  // The InFlag in necessary since all emited instructions must be
445  // stuck together.
446  SDValue InFlag;
447  for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
448    unsigned Reg = RegsToPass[i].first;
449    // Remap I0->I7 -> O0->O7.
450    if (Reg >= SP::I0 && Reg <= SP::I7)
451      Reg = Reg-SP::I0+SP::O0;
452
453    Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag);
454    InFlag = Chain.getValue(1);
455  }
456
457  // If the callee is a GlobalAddress node (quite common, every direct call is)
458  // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
459  // Likewise ExternalSymbol -> TargetExternalSymbol.
460  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
461    Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
462  else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
463    Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
464
465  std::vector<EVT> NodeTys;
466  NodeTys.push_back(MVT::Other);   // Returns a chain
467  NodeTys.push_back(MVT::Flag);    // Returns a flag for retval copy to use.
468  SDValue Ops[] = { Chain, Callee, InFlag };
469  Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2);
470  InFlag = Chain.getValue(1);
471
472  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true),
473                             DAG.getIntPtrConstant(0, true), InFlag);
474  InFlag = Chain.getValue(1);
475
476  // Assign locations to each value returned by this call.
477  SmallVector<CCValAssign, 16> RVLocs;
478  CCState RVInfo(CallConv, isVarArg, DAG.getTarget(),
479                 RVLocs, *DAG.getContext());
480
481  RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32);
482
483  // Copy all of the result registers out of their specified physreg.
484  for (unsigned i = 0; i != RVLocs.size(); ++i) {
485    unsigned Reg = RVLocs[i].getLocReg();
486
487    // Remap I0->I7 -> O0->O7.
488    if (Reg >= SP::I0 && Reg <= SP::I7)
489      Reg = Reg-SP::I0+SP::O0;
490
491    Chain = DAG.getCopyFromReg(Chain, dl, Reg,
492                               RVLocs[i].getValVT(), InFlag).getValue(1);
493    InFlag = Chain.getValue(2);
494    InVals.push_back(Chain.getValue(0));
495  }
496
497  return Chain;
498}
499
500
501
502//===----------------------------------------------------------------------===//
503// TargetLowering Implementation
504//===----------------------------------------------------------------------===//
505
506/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC
507/// condition.
508static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) {
509  switch (CC) {
510  default: llvm_unreachable("Unknown integer condition code!");
511  case ISD::SETEQ:  return SPCC::ICC_E;
512  case ISD::SETNE:  return SPCC::ICC_NE;
513  case ISD::SETLT:  return SPCC::ICC_L;
514  case ISD::SETGT:  return SPCC::ICC_G;
515  case ISD::SETLE:  return SPCC::ICC_LE;
516  case ISD::SETGE:  return SPCC::ICC_GE;
517  case ISD::SETULT: return SPCC::ICC_CS;
518  case ISD::SETULE: return SPCC::ICC_LEU;
519  case ISD::SETUGT: return SPCC::ICC_GU;
520  case ISD::SETUGE: return SPCC::ICC_CC;
521  }
522}
523
524/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC
525/// FCC condition.
526static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
527  switch (CC) {
528  default: llvm_unreachable("Unknown fp condition code!");
529  case ISD::SETEQ:
530  case ISD::SETOEQ: return SPCC::FCC_E;
531  case ISD::SETNE:
532  case ISD::SETUNE: return SPCC::FCC_NE;
533  case ISD::SETLT:
534  case ISD::SETOLT: return SPCC::FCC_L;
535  case ISD::SETGT:
536  case ISD::SETOGT: return SPCC::FCC_G;
537  case ISD::SETLE:
538  case ISD::SETOLE: return SPCC::FCC_LE;
539  case ISD::SETGE:
540  case ISD::SETOGE: return SPCC::FCC_GE;
541  case ISD::SETULT: return SPCC::FCC_UL;
542  case ISD::SETULE: return SPCC::FCC_ULE;
543  case ISD::SETUGT: return SPCC::FCC_UG;
544  case ISD::SETUGE: return SPCC::FCC_UGE;
545  case ISD::SETUO:  return SPCC::FCC_U;
546  case ISD::SETO:   return SPCC::FCC_O;
547  case ISD::SETONE: return SPCC::FCC_LG;
548  case ISD::SETUEQ: return SPCC::FCC_UE;
549  }
550}
551
552SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
553  : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
554
555  // Set up the register classes.
556  addRegisterClass(MVT::i32, SP::IntRegsRegisterClass);
557  addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
558  addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
559
560  // Turn FP extload into load/fextend
561  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
562  // Sparc doesn't have i1 sign extending load
563  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
564  // Turn FP truncstore into trunc + store.
565  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
566
567  // Custom legalize GlobalAddress nodes into LO/HI parts.
568  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
569  setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
570  setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
571
572  // Sparc doesn't have sext_inreg, replace them with shl/sra
573  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
574  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand);
575  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
576
577  // Sparc has no REM or DIVREM operations.
578  setOperationAction(ISD::UREM, MVT::i32, Expand);
579  setOperationAction(ISD::SREM, MVT::i32, Expand);
580  setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
581  setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
582
583  // Custom expand fp<->sint
584  setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
585  setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
586
587  // Expand fp<->uint
588  setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
589  setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
590
591  setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
592  setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
593
594  // Sparc has no select or setcc: expand to SELECT_CC.
595  setOperationAction(ISD::SELECT, MVT::i32, Expand);
596  setOperationAction(ISD::SELECT, MVT::f32, Expand);
597  setOperationAction(ISD::SELECT, MVT::f64, Expand);
598  setOperationAction(ISD::SETCC, MVT::i32, Expand);
599  setOperationAction(ISD::SETCC, MVT::f32, Expand);
600  setOperationAction(ISD::SETCC, MVT::f64, Expand);
601
602  // Sparc doesn't have BRCOND either, it has BR_CC.
603  setOperationAction(ISD::BRCOND, MVT::Other, Expand);
604  setOperationAction(ISD::BRIND, MVT::Other, Expand);
605  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
606  setOperationAction(ISD::BR_CC, MVT::i32, Custom);
607  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
608  setOperationAction(ISD::BR_CC, MVT::f64, Custom);
609
610  setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
611  setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
612  setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
613
614  // SPARC has no intrinsics for these particular operations.
615  setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
616
617  setOperationAction(ISD::FSIN , MVT::f64, Expand);
618  setOperationAction(ISD::FCOS , MVT::f64, Expand);
619  setOperationAction(ISD::FREM , MVT::f64, Expand);
620  setOperationAction(ISD::FSIN , MVT::f32, Expand);
621  setOperationAction(ISD::FCOS , MVT::f32, Expand);
622  setOperationAction(ISD::FREM , MVT::f32, Expand);
623  setOperationAction(ISD::CTPOP, MVT::i32, Expand);
624  setOperationAction(ISD::CTTZ , MVT::i32, Expand);
625  setOperationAction(ISD::CTLZ , MVT::i32, Expand);
626  setOperationAction(ISD::ROTL , MVT::i32, Expand);
627  setOperationAction(ISD::ROTR , MVT::i32, Expand);
628  setOperationAction(ISD::BSWAP, MVT::i32, Expand);
629  setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
630  setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
631  setOperationAction(ISD::FPOW , MVT::f64, Expand);
632  setOperationAction(ISD::FPOW , MVT::f32, Expand);
633
634  setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
635  setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
636  setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
637
638  // FIXME: Sparc provides these multiplies, but we don't have them yet.
639  setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
640  setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
641
642  // We don't have line number support yet.
643  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
644  setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
645  setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
646  setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
647
648  // VASTART needs to be custom lowered to use the VarArgsFrameIndex.
649  setOperationAction(ISD::VASTART           , MVT::Other, Custom);
650  // VAARG needs to be lowered to not do unaligned accesses for doubles.
651  setOperationAction(ISD::VAARG             , MVT::Other, Custom);
652
653  // Use the default implementation.
654  setOperationAction(ISD::VACOPY            , MVT::Other, Expand);
655  setOperationAction(ISD::VAEND             , MVT::Other, Expand);
656  setOperationAction(ISD::STACKSAVE         , MVT::Other, Expand);
657  setOperationAction(ISD::STACKRESTORE      , MVT::Other, Expand);
658  setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32  , Custom);
659
660  // No debug info support yet.
661  setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
662  setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand);
663  setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
664
665  setStackPointerRegisterToSaveRestore(SP::O6);
666
667  if (TM.getSubtarget<SparcSubtarget>().isV9())
668    setOperationAction(ISD::CTPOP, MVT::i32, Legal);
669
670  computeRegisterProperties();
671}
672
673const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
674  switch (Opcode) {
675  default: return 0;
676  case SPISD::CMPICC:     return "SPISD::CMPICC";
677  case SPISD::CMPFCC:     return "SPISD::CMPFCC";
678  case SPISD::BRICC:      return "SPISD::BRICC";
679  case SPISD::BRFCC:      return "SPISD::BRFCC";
680  case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC";
681  case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC";
682  case SPISD::Hi:         return "SPISD::Hi";
683  case SPISD::Lo:         return "SPISD::Lo";
684  case SPISD::FTOI:       return "SPISD::FTOI";
685  case SPISD::ITOF:       return "SPISD::ITOF";
686  case SPISD::CALL:       return "SPISD::CALL";
687  case SPISD::RET_FLAG:   return "SPISD::RET_FLAG";
688  }
689}
690
691/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
692/// be zero. Op is expected to be a target specific node. Used by DAG
693/// combiner.
694void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
695                                                         const APInt &Mask,
696                                                         APInt &KnownZero,
697                                                         APInt &KnownOne,
698                                                         const SelectionDAG &DAG,
699                                                         unsigned Depth) const {
700  APInt KnownZero2, KnownOne2;
701  KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);   // Don't know anything.
702
703  switch (Op.getOpcode()) {
704  default: break;
705  case SPISD::SELECT_ICC:
706  case SPISD::SELECT_FCC:
707    DAG.ComputeMaskedBits(Op.getOperand(1), Mask, KnownZero, KnownOne,
708                          Depth+1);
709    DAG.ComputeMaskedBits(Op.getOperand(0), Mask, KnownZero2, KnownOne2,
710                          Depth+1);
711    assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
712    assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
713
714    // Only known if known in both the LHS and RHS.
715    KnownOne &= KnownOne2;
716    KnownZero &= KnownZero2;
717    break;
718  }
719}
720
721// Look at LHS/RHS/CC and see if they are a lowered setcc instruction.  If so
722// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition.
723static void LookThroughSetCC(SDValue &LHS, SDValue &RHS,
724                             ISD::CondCode CC, unsigned &SPCC) {
725  if (isa<ConstantSDNode>(RHS) &&
726      cast<ConstantSDNode>(RHS)->getZExtValue() == 0 &&
727      CC == ISD::SETNE &&
728      ((LHS.getOpcode() == SPISD::SELECT_ICC &&
729        LHS.getOperand(3).getOpcode() == SPISD::CMPICC) ||
730       (LHS.getOpcode() == SPISD::SELECT_FCC &&
731        LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) &&
732      isa<ConstantSDNode>(LHS.getOperand(0)) &&
733      isa<ConstantSDNode>(LHS.getOperand(1)) &&
734      cast<ConstantSDNode>(LHS.getOperand(0))->getZExtValue() == 1 &&
735      cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() == 0) {
736    SDValue CMPCC = LHS.getOperand(3);
737    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
738    LHS = CMPCC.getOperand(0);
739    RHS = CMPCC.getOperand(1);
740  }
741}
742
743SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op,
744                                                SelectionDAG &DAG) {
745  GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
746  // FIXME there isn't really any debug info here
747  DebugLoc dl = Op.getDebugLoc();
748  SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
749  SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA);
750  SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA);
751
752  if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
753    return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
754
755  SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
756                                   getPointerTy());
757  SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
758  SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
759                                GlobalBase, RelAddr);
760  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
761                     AbsAddr, NULL, 0);
762}
763
764SDValue SparcTargetLowering::LowerConstantPool(SDValue Op,
765                                               SelectionDAG &DAG) {
766  ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
767  // FIXME there isn't really any debug info here
768  DebugLoc dl = Op.getDebugLoc();
769  Constant *C = N->getConstVal();
770  SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment());
771  SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP);
772  SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP);
773  if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
774    return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
775
776  SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, dl,
777                                   getPointerTy());
778  SDValue RelAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi);
779  SDValue AbsAddr = DAG.getNode(ISD::ADD, dl, MVT::i32,
780                                GlobalBase, RelAddr);
781  return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
782                     AbsAddr, NULL, 0);
783}
784
785static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
786  DebugLoc dl = Op.getDebugLoc();
787  // Convert the fp value to integer in an FP register.
788  assert(Op.getValueType() == MVT::i32);
789  Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0));
790  return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
791}
792
793static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
794  DebugLoc dl = Op.getDebugLoc();
795  assert(Op.getOperand(0).getValueType() == MVT::i32);
796  SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0));
797  // Convert the int value to FP in an FP register.
798  return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp);
799}
800
801static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
802  SDValue Chain = Op.getOperand(0);
803  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
804  SDValue LHS = Op.getOperand(2);
805  SDValue RHS = Op.getOperand(3);
806  SDValue Dest = Op.getOperand(4);
807  DebugLoc dl = Op.getDebugLoc();
808  unsigned Opc, SPCC = ~0U;
809
810  // If this is a br_cc of a "setcc", and if the setcc got lowered into
811  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
812  LookThroughSetCC(LHS, RHS, CC, SPCC);
813
814  // Get the condition flag.
815  SDValue CompareFlag;
816  if (LHS.getValueType() == MVT::i32) {
817    std::vector<EVT> VTs;
818    VTs.push_back(MVT::i32);
819    VTs.push_back(MVT::Flag);
820    SDValue Ops[2] = { LHS, RHS };
821    CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
822    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
823    Opc = SPISD::BRICC;
824  } else {
825    CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
826    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
827    Opc = SPISD::BRFCC;
828  }
829  return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest,
830                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
831}
832
833static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
834  SDValue LHS = Op.getOperand(0);
835  SDValue RHS = Op.getOperand(1);
836  ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
837  SDValue TrueVal = Op.getOperand(2);
838  SDValue FalseVal = Op.getOperand(3);
839  DebugLoc dl = Op.getDebugLoc();
840  unsigned Opc, SPCC = ~0U;
841
842  // If this is a select_cc of a "setcc", and if the setcc got lowered into
843  // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values.
844  LookThroughSetCC(LHS, RHS, CC, SPCC);
845
846  SDValue CompareFlag;
847  if (LHS.getValueType() == MVT::i32) {
848    std::vector<EVT> VTs;
849    VTs.push_back(LHS.getValueType());   // subcc returns a value
850    VTs.push_back(MVT::Flag);
851    SDValue Ops[2] = { LHS, RHS };
852    CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1);
853    Opc = SPISD::SELECT_ICC;
854    if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
855  } else {
856    CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS);
857    Opc = SPISD::SELECT_FCC;
858    if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC);
859  }
860  return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal,
861                     DAG.getConstant(SPCC, MVT::i32), CompareFlag);
862}
863
864static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
865                              SparcTargetLowering &TLI) {
866  // vastart just stores the address of the VarArgsFrameIndex slot into the
867  // memory location argument.
868  DebugLoc dl = Op.getDebugLoc();
869  SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32,
870                                 DAG.getRegister(SP::I6, MVT::i32),
871                                 DAG.getConstant(TLI.getVarArgsFrameOffset(),
872                                                 MVT::i32));
873  const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
874  return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0);
875}
876
877static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) {
878  SDNode *Node = Op.getNode();
879  EVT VT = Node->getValueType(0);
880  SDValue InChain = Node->getOperand(0);
881  SDValue VAListPtr = Node->getOperand(1);
882  const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
883  DebugLoc dl = Node->getDebugLoc();
884  SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0);
885  // Increment the pointer, VAList, to the next vaarg
886  SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList,
887                                  DAG.getConstant(VT.getSizeInBits()/8,
888                                                  MVT::i32));
889  // Store the incremented VAList to the legalized pointer
890  InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr,
891                         VAListPtr, SV, 0);
892  // Load the actual argument out of the pointer VAList, unless this is an
893  // f64 load.
894  if (VT != MVT::f64)
895    return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0);
896
897  // Otherwise, load it as i64, then do a bitconvert.
898  SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0);
899
900  // Bit-Convert the value to f64.
901  SDValue Ops[2] = {
902    DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V),
903    V.getValue(1)
904  };
905  return DAG.getMergeValues(Ops, 2, dl);
906}
907
908static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) {
909  SDValue Chain = Op.getOperand(0);  // Legalize the chain.
910  SDValue Size  = Op.getOperand(1);  // Legalize the size.
911  DebugLoc dl = Op.getDebugLoc();
912
913  unsigned SPReg = SP::O6;
914  SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32);
915  SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value
916  Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP);    // Output chain
917
918  // The resultant pointer is actually 16 words from the bottom of the stack,
919  // to provide a register spill area.
920  SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
921                                 DAG.getConstant(96, MVT::i32));
922  SDValue Ops[2] = { NewVal, Chain };
923  return DAG.getMergeValues(Ops, 2, dl);
924}
925
926
927SDValue SparcTargetLowering::
928LowerOperation(SDValue Op, SelectionDAG &DAG) {
929  switch (Op.getOpcode()) {
930  default: llvm_unreachable("Should not custom lower this!");
931  // Frame & Return address.  Currently unimplemented
932  case ISD::RETURNADDR: return SDValue();
933  case ISD::FRAMEADDR:  return SDValue();
934  case ISD::GlobalTLSAddress:
935    llvm_unreachable("TLS not implemented for Sparc.");
936  case ISD::GlobalAddress:      return LowerGlobalAddress(Op, DAG);
937  case ISD::ConstantPool:       return LowerConstantPool(Op, DAG);
938  case ISD::FP_TO_SINT:         return LowerFP_TO_SINT(Op, DAG);
939  case ISD::SINT_TO_FP:         return LowerSINT_TO_FP(Op, DAG);
940  case ISD::BR_CC:              return LowerBR_CC(Op, DAG);
941  case ISD::SELECT_CC:          return LowerSELECT_CC(Op, DAG);
942  case ISD::VASTART:            return LowerVASTART(Op, DAG, *this);
943  case ISD::VAARG:              return LowerVAARG(Op, DAG);
944  case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
945  }
946}
947
948MachineBasicBlock *
949SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
950                                                 MachineBasicBlock *BB,
951                   DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
952  const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
953  unsigned BROpcode;
954  unsigned CC;
955  DebugLoc dl = MI->getDebugLoc();
956  // Figure out the conditional branch opcode to use for this select_cc.
957  switch (MI->getOpcode()) {
958  default: llvm_unreachable("Unknown SELECT_CC!");
959  case SP::SELECT_CC_Int_ICC:
960  case SP::SELECT_CC_FP_ICC:
961  case SP::SELECT_CC_DFP_ICC:
962    BROpcode = SP::BCOND;
963    break;
964  case SP::SELECT_CC_Int_FCC:
965  case SP::SELECT_CC_FP_FCC:
966  case SP::SELECT_CC_DFP_FCC:
967    BROpcode = SP::FBCOND;
968    break;
969  }
970
971  CC = (SPCC::CondCodes)MI->getOperand(3).getImm();
972
973  // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
974  // control-flow pattern.  The incoming instruction knows the destination vreg
975  // to set, the condition code register to branch on, the true/false values to
976  // select between, and a branch opcode to use.
977  const BasicBlock *LLVM_BB = BB->getBasicBlock();
978  MachineFunction::iterator It = BB;
979  ++It;
980
981  //  thisMBB:
982  //  ...
983  //   TrueVal = ...
984  //   [f]bCC copy1MBB
985  //   fallthrough --> copy0MBB
986  MachineBasicBlock *thisMBB = BB;
987  MachineFunction *F = BB->getParent();
988  MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
989  MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
990  BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
991  F->insert(It, copy0MBB);
992  F->insert(It, sinkMBB);
993  // Update machine-CFG edges by first adding all successors of the current
994  // block to the new block which will contain the Phi node for the select.
995  // Also inform sdisel of the edge changes.
996  for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
997         E = BB->succ_end(); I != E; ++I) {
998    EM->insert(std::make_pair(*I, sinkMBB));
999    sinkMBB->addSuccessor(*I);
1000  }
1001  // Next, remove all successors of the current block, and add the true
1002  // and fallthrough blocks as its successors.
1003  while (!BB->succ_empty())
1004    BB->removeSuccessor(BB->succ_begin());
1005  // Next, add the true and fallthrough blocks as its successors.
1006  BB->addSuccessor(copy0MBB);
1007  BB->addSuccessor(sinkMBB);
1008
1009  //  copy0MBB:
1010  //   %FalseValue = ...
1011  //   # fallthrough to sinkMBB
1012  BB = copy0MBB;
1013
1014  // Update machine-CFG edges
1015  BB->addSuccessor(sinkMBB);
1016
1017  //  sinkMBB:
1018  //   %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1019  //  ...
1020  BB = sinkMBB;
1021  BuildMI(BB, dl, TII.get(SP::PHI), MI->getOperand(0).getReg())
1022    .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
1023    .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
1024
1025  F->DeleteMachineInstr(MI);   // The pseudo instruction is gone now.
1026  return BB;
1027}
1028
1029//===----------------------------------------------------------------------===//
1030//                         Sparc Inline Assembly Support
1031//===----------------------------------------------------------------------===//
1032
1033/// getConstraintType - Given a constraint letter, return the type of
1034/// constraint it is for this target.
1035SparcTargetLowering::ConstraintType
1036SparcTargetLowering::getConstraintType(const std::string &Constraint) const {
1037  if (Constraint.size() == 1) {
1038    switch (Constraint[0]) {
1039    default:  break;
1040    case 'r': return C_RegisterClass;
1041    }
1042  }
1043
1044  return TargetLowering::getConstraintType(Constraint);
1045}
1046
1047std::pair<unsigned, const TargetRegisterClass*>
1048SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
1049                                                  EVT VT) const {
1050  if (Constraint.size() == 1) {
1051    switch (Constraint[0]) {
1052    case 'r':
1053      return std::make_pair(0U, SP::IntRegsRegisterClass);
1054    }
1055  }
1056
1057  return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
1058}
1059
1060std::vector<unsigned> SparcTargetLowering::
1061getRegClassForInlineAsmConstraint(const std::string &Constraint,
1062                                  EVT VT) const {
1063  if (Constraint.size() != 1)
1064    return std::vector<unsigned>();
1065
1066  switch (Constraint[0]) {
1067  default: break;
1068  case 'r':
1069    return make_vector<unsigned>(SP::L0, SP::L1, SP::L2, SP::L3,
1070                                 SP::L4, SP::L5, SP::L6, SP::L7,
1071                                 SP::I0, SP::I1, SP::I2, SP::I3,
1072                                 SP::I4, SP::I5,
1073                                 SP::O0, SP::O1, SP::O2, SP::O3,
1074                                 SP::O4, SP::O5, SP::O7, 0);
1075  }
1076
1077  return std::vector<unsigned>();
1078}
1079
1080bool
1081SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1082  // The Sparc target isn't yet aware of offsets.
1083  return false;
1084}
1085
1086/// getFunctionAlignment - Return the Log2 alignment of this function.
1087unsigned SparcTargetLowering::getFunctionAlignment(const Function *) const {
1088  return 2;
1089}
1090