SparcISelLowering.cpp revision d9f88da7b329c54ccb0d2ebd3b3a4b0e4b1e2b06
1//===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file implements the interfaces that Sparc uses to lower LLVM code into a 11// selection DAG. 12// 13//===----------------------------------------------------------------------===// 14 15#include "SparcISelLowering.h" 16#include "SparcMachineFunctionInfo.h" 17#include "SparcTargetMachine.h" 18#include "MCTargetDesc/SparcBaseInfo.h" 19#include "llvm/CodeGen/CallingConvLower.h" 20#include "llvm/CodeGen/MachineFrameInfo.h" 21#include "llvm/CodeGen/MachineFunction.h" 22#include "llvm/CodeGen/MachineInstrBuilder.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/SelectionDAG.h" 25#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 26#include "llvm/IR/DerivedTypes.h" 27#include "llvm/IR/Function.h" 28#include "llvm/IR/Module.h" 29#include "llvm/Support/ErrorHandling.h" 30using namespace llvm; 31 32 33//===----------------------------------------------------------------------===// 34// Calling Convention Implementation 35//===----------------------------------------------------------------------===// 36 37static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT, 38 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 39 ISD::ArgFlagsTy &ArgFlags, CCState &State) 40{ 41 assert (ArgFlags.isSRet()); 42 43 //Assign SRet argument 44 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 45 0, 46 LocVT, LocInfo)); 47 return true; 48} 49 50static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT, 51 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 52 ISD::ArgFlagsTy &ArgFlags, CCState &State) 53{ 54 static const uint16_t RegList[] = { 55 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 56 }; 57 //Try to get first reg 58 if (unsigned Reg = State.AllocateReg(RegList, 6)) { 59 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 60 } else { 61 //Assign whole thing in stack 62 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 63 State.AllocateStack(8,4), 64 LocVT, LocInfo)); 65 return true; 66 } 67 68 //Try to get second reg 69 if (unsigned Reg = State.AllocateReg(RegList, 6)) 70 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 71 else 72 State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT, 73 State.AllocateStack(4,4), 74 LocVT, LocInfo)); 75 return true; 76} 77 78// Allocate a full-sized argument for the 64-bit ABI. 79static bool CC_Sparc64_Full(unsigned &ValNo, MVT &ValVT, 80 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 81 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 82 assert((LocVT == MVT::f32 || LocVT.getSizeInBits() == 64) && 83 "Can't handle non-64 bits locations"); 84 85 // Stack space is allocated for all arguments starting from [%fp+BIAS+128]. 86 unsigned Offset = State.AllocateStack(8, 8); 87 unsigned Reg = 0; 88 89 if (LocVT == MVT::i64 && Offset < 6*8) 90 // Promote integers to %i0-%i5. 91 Reg = SP::I0 + Offset/8; 92 else if (LocVT == MVT::f64 && Offset < 16*8) 93 // Promote doubles to %d0-%d30. (Which LLVM calls D0-D15). 94 Reg = SP::D0 + Offset/8; 95 else if (LocVT == MVT::f32 && Offset < 16*8) 96 // Promote floats to %f1, %f3, ... 97 Reg = SP::F1 + Offset/4; 98 99 // Promote to register when possible, otherwise use the stack slot. 100 if (Reg) { 101 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 102 return true; 103 } 104 105 // This argument goes on the stack in an 8-byte slot. 106 // When passing floats, LocVT is smaller than 8 bytes. Adjust the offset to 107 // the right-aligned float. The first 4 bytes of the stack slot are undefined. 108 if (LocVT == MVT::f32) 109 Offset += 4; 110 111 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 112 return true; 113} 114 115// Allocate a half-sized argument for the 64-bit ABI. 116// 117// This is used when passing { float, int } structs by value in registers. 118static bool CC_Sparc64_Half(unsigned &ValNo, MVT &ValVT, 119 MVT &LocVT, CCValAssign::LocInfo &LocInfo, 120 ISD::ArgFlagsTy &ArgFlags, CCState &State) { 121 assert(LocVT.getSizeInBits() == 32 && "Can't handle non-32 bits locations"); 122 unsigned Offset = State.AllocateStack(4, 4); 123 124 if (LocVT == MVT::f32 && Offset < 16*8) { 125 // Promote floats to %f0-%f31. 126 State.addLoc(CCValAssign::getReg(ValNo, ValVT, SP::F0 + Offset/4, 127 LocVT, LocInfo)); 128 return true; 129 } 130 131 if (LocVT == MVT::i32 && Offset < 6*8) { 132 // Promote integers to %i0-%i5, using half the register. 133 unsigned Reg = SP::I0 + Offset/8; 134 LocVT = MVT::i64; 135 LocInfo = CCValAssign::AExt; 136 137 // Set the Custom bit if this i32 goes in the high bits of a register. 138 if (Offset % 8 == 0) 139 State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, 140 LocVT, LocInfo)); 141 else 142 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 143 return true; 144 } 145 146 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 147 return true; 148} 149 150#include "SparcGenCallingConv.inc" 151 152// The calling conventions in SparcCallingConv.td are described in terms of the 153// callee's register window. This function translates registers to the 154// corresponding caller window %o register. 155static unsigned toCallerWindow(unsigned Reg) { 156 assert(SP::I0 + 7 == SP::I7 && SP::O0 + 7 == SP::O7 && "Unexpected enum"); 157 if (Reg >= SP::I0 && Reg <= SP::I7) 158 return Reg - SP::I0 + SP::O0; 159 return Reg; 160} 161 162SDValue 163SparcTargetLowering::LowerReturn(SDValue Chain, 164 CallingConv::ID CallConv, bool IsVarArg, 165 const SmallVectorImpl<ISD::OutputArg> &Outs, 166 const SmallVectorImpl<SDValue> &OutVals, 167 DebugLoc DL, SelectionDAG &DAG) const { 168 if (Subtarget->is64Bit()) 169 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 170 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); 171} 172 173SDValue 174SparcTargetLowering::LowerReturn_32(SDValue Chain, 175 CallingConv::ID CallConv, bool IsVarArg, 176 const SmallVectorImpl<ISD::OutputArg> &Outs, 177 const SmallVectorImpl<SDValue> &OutVals, 178 DebugLoc DL, SelectionDAG &DAG) const { 179 MachineFunction &MF = DAG.getMachineFunction(); 180 181 // CCValAssign - represent the assignment of the return value to locations. 182 SmallVector<CCValAssign, 16> RVLocs; 183 184 // CCState - Info about the registers and stack slot. 185 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 186 DAG.getTarget(), RVLocs, *DAG.getContext()); 187 188 // Analyze return values. 189 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32); 190 191 SDValue Flag; 192 SmallVector<SDValue, 4> RetOps(1, Chain); 193 // Make room for the return address offset. 194 RetOps.push_back(SDValue()); 195 196 // Copy the result values into the output registers. 197 for (unsigned i = 0; i != RVLocs.size(); ++i) { 198 CCValAssign &VA = RVLocs[i]; 199 assert(VA.isRegLoc() && "Can only return in registers!"); 200 201 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), 202 OutVals[i], Flag); 203 204 // Guarantee that all emitted copies are stuck together with flags. 205 Flag = Chain.getValue(1); 206 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 207 } 208 209 unsigned RetAddrOffset = 8; //Call Inst + Delay Slot 210 // If the function returns a struct, copy the SRetReturnReg to I0 211 if (MF.getFunction()->hasStructRetAttr()) { 212 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 213 unsigned Reg = SFI->getSRetReturnReg(); 214 if (!Reg) 215 llvm_unreachable("sret virtual register not created in the entry block"); 216 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 217 Chain = DAG.getCopyToReg(Chain, DL, SP::I0, Val, Flag); 218 Flag = Chain.getValue(1); 219 RetOps.push_back(DAG.getRegister(SP::I0, getPointerTy())); 220 RetAddrOffset = 12; // CallInst + Delay Slot + Unimp 221 } 222 223 RetOps[0] = Chain; // Update chain. 224 RetOps[1] = DAG.getConstant(RetAddrOffset, MVT::i32); 225 226 // Add the flag if we have it. 227 if (Flag.getNode()) 228 RetOps.push_back(Flag); 229 230 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 231 &RetOps[0], RetOps.size()); 232} 233 234// Lower return values for the 64-bit ABI. 235// Return values are passed the exactly the same way as function arguments. 236SDValue 237SparcTargetLowering::LowerReturn_64(SDValue Chain, 238 CallingConv::ID CallConv, bool IsVarArg, 239 const SmallVectorImpl<ISD::OutputArg> &Outs, 240 const SmallVectorImpl<SDValue> &OutVals, 241 DebugLoc DL, SelectionDAG &DAG) const { 242 // CCValAssign - represent the assignment of the return value to locations. 243 SmallVector<CCValAssign, 16> RVLocs; 244 245 // CCState - Info about the registers and stack slot. 246 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 247 DAG.getTarget(), RVLocs, *DAG.getContext()); 248 249 // Analyze return values. 250 CCInfo.AnalyzeReturn(Outs, CC_Sparc64); 251 252 SDValue Flag; 253 SmallVector<SDValue, 4> RetOps(1, Chain); 254 255 // The second operand on the return instruction is the return address offset. 256 // The return address is always %i7+8 with the 64-bit ABI. 257 RetOps.push_back(DAG.getConstant(8, MVT::i32)); 258 259 // Copy the result values into the output registers. 260 for (unsigned i = 0; i != RVLocs.size(); ++i) { 261 CCValAssign &VA = RVLocs[i]; 262 assert(VA.isRegLoc() && "Can only return in registers!"); 263 SDValue OutVal = OutVals[i]; 264 265 // Integer return values must be sign or zero extended by the callee. 266 switch (VA.getLocInfo()) { 267 case CCValAssign::SExt: 268 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); 269 break; 270 case CCValAssign::ZExt: 271 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); 272 break; 273 case CCValAssign::AExt: 274 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); 275 default: 276 break; 277 } 278 279 // The custom bit on an i32 return value indicates that it should be passed 280 // in the high bits of the register. 281 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 282 OutVal = DAG.getNode(ISD::SHL, DL, MVT::i64, OutVal, 283 DAG.getConstant(32, MVT::i32)); 284 285 // The next value may go in the low bits of the same register. 286 // Handle both at once. 287 if (i+1 < RVLocs.size() && RVLocs[i+1].getLocReg() == VA.getLocReg()) { 288 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, OutVals[i+1]); 289 OutVal = DAG.getNode(ISD::OR, DL, MVT::i64, OutVal, NV); 290 // Skip the next value, it's already done. 291 ++i; 292 } 293 } 294 295 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), OutVal, Flag); 296 297 // Guarantee that all emitted copies are stuck together with flags. 298 Flag = Chain.getValue(1); 299 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); 300 } 301 302 RetOps[0] = Chain; // Update chain. 303 304 // Add the flag if we have it. 305 if (Flag.getNode()) 306 RetOps.push_back(Flag); 307 308 return DAG.getNode(SPISD::RET_FLAG, DL, MVT::Other, 309 &RetOps[0], RetOps.size()); 310} 311 312SDValue SparcTargetLowering:: 313LowerFormalArguments(SDValue Chain, 314 CallingConv::ID CallConv, 315 bool IsVarArg, 316 const SmallVectorImpl<ISD::InputArg> &Ins, 317 DebugLoc DL, 318 SelectionDAG &DAG, 319 SmallVectorImpl<SDValue> &InVals) const { 320 if (Subtarget->is64Bit()) 321 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins, 322 DL, DAG, InVals); 323 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins, 324 DL, DAG, InVals); 325} 326 327/// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are 328/// passed in either one or two GPRs, including FP values. TODO: we should 329/// pass FP values in FP registers for fastcc functions. 330SDValue SparcTargetLowering:: 331LowerFormalArguments_32(SDValue Chain, 332 CallingConv::ID CallConv, 333 bool isVarArg, 334 const SmallVectorImpl<ISD::InputArg> &Ins, 335 DebugLoc dl, 336 SelectionDAG &DAG, 337 SmallVectorImpl<SDValue> &InVals) const { 338 MachineFunction &MF = DAG.getMachineFunction(); 339 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 340 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 341 342 // Assign locations to all of the incoming arguments. 343 SmallVector<CCValAssign, 16> ArgLocs; 344 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 345 getTargetMachine(), ArgLocs, *DAG.getContext()); 346 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc32); 347 348 const unsigned StackOffset = 92; 349 350 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 351 CCValAssign &VA = ArgLocs[i]; 352 353 if (i == 0 && Ins[i].Flags.isSRet()) { 354 //Get SRet from [%fp+64] 355 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, 64, true); 356 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 357 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 358 MachinePointerInfo(), 359 false, false, false, 0); 360 InVals.push_back(Arg); 361 continue; 362 } 363 364 if (VA.isRegLoc()) { 365 if (VA.needsCustom()) { 366 assert(VA.getLocVT() == MVT::f64); 367 unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 368 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); 369 SDValue HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); 370 371 assert(i+1 < e); 372 CCValAssign &NextVA = ArgLocs[++i]; 373 374 SDValue LoVal; 375 if (NextVA.isMemLoc()) { 376 int FrameIdx = MF.getFrameInfo()-> 377 CreateFixedObject(4, StackOffset+NextVA.getLocMemOffset(),true); 378 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 379 LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 380 MachinePointerInfo(), 381 false, false, false, 0); 382 } else { 383 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), 384 &SP::IntRegsRegClass); 385 LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32); 386 } 387 SDValue WholeValue = 388 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 389 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 390 InVals.push_back(WholeValue); 391 continue; 392 } 393 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 394 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); 395 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); 396 if (VA.getLocVT() == MVT::f32) 397 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); 398 else if (VA.getLocVT() != MVT::i32) { 399 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, 400 DAG.getValueType(VA.getLocVT())); 401 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); 402 } 403 InVals.push_back(Arg); 404 continue; 405 } 406 407 assert(VA.isMemLoc()); 408 409 unsigned Offset = VA.getLocMemOffset()+StackOffset; 410 411 if (VA.needsCustom()) { 412 assert(VA.getValVT() == MVT::f64); 413 //If it is double-word aligned, just load. 414 if (Offset % 8 == 0) { 415 int FI = MF.getFrameInfo()->CreateFixedObject(8, 416 Offset, 417 true); 418 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 419 SDValue Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 420 MachinePointerInfo(), 421 false,false, false, 0); 422 InVals.push_back(Load); 423 continue; 424 } 425 426 int FI = MF.getFrameInfo()->CreateFixedObject(4, 427 Offset, 428 true); 429 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 430 SDValue HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, 431 MachinePointerInfo(), 432 false, false, false, 0); 433 int FI2 = MF.getFrameInfo()->CreateFixedObject(4, 434 Offset+4, 435 true); 436 SDValue FIPtr2 = DAG.getFrameIndex(FI2, getPointerTy()); 437 438 SDValue LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr2, 439 MachinePointerInfo(), 440 false, false, false, 0); 441 442 SDValue WholeValue = 443 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); 444 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); 445 InVals.push_back(WholeValue); 446 continue; 447 } 448 449 int FI = MF.getFrameInfo()->CreateFixedObject(4, 450 Offset, 451 true); 452 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 453 SDValue Load ; 454 if (VA.getValVT() == MVT::i32 || VA.getValVT() == MVT::f32) { 455 Load = DAG.getLoad(VA.getValVT(), dl, Chain, FIPtr, 456 MachinePointerInfo(), 457 false, false, false, 0); 458 } else { 459 ISD::LoadExtType LoadOp = ISD::SEXTLOAD; 460 // Sparc is big endian, so add an offset based on the ObjectVT. 461 unsigned Offset = 4-std::max(1U, VA.getValVT().getSizeInBits()/8); 462 FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, 463 DAG.getConstant(Offset, MVT::i32)); 464 Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, 465 MachinePointerInfo(), 466 VA.getValVT(), false, false,0); 467 Load = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Load); 468 } 469 InVals.push_back(Load); 470 } 471 472 if (MF.getFunction()->hasStructRetAttr()) { 473 //Copy the SRet Argument to SRetReturnReg 474 SparcMachineFunctionInfo *SFI = MF.getInfo<SparcMachineFunctionInfo>(); 475 unsigned Reg = SFI->getSRetReturnReg(); 476 if (!Reg) { 477 Reg = MF.getRegInfo().createVirtualRegister(&SP::IntRegsRegClass); 478 SFI->setSRetReturnReg(Reg); 479 } 480 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 481 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 482 } 483 484 // Store remaining ArgRegs to the stack if this is a varargs function. 485 if (isVarArg) { 486 static const uint16_t ArgRegs[] = { 487 SP::I0, SP::I1, SP::I2, SP::I3, SP::I4, SP::I5 488 }; 489 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); 490 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; 491 unsigned ArgOffset = CCInfo.getNextStackOffset(); 492 if (NumAllocated == 6) 493 ArgOffset += StackOffset; 494 else { 495 assert(!ArgOffset); 496 ArgOffset = 68+4*NumAllocated; 497 } 498 499 // Remember the vararg offset for the va_start implementation. 500 FuncInfo->setVarArgsFrameOffset(ArgOffset); 501 502 std::vector<SDValue> OutChains; 503 504 for (; CurArgReg != ArgRegEnd; ++CurArgReg) { 505 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); 506 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); 507 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); 508 509 int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset, 510 true); 511 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); 512 513 OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, 514 MachinePointerInfo(), 515 false, false, 0)); 516 ArgOffset += 4; 517 } 518 519 if (!OutChains.empty()) { 520 OutChains.push_back(Chain); 521 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 522 &OutChains[0], OutChains.size()); 523 } 524 } 525 526 return Chain; 527} 528 529// Lower formal arguments for the 64 bit ABI. 530SDValue SparcTargetLowering:: 531LowerFormalArguments_64(SDValue Chain, 532 CallingConv::ID CallConv, 533 bool IsVarArg, 534 const SmallVectorImpl<ISD::InputArg> &Ins, 535 DebugLoc DL, 536 SelectionDAG &DAG, 537 SmallVectorImpl<SDValue> &InVals) const { 538 MachineFunction &MF = DAG.getMachineFunction(); 539 540 // Analyze arguments according to CC_Sparc64. 541 SmallVector<CCValAssign, 16> ArgLocs; 542 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), 543 getTargetMachine(), ArgLocs, *DAG.getContext()); 544 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64); 545 546 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 547 CCValAssign &VA = ArgLocs[i]; 548 if (VA.isRegLoc()) { 549 // This argument is passed in a register. 550 // All integer register arguments are promoted by the caller to i64. 551 552 // Create a virtual register for the promoted live-in value. 553 unsigned VReg = MF.addLiveIn(VA.getLocReg(), 554 getRegClassFor(VA.getLocVT())); 555 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); 556 557 // Get the high bits for i32 struct elements. 558 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 559 Arg = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), Arg, 560 DAG.getConstant(32, MVT::i32)); 561 562 // The caller promoted the argument, so insert an Assert?ext SDNode so we 563 // won't promote the value again in this function. 564 switch (VA.getLocInfo()) { 565 case CCValAssign::SExt: 566 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, 567 DAG.getValueType(VA.getValVT())); 568 break; 569 case CCValAssign::ZExt: 570 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, 571 DAG.getValueType(VA.getValVT())); 572 break; 573 default: 574 break; 575 } 576 577 // Truncate the register down to the argument type. 578 if (VA.isExtInLoc()) 579 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg); 580 581 InVals.push_back(Arg); 582 continue; 583 } 584 585 // The registers are exhausted. This argument was passed on the stack. 586 assert(VA.isMemLoc()); 587 // The CC_Sparc64_Full/Half functions compute stack offsets relative to the 588 // beginning of the arguments area at %fp+BIAS+128. 589 unsigned Offset = VA.getLocMemOffset() + 128; 590 unsigned ValSize = VA.getValVT().getSizeInBits() / 8; 591 // Adjust offset for extended arguments, SPARC is big-endian. 592 // The caller will have written the full slot with extended bytes, but we 593 // prefer our own extending loads. 594 if (VA.isExtInLoc()) 595 Offset += 8 - ValSize; 596 int FI = MF.getFrameInfo()->CreateFixedObject(ValSize, Offset, true); 597 InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, 598 DAG.getFrameIndex(FI, getPointerTy()), 599 MachinePointerInfo::getFixedStack(FI), 600 false, false, false, 0)); 601 } 602 return Chain; 603} 604 605SDValue 606SparcTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, 607 SmallVectorImpl<SDValue> &InVals) const { 608 if (Subtarget->is64Bit()) 609 return LowerCall_64(CLI, InVals); 610 return LowerCall_32(CLI, InVals); 611} 612 613// Lower a call for the 32-bit ABI. 614SDValue 615SparcTargetLowering::LowerCall_32(TargetLowering::CallLoweringInfo &CLI, 616 SmallVectorImpl<SDValue> &InVals) const { 617 SelectionDAG &DAG = CLI.DAG; 618 DebugLoc &dl = CLI.DL; 619 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs; 620 SmallVector<SDValue, 32> &OutVals = CLI.OutVals; 621 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins; 622 SDValue Chain = CLI.Chain; 623 SDValue Callee = CLI.Callee; 624 bool &isTailCall = CLI.IsTailCall; 625 CallingConv::ID CallConv = CLI.CallConv; 626 bool isVarArg = CLI.IsVarArg; 627 628 // Sparc target does not yet support tail call optimization. 629 isTailCall = false; 630 631 // Analyze operands of the call, assigning locations to each operand. 632 SmallVector<CCValAssign, 16> ArgLocs; 633 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 634 DAG.getTarget(), ArgLocs, *DAG.getContext()); 635 CCInfo.AnalyzeCallOperands(Outs, CC_Sparc32); 636 637 // Get the size of the outgoing arguments stack space requirement. 638 unsigned ArgsSize = CCInfo.getNextStackOffset(); 639 640 // Keep stack frames 8-byte aligned. 641 ArgsSize = (ArgsSize+7) & ~7; 642 643 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 644 645 //Create local copies for byval args. 646 SmallVector<SDValue, 8> ByValArgs; 647 for (unsigned i = 0, e = Outs.size(); i != e; ++i) { 648 ISD::ArgFlagsTy Flags = Outs[i].Flags; 649 if (!Flags.isByVal()) 650 continue; 651 652 SDValue Arg = OutVals[i]; 653 unsigned Size = Flags.getByValSize(); 654 unsigned Align = Flags.getByValAlign(); 655 656 int FI = MFI->CreateStackObject(Size, Align, false); 657 SDValue FIPtr = DAG.getFrameIndex(FI, getPointerTy()); 658 SDValue SizeNode = DAG.getConstant(Size, MVT::i32); 659 660 Chain = DAG.getMemcpy(Chain, dl, FIPtr, Arg, SizeNode, Align, 661 false, //isVolatile, 662 (Size <= 32), //AlwaysInline if size <= 32 663 MachinePointerInfo(), MachinePointerInfo()); 664 ByValArgs.push_back(FIPtr); 665 } 666 667 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 668 669 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 670 SmallVector<SDValue, 8> MemOpChains; 671 672 const unsigned StackOffset = 92; 673 bool hasStructRetAttr = false; 674 // Walk the register/memloc assignments, inserting copies/loads. 675 for (unsigned i = 0, realArgIdx = 0, byvalArgIdx = 0, e = ArgLocs.size(); 676 i != e; 677 ++i, ++realArgIdx) { 678 CCValAssign &VA = ArgLocs[i]; 679 SDValue Arg = OutVals[realArgIdx]; 680 681 ISD::ArgFlagsTy Flags = Outs[realArgIdx].Flags; 682 683 //Use local copy if it is a byval arg. 684 if (Flags.isByVal()) 685 Arg = ByValArgs[byvalArgIdx++]; 686 687 // Promote the value if needed. 688 switch (VA.getLocInfo()) { 689 default: llvm_unreachable("Unknown loc info!"); 690 case CCValAssign::Full: break; 691 case CCValAssign::SExt: 692 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 693 break; 694 case CCValAssign::ZExt: 695 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 696 break; 697 case CCValAssign::AExt: 698 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 699 break; 700 case CCValAssign::BCvt: 701 Arg = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), Arg); 702 break; 703 } 704 705 if (Flags.isSRet()) { 706 assert(VA.needsCustom()); 707 // store SRet argument in %sp+64 708 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 709 SDValue PtrOff = DAG.getIntPtrConstant(64); 710 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 711 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 712 MachinePointerInfo(), 713 false, false, 0)); 714 hasStructRetAttr = true; 715 continue; 716 } 717 718 if (VA.needsCustom()) { 719 assert(VA.getLocVT() == MVT::f64); 720 721 if (VA.isMemLoc()) { 722 unsigned Offset = VA.getLocMemOffset() + StackOffset; 723 //if it is double-word aligned, just store. 724 if (Offset % 8 == 0) { 725 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 726 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 727 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 728 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 729 MachinePointerInfo(), 730 false, false, 0)); 731 continue; 732 } 733 } 734 735 SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); 736 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, 737 Arg, StackPtr, MachinePointerInfo(), 738 false, false, 0); 739 // Sparc is big-endian, so the high part comes first. 740 SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 741 MachinePointerInfo(), false, false, false, 0); 742 // Increment the pointer to the other half. 743 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 744 DAG.getIntPtrConstant(4)); 745 // Load the low part. 746 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, 747 MachinePointerInfo(), false, false, false, 0); 748 749 if (VA.isRegLoc()) { 750 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Hi)); 751 assert(i+1 != e); 752 CCValAssign &NextVA = ArgLocs[++i]; 753 if (NextVA.isRegLoc()) { 754 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); 755 } else { 756 //Store the low part in stack. 757 unsigned Offset = NextVA.getLocMemOffset() + StackOffset; 758 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 759 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 760 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 761 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 762 MachinePointerInfo(), 763 false, false, 0)); 764 } 765 } else { 766 unsigned Offset = VA.getLocMemOffset() + StackOffset; 767 // Store the high part. 768 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 769 SDValue PtrOff = DAG.getIntPtrConstant(Offset); 770 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 771 MemOpChains.push_back(DAG.getStore(Chain, dl, Hi, PtrOff, 772 MachinePointerInfo(), 773 false, false, 0)); 774 // Store the low part. 775 PtrOff = DAG.getIntPtrConstant(Offset+4); 776 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 777 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, 778 MachinePointerInfo(), 779 false, false, 0)); 780 } 781 continue; 782 } 783 784 // Arguments that can be passed on register must be kept at 785 // RegsToPass vector 786 if (VA.isRegLoc()) { 787 if (VA.getLocVT() != MVT::f32) { 788 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 789 continue; 790 } 791 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 792 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 793 continue; 794 } 795 796 assert(VA.isMemLoc()); 797 798 // Create a store off the stack pointer for this argument. 799 SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); 800 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+StackOffset); 801 PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); 802 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 803 MachinePointerInfo(), 804 false, false, 0)); 805 } 806 807 808 // Emit all stores, make sure the occur before any copies into physregs. 809 if (!MemOpChains.empty()) 810 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 811 &MemOpChains[0], MemOpChains.size()); 812 813 // Build a sequence of copy-to-reg nodes chained together with token 814 // chain and flag operands which copy the outgoing args into registers. 815 // The InFlag in necessary since all emitted instructions must be 816 // stuck together. 817 SDValue InFlag; 818 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 819 unsigned Reg = toCallerWindow(RegsToPass[i].first); 820 Chain = DAG.getCopyToReg(Chain, dl, Reg, RegsToPass[i].second, InFlag); 821 InFlag = Chain.getValue(1); 822 } 823 824 unsigned SRetArgSize = (hasStructRetAttr)? getSRetArgSize(DAG, Callee):0; 825 826 // If the callee is a GlobalAddress node (quite common, every direct call is) 827 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 828 // Likewise ExternalSymbol -> TargetExternalSymbol. 829 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 830 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 831 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 832 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 833 834 // Returns a chain & a flag for retval copy to use 835 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 836 SmallVector<SDValue, 8> Ops; 837 Ops.push_back(Chain); 838 Ops.push_back(Callee); 839 if (hasStructRetAttr) 840 Ops.push_back(DAG.getTargetConstant(SRetArgSize, MVT::i32)); 841 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 842 Ops.push_back(DAG.getRegister(toCallerWindow(RegsToPass[i].first), 843 RegsToPass[i].second.getValueType())); 844 if (InFlag.getNode()) 845 Ops.push_back(InFlag); 846 847 Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 848 InFlag = Chain.getValue(1); 849 850 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 851 DAG.getIntPtrConstant(0, true), InFlag); 852 InFlag = Chain.getValue(1); 853 854 // Assign locations to each value returned by this call. 855 SmallVector<CCValAssign, 16> RVLocs; 856 CCState RVInfo(CallConv, isVarArg, DAG.getMachineFunction(), 857 DAG.getTarget(), RVLocs, *DAG.getContext()); 858 859 RVInfo.AnalyzeCallResult(Ins, RetCC_Sparc32); 860 861 // Copy all of the result registers out of their specified physreg. 862 for (unsigned i = 0; i != RVLocs.size(); ++i) { 863 Chain = DAG.getCopyFromReg(Chain, dl, toCallerWindow(RVLocs[i].getLocReg()), 864 RVLocs[i].getValVT(), InFlag).getValue(1); 865 InFlag = Chain.getValue(2); 866 InVals.push_back(Chain.getValue(0)); 867 } 868 869 return Chain; 870} 871 872unsigned 873SparcTargetLowering::getSRetArgSize(SelectionDAG &DAG, SDValue Callee) const 874{ 875 const Function *CalleeFn = 0; 876 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 877 CalleeFn = dyn_cast<Function>(G->getGlobal()); 878 } else if (ExternalSymbolSDNode *E = 879 dyn_cast<ExternalSymbolSDNode>(Callee)) { 880 const Function *Fn = DAG.getMachineFunction().getFunction(); 881 const Module *M = Fn->getParent(); 882 CalleeFn = M->getFunction(E->getSymbol()); 883 } 884 885 if (!CalleeFn) 886 return 0; 887 888 assert(CalleeFn->hasStructRetAttr() && 889 "Callee does not have the StructRet attribute."); 890 891 PointerType *Ty = cast<PointerType>(CalleeFn->arg_begin()->getType()); 892 Type *ElementTy = Ty->getElementType(); 893 return getDataLayout()->getTypeAllocSize(ElementTy); 894} 895 896// Lower a call for the 64-bit ABI. 897SDValue 898SparcTargetLowering::LowerCall_64(TargetLowering::CallLoweringInfo &CLI, 899 SmallVectorImpl<SDValue> &InVals) const { 900 SelectionDAG &DAG = CLI.DAG; 901 DebugLoc DL = CLI.DL; 902 SDValue Chain = CLI.Chain; 903 904 // Analyze operands of the call, assigning locations to each operand. 905 SmallVector<CCValAssign, 16> ArgLocs; 906 CCState CCInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 907 DAG.getTarget(), ArgLocs, *DAG.getContext()); 908 CCInfo.AnalyzeCallOperands(CLI.Outs, CC_Sparc64); 909 910 // Get the size of the outgoing arguments stack space requirement. 911 // The stack offset computed by CC_Sparc64 includes all arguments. 912 // Called functions expect 6 argument words to exist in the stack frame, used 913 // or not. 914 unsigned ArgsSize = std::max(6*8u, CCInfo.getNextStackOffset()); 915 916 // Keep stack frames 16-byte aligned. 917 ArgsSize = RoundUpToAlignment(ArgsSize, 16); 918 919 // Adjust the stack pointer to make room for the arguments. 920 // FIXME: Use hasReservedCallFrame to avoid %sp adjustments around all calls 921 // with more than 6 arguments. 922 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(ArgsSize, true)); 923 924 // Collect the set of registers to pass to the function and their values. 925 // This will be emitted as a sequence of CopyToReg nodes glued to the call 926 // instruction. 927 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 928 929 // Collect chains from all the memory opeations that copy arguments to the 930 // stack. They must follow the stack pointer adjustment above and precede the 931 // call instruction itself. 932 SmallVector<SDValue, 8> MemOpChains; 933 934 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 935 const CCValAssign &VA = ArgLocs[i]; 936 SDValue Arg = CLI.OutVals[i]; 937 938 // Promote the value if needed. 939 switch (VA.getLocInfo()) { 940 default: 941 llvm_unreachable("Unknown location info!"); 942 case CCValAssign::Full: 943 break; 944 case CCValAssign::SExt: 945 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); 946 break; 947 case CCValAssign::ZExt: 948 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); 949 break; 950 case CCValAssign::AExt: 951 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); 952 break; 953 case CCValAssign::BCvt: 954 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg); 955 break; 956 } 957 958 if (VA.isRegLoc()) { 959 // The custom bit on an i32 return value indicates that it should be 960 // passed in the high bits of the register. 961 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) { 962 Arg = DAG.getNode(ISD::SHL, DL, MVT::i64, Arg, 963 DAG.getConstant(32, MVT::i32)); 964 965 // The next value may go in the low bits of the same register. 966 // Handle both at once. 967 if (i+1 < ArgLocs.size() && ArgLocs[i+1].isRegLoc() && 968 ArgLocs[i+1].getLocReg() == VA.getLocReg()) { 969 SDValue NV = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, 970 CLI.OutVals[i+1]); 971 Arg = DAG.getNode(ISD::OR, DL, MVT::i64, Arg, NV); 972 // Skip the next value, it's already done. 973 ++i; 974 } 975 } 976 RegsToPass.push_back(std::make_pair(toCallerWindow(VA.getLocReg()), Arg)); 977 continue; 978 } 979 980 assert(VA.isMemLoc()); 981 982 // Create a store off the stack pointer for this argument. 983 SDValue StackPtr = DAG.getRegister(SP::O6, getPointerTy()); 984 // The argument area starts at %fp+BIAS+128 in the callee frame, 985 // %sp+BIAS+128 in ours. 986 SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset() + 987 Subtarget->getStackPointerBias() + 988 128); 989 PtrOff = DAG.getNode(ISD::ADD, DL, getPointerTy(), StackPtr, PtrOff); 990 MemOpChains.push_back(DAG.getStore(Chain, DL, Arg, PtrOff, 991 MachinePointerInfo(), 992 false, false, 0)); 993 } 994 995 // Emit all stores, make sure they occur before the call. 996 if (!MemOpChains.empty()) 997 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 998 &MemOpChains[0], MemOpChains.size()); 999 1000 // Build a sequence of CopyToReg nodes glued together with token chain and 1001 // glue operands which copy the outgoing args into registers. The InGlue is 1002 // necessary since all emitted instructions must be stuck together in order 1003 // to pass the live physical registers. 1004 SDValue InGlue; 1005 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 1006 Chain = DAG.getCopyToReg(Chain, DL, 1007 RegsToPass[i].first, RegsToPass[i].second, InGlue); 1008 InGlue = Chain.getValue(1); 1009 } 1010 1011 // If the callee is a GlobalAddress node (quite common, every direct call is) 1012 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. 1013 // Likewise ExternalSymbol -> TargetExternalSymbol. 1014 SDValue Callee = CLI.Callee; 1015 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) 1016 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, getPointerTy()); 1017 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) 1018 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); 1019 1020 // Build the operands for the call instruction itself. 1021 SmallVector<SDValue, 8> Ops; 1022 Ops.push_back(Chain); 1023 Ops.push_back(Callee); 1024 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 1025 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 1026 RegsToPass[i].second.getValueType())); 1027 1028 // Make sure the CopyToReg nodes are glued to the call instruction which 1029 // consumes the registers. 1030 if (InGlue.getNode()) 1031 Ops.push_back(InGlue); 1032 1033 // Now the call itself. 1034 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 1035 Chain = DAG.getNode(SPISD::CALL, DL, NodeTys, &Ops[0], Ops.size()); 1036 InGlue = Chain.getValue(1); 1037 1038 // Revert the stack pointer immediately after the call. 1039 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), 1040 DAG.getIntPtrConstant(0, true), InGlue); 1041 InGlue = Chain.getValue(1); 1042 1043 // Now extract the return values. This is more or less the same as 1044 // LowerFormalArguments_64. 1045 1046 // Assign locations to each value returned by this call. 1047 SmallVector<CCValAssign, 16> RVLocs; 1048 CCState RVInfo(CLI.CallConv, CLI.IsVarArg, DAG.getMachineFunction(), 1049 DAG.getTarget(), RVLocs, *DAG.getContext()); 1050 RVInfo.AnalyzeCallResult(CLI.Ins, CC_Sparc64); 1051 1052 // Copy all of the result registers out of their specified physreg. 1053 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1054 CCValAssign &VA = RVLocs[i]; 1055 unsigned Reg = toCallerWindow(VA.getLocReg()); 1056 1057 // When returning 'inreg {i32, i32 }', two consecutive i32 arguments can 1058 // reside in the same register in the high and low bits. Reuse the 1059 // CopyFromReg previous node to avoid duplicate copies. 1060 SDValue RV; 1061 if (RegisterSDNode *SrcReg = dyn_cast<RegisterSDNode>(Chain.getOperand(1))) 1062 if (SrcReg->getReg() == Reg && Chain->getOpcode() == ISD::CopyFromReg) 1063 RV = Chain.getValue(0); 1064 1065 // But usually we'll create a new CopyFromReg for a different register. 1066 if (!RV.getNode()) { 1067 RV = DAG.getCopyFromReg(Chain, DL, Reg, RVLocs[i].getLocVT(), InGlue); 1068 Chain = RV.getValue(1); 1069 InGlue = Chain.getValue(2); 1070 } 1071 1072 // Get the high bits for i32 struct elements. 1073 if (VA.getValVT() == MVT::i32 && VA.needsCustom()) 1074 RV = DAG.getNode(ISD::SRL, DL, VA.getLocVT(), RV, 1075 DAG.getConstant(32, MVT::i32)); 1076 1077 // The callee promoted the return value, so insert an Assert?ext SDNode so 1078 // we won't promote the value again in this function. 1079 switch (VA.getLocInfo()) { 1080 case CCValAssign::SExt: 1081 RV = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), RV, 1082 DAG.getValueType(VA.getValVT())); 1083 break; 1084 case CCValAssign::ZExt: 1085 RV = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), RV, 1086 DAG.getValueType(VA.getValVT())); 1087 break; 1088 default: 1089 break; 1090 } 1091 1092 // Truncate the register down to the return value type. 1093 if (VA.isExtInLoc()) 1094 RV = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), RV); 1095 1096 InVals.push_back(RV); 1097 } 1098 1099 return Chain; 1100} 1101 1102//===----------------------------------------------------------------------===// 1103// TargetLowering Implementation 1104//===----------------------------------------------------------------------===// 1105 1106/// IntCondCCodeToICC - Convert a DAG integer condition code to a SPARC ICC 1107/// condition. 1108static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { 1109 switch (CC) { 1110 default: llvm_unreachable("Unknown integer condition code!"); 1111 case ISD::SETEQ: return SPCC::ICC_E; 1112 case ISD::SETNE: return SPCC::ICC_NE; 1113 case ISD::SETLT: return SPCC::ICC_L; 1114 case ISD::SETGT: return SPCC::ICC_G; 1115 case ISD::SETLE: return SPCC::ICC_LE; 1116 case ISD::SETGE: return SPCC::ICC_GE; 1117 case ISD::SETULT: return SPCC::ICC_CS; 1118 case ISD::SETULE: return SPCC::ICC_LEU; 1119 case ISD::SETUGT: return SPCC::ICC_GU; 1120 case ISD::SETUGE: return SPCC::ICC_CC; 1121 } 1122} 1123 1124/// FPCondCCodeToFCC - Convert a DAG floatingp oint condition code to a SPARC 1125/// FCC condition. 1126static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { 1127 switch (CC) { 1128 default: llvm_unreachable("Unknown fp condition code!"); 1129 case ISD::SETEQ: 1130 case ISD::SETOEQ: return SPCC::FCC_E; 1131 case ISD::SETNE: 1132 case ISD::SETUNE: return SPCC::FCC_NE; 1133 case ISD::SETLT: 1134 case ISD::SETOLT: return SPCC::FCC_L; 1135 case ISD::SETGT: 1136 case ISD::SETOGT: return SPCC::FCC_G; 1137 case ISD::SETLE: 1138 case ISD::SETOLE: return SPCC::FCC_LE; 1139 case ISD::SETGE: 1140 case ISD::SETOGE: return SPCC::FCC_GE; 1141 case ISD::SETULT: return SPCC::FCC_UL; 1142 case ISD::SETULE: return SPCC::FCC_ULE; 1143 case ISD::SETUGT: return SPCC::FCC_UG; 1144 case ISD::SETUGE: return SPCC::FCC_UGE; 1145 case ISD::SETUO: return SPCC::FCC_U; 1146 case ISD::SETO: return SPCC::FCC_O; 1147 case ISD::SETONE: return SPCC::FCC_LG; 1148 case ISD::SETUEQ: return SPCC::FCC_UE; 1149 } 1150} 1151 1152SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) 1153 : TargetLowering(TM, new TargetLoweringObjectFileELF()) { 1154 Subtarget = &TM.getSubtarget<SparcSubtarget>(); 1155 1156 // Set up the register classes. 1157 addRegisterClass(MVT::i32, &SP::IntRegsRegClass); 1158 addRegisterClass(MVT::f32, &SP::FPRegsRegClass); 1159 addRegisterClass(MVT::f64, &SP::DFPRegsRegClass); 1160 if (Subtarget->is64Bit()) 1161 addRegisterClass(MVT::i64, &SP::I64RegsRegClass); 1162 1163 // Turn FP extload into load/fextend 1164 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 1165 // Sparc doesn't have i1 sign extending load 1166 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 1167 // Turn FP truncstore into trunc + store. 1168 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 1169 1170 // Custom legalize GlobalAddress nodes into LO/HI parts. 1171 setOperationAction(ISD::GlobalAddress, getPointerTy(), Custom); 1172 setOperationAction(ISD::GlobalTLSAddress, getPointerTy(), Custom); 1173 setOperationAction(ISD::ConstantPool, getPointerTy(), Custom); 1174 1175 // Sparc doesn't have sext_inreg, replace them with shl/sra 1176 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 1177 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); 1178 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 1179 1180 // Sparc has no REM or DIVREM operations. 1181 setOperationAction(ISD::UREM, MVT::i32, Expand); 1182 setOperationAction(ISD::SREM, MVT::i32, Expand); 1183 setOperationAction(ISD::SDIVREM, MVT::i32, Expand); 1184 setOperationAction(ISD::UDIVREM, MVT::i32, Expand); 1185 1186 // Custom expand fp<->sint 1187 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); 1188 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); 1189 1190 // Expand fp<->uint 1191 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 1192 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 1193 1194 setOperationAction(ISD::BITCAST, MVT::f32, Expand); 1195 setOperationAction(ISD::BITCAST, MVT::i32, Expand); 1196 1197 // Sparc has no select or setcc: expand to SELECT_CC. 1198 setOperationAction(ISD::SELECT, MVT::i32, Expand); 1199 setOperationAction(ISD::SELECT, MVT::f32, Expand); 1200 setOperationAction(ISD::SELECT, MVT::f64, Expand); 1201 setOperationAction(ISD::SETCC, MVT::i32, Expand); 1202 setOperationAction(ISD::SETCC, MVT::f32, Expand); 1203 setOperationAction(ISD::SETCC, MVT::f64, Expand); 1204 1205 // Sparc doesn't have BRCOND either, it has BR_CC. 1206 setOperationAction(ISD::BRCOND, MVT::Other, Expand); 1207 setOperationAction(ISD::BRIND, MVT::Other, Expand); 1208 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 1209 setOperationAction(ISD::BR_CC, MVT::i32, Custom); 1210 setOperationAction(ISD::BR_CC, MVT::f32, Custom); 1211 setOperationAction(ISD::BR_CC, MVT::f64, Custom); 1212 1213 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); 1214 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); 1215 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); 1216 1217 if (Subtarget->is64Bit()) { 1218 setOperationAction(ISD::BR_CC, MVT::i64, Custom); 1219 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); 1220 } 1221 1222 // FIXME: There are instructions available for ATOMIC_FENCE 1223 // on SparcV8 and later. 1224 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); 1225 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Expand); 1226 1227 setOperationAction(ISD::FSIN , MVT::f64, Expand); 1228 setOperationAction(ISD::FCOS , MVT::f64, Expand); 1229 setOperationAction(ISD::FSINCOS, MVT::f64, Expand); 1230 setOperationAction(ISD::FREM , MVT::f64, Expand); 1231 setOperationAction(ISD::FMA , MVT::f64, Expand); 1232 setOperationAction(ISD::FSIN , MVT::f32, Expand); 1233 setOperationAction(ISD::FCOS , MVT::f32, Expand); 1234 setOperationAction(ISD::FSINCOS, MVT::f32, Expand); 1235 setOperationAction(ISD::FREM , MVT::f32, Expand); 1236 setOperationAction(ISD::FMA , MVT::f32, Expand); 1237 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 1238 setOperationAction(ISD::CTTZ , MVT::i32, Expand); 1239 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand); 1240 setOperationAction(ISD::CTLZ , MVT::i32, Expand); 1241 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand); 1242 setOperationAction(ISD::ROTL , MVT::i32, Expand); 1243 setOperationAction(ISD::ROTR , MVT::i32, Expand); 1244 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 1245 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 1246 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 1247 setOperationAction(ISD::FPOW , MVT::f64, Expand); 1248 setOperationAction(ISD::FPOW , MVT::f32, Expand); 1249 1250 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 1251 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 1252 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 1253 1254 // FIXME: Sparc provides these multiplies, but we don't have them yet. 1255 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); 1256 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); 1257 1258 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 1259 1260 // VASTART needs to be custom lowered to use the VarArgsFrameIndex. 1261 setOperationAction(ISD::VASTART , MVT::Other, Custom); 1262 // VAARG needs to be lowered to not do unaligned accesses for doubles. 1263 setOperationAction(ISD::VAARG , MVT::Other, Custom); 1264 1265 // Use the default implementation. 1266 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 1267 setOperationAction(ISD::VAEND , MVT::Other, Expand); 1268 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); 1269 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); 1270 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); 1271 1272 // No debug info support yet. 1273 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 1274 1275 setStackPointerRegisterToSaveRestore(SP::O6); 1276 1277 if (TM.getSubtarget<SparcSubtarget>().isV9()) 1278 setOperationAction(ISD::CTPOP, MVT::i32, Legal); 1279 1280 setMinFunctionAlignment(2); 1281 1282 computeRegisterProperties(); 1283} 1284 1285const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const { 1286 switch (Opcode) { 1287 default: return 0; 1288 case SPISD::CMPICC: return "SPISD::CMPICC"; 1289 case SPISD::CMPFCC: return "SPISD::CMPFCC"; 1290 case SPISD::BRICC: return "SPISD::BRICC"; 1291 case SPISD::BRXCC: return "SPISD::BRXCC"; 1292 case SPISD::BRFCC: return "SPISD::BRFCC"; 1293 case SPISD::SELECT_ICC: return "SPISD::SELECT_ICC"; 1294 case SPISD::SELECT_XCC: return "SPISD::SELECT_XCC"; 1295 case SPISD::SELECT_FCC: return "SPISD::SELECT_FCC"; 1296 case SPISD::Hi: return "SPISD::Hi"; 1297 case SPISD::Lo: return "SPISD::Lo"; 1298 case SPISD::FTOI: return "SPISD::FTOI"; 1299 case SPISD::ITOF: return "SPISD::ITOF"; 1300 case SPISD::CALL: return "SPISD::CALL"; 1301 case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; 1302 case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; 1303 case SPISD::FLUSHW: return "SPISD::FLUSHW"; 1304 } 1305} 1306 1307/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to 1308/// be zero. Op is expected to be a target specific node. Used by DAG 1309/// combiner. 1310void SparcTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 1311 APInt &KnownZero, 1312 APInt &KnownOne, 1313 const SelectionDAG &DAG, 1314 unsigned Depth) const { 1315 APInt KnownZero2, KnownOne2; 1316 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0); 1317 1318 switch (Op.getOpcode()) { 1319 default: break; 1320 case SPISD::SELECT_ICC: 1321 case SPISD::SELECT_XCC: 1322 case SPISD::SELECT_FCC: 1323 DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); 1324 DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); 1325 assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); 1326 assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); 1327 1328 // Only known if known in both the LHS and RHS. 1329 KnownOne &= KnownOne2; 1330 KnownZero &= KnownZero2; 1331 break; 1332 } 1333} 1334 1335// Look at LHS/RHS/CC and see if they are a lowered setcc instruction. If so 1336// set LHS/RHS and SPCC to the LHS/RHS of the setcc and SPCC to the condition. 1337static void LookThroughSetCC(SDValue &LHS, SDValue &RHS, 1338 ISD::CondCode CC, unsigned &SPCC) { 1339 if (isa<ConstantSDNode>(RHS) && 1340 cast<ConstantSDNode>(RHS)->isNullValue() && 1341 CC == ISD::SETNE && 1342 (((LHS.getOpcode() == SPISD::SELECT_ICC || 1343 LHS.getOpcode() == SPISD::SELECT_XCC) && 1344 LHS.getOperand(3).getOpcode() == SPISD::CMPICC) || 1345 (LHS.getOpcode() == SPISD::SELECT_FCC && 1346 LHS.getOperand(3).getOpcode() == SPISD::CMPFCC)) && 1347 isa<ConstantSDNode>(LHS.getOperand(0)) && 1348 isa<ConstantSDNode>(LHS.getOperand(1)) && 1349 cast<ConstantSDNode>(LHS.getOperand(0))->isOne() && 1350 cast<ConstantSDNode>(LHS.getOperand(1))->isNullValue()) { 1351 SDValue CMPCC = LHS.getOperand(3); 1352 SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue(); 1353 LHS = CMPCC.getOperand(0); 1354 RHS = CMPCC.getOperand(1); 1355 } 1356} 1357 1358// Convert to a target node and set target flags. 1359SDValue SparcTargetLowering::withTargetFlags(SDValue Op, unsigned TF, 1360 SelectionDAG &DAG) const { 1361 if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) 1362 return DAG.getTargetGlobalAddress(GA->getGlobal(), 1363 GA->getDebugLoc(), 1364 GA->getValueType(0), 1365 GA->getOffset(), TF); 1366 1367 if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op)) 1368 return DAG.getTargetConstantPool(CP->getConstVal(), 1369 CP->getValueType(0), 1370 CP->getAlignment(), 1371 CP->getOffset(), TF); 1372 1373 if (const ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Op)) 1374 return DAG.getTargetExternalSymbol(ES->getSymbol(), 1375 ES->getValueType(0), TF); 1376 1377 llvm_unreachable("Unhandled address SDNode"); 1378} 1379 1380// Split Op into high and low parts according to HiTF and LoTF. 1381// Return an ADD node combining the parts. 1382SDValue SparcTargetLowering::makeHiLoPair(SDValue Op, 1383 unsigned HiTF, unsigned LoTF, 1384 SelectionDAG &DAG) const { 1385 DebugLoc DL = Op.getDebugLoc(); 1386 EVT VT = Op.getValueType(); 1387 SDValue Hi = DAG.getNode(SPISD::Hi, DL, VT, withTargetFlags(Op, HiTF, DAG)); 1388 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG)); 1389 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); 1390} 1391 1392// Build SDNodes for producing an address from a GlobalAddress, ConstantPool, 1393// or ExternalSymbol SDNode. 1394SDValue SparcTargetLowering::makeAddress(SDValue Op, SelectionDAG &DAG) const { 1395 DebugLoc DL = Op.getDebugLoc(); 1396 EVT VT = getPointerTy(); 1397 1398 // Handle PIC mode first. 1399 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1400 // This is the pic32 code model, the GOT is known to be smaller than 4GB. 1401 SDValue HiLo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG); 1402 SDValue GlobalBase = DAG.getNode(SPISD::GLOBAL_BASE_REG, DL, VT); 1403 SDValue AbsAddr = DAG.getNode(ISD::ADD, DL, VT, GlobalBase, HiLo); 1404 return DAG.getLoad(VT, DL, DAG.getEntryNode(), AbsAddr, 1405 MachinePointerInfo::getGOT(), false, false, false, 0); 1406 } 1407 1408 // This is one of the absolute code models. 1409 switch(getTargetMachine().getCodeModel()) { 1410 default: 1411 llvm_unreachable("Unsupported absolute code model"); 1412 case CodeModel::Small: 1413 // abs32. 1414 return makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG); 1415 case CodeModel::Medium: { 1416 // abs44. 1417 SDValue H44 = makeHiLoPair(Op, SPII::MO_H44, SPII::MO_M44, DAG); 1418 H44 = DAG.getNode(ISD::SHL, DL, VT, H44, DAG.getConstant(12, MVT::i32)); 1419 SDValue L44 = withTargetFlags(Op, SPII::MO_L44, DAG); 1420 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44); 1421 return DAG.getNode(ISD::ADD, DL, VT, H44, L44); 1422 } 1423 case CodeModel::Large: { 1424 // abs64. 1425 SDValue Hi = makeHiLoPair(Op, SPII::MO_HH, SPII::MO_HM, DAG); 1426 Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, DAG.getConstant(32, MVT::i32)); 1427 SDValue Lo = makeHiLoPair(Op, SPII::MO_HI, SPII::MO_LO, DAG); 1428 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); 1429 } 1430 } 1431} 1432 1433SDValue SparcTargetLowering::LowerGlobalAddress(SDValue Op, 1434 SelectionDAG &DAG) const { 1435 return makeAddress(Op, DAG); 1436} 1437 1438SDValue SparcTargetLowering::LowerConstantPool(SDValue Op, 1439 SelectionDAG &DAG) const { 1440 return makeAddress(Op, DAG); 1441} 1442 1443static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { 1444 DebugLoc dl = Op.getDebugLoc(); 1445 // Convert the fp value to integer in an FP register. 1446 assert(Op.getValueType() == MVT::i32); 1447 Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); 1448 return DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 1449} 1450 1451static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { 1452 DebugLoc dl = Op.getDebugLoc(); 1453 assert(Op.getOperand(0).getValueType() == MVT::i32); 1454 SDValue Tmp = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Op.getOperand(0)); 1455 // Convert the int value to FP in an FP register. 1456 return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp); 1457} 1458 1459static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { 1460 SDValue Chain = Op.getOperand(0); 1461 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); 1462 SDValue LHS = Op.getOperand(2); 1463 SDValue RHS = Op.getOperand(3); 1464 SDValue Dest = Op.getOperand(4); 1465 DebugLoc dl = Op.getDebugLoc(); 1466 unsigned Opc, SPCC = ~0U; 1467 1468 // If this is a br_cc of a "setcc", and if the setcc got lowered into 1469 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 1470 LookThroughSetCC(LHS, RHS, CC, SPCC); 1471 1472 // Get the condition flag. 1473 SDValue CompareFlag; 1474 if (LHS.getValueType().isInteger()) { 1475 EVT VTs[] = { LHS.getValueType(), MVT::Glue }; 1476 SDValue Ops[2] = { LHS, RHS }; 1477 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 1478 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 1479 // 32-bit compares use the icc flags, 64-bit uses the xcc flags. 1480 Opc = LHS.getValueType() == MVT::i32 ? SPISD::BRICC : SPISD::BRXCC; 1481 } else { 1482 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 1483 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 1484 Opc = SPISD::BRFCC; 1485 } 1486 return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, 1487 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 1488} 1489 1490static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { 1491 SDValue LHS = Op.getOperand(0); 1492 SDValue RHS = Op.getOperand(1); 1493 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); 1494 SDValue TrueVal = Op.getOperand(2); 1495 SDValue FalseVal = Op.getOperand(3); 1496 DebugLoc dl = Op.getDebugLoc(); 1497 unsigned Opc, SPCC = ~0U; 1498 1499 // If this is a select_cc of a "setcc", and if the setcc got lowered into 1500 // an CMP[IF]CC/SELECT_[IF]CC pair, find the original compared values. 1501 LookThroughSetCC(LHS, RHS, CC, SPCC); 1502 1503 SDValue CompareFlag; 1504 if (LHS.getValueType().isInteger()) { 1505 // subcc returns a value 1506 EVT VTs[] = { LHS.getValueType(), MVT::Glue }; 1507 SDValue Ops[2] = { LHS, RHS }; 1508 CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); 1509 Opc = LHS.getValueType() == MVT::i32 ? 1510 SPISD::SELECT_ICC : SPISD::SELECT_XCC; 1511 if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); 1512 } else { 1513 CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Glue, LHS, RHS); 1514 Opc = SPISD::SELECT_FCC; 1515 if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); 1516 } 1517 return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, 1518 DAG.getConstant(SPCC, MVT::i32), CompareFlag); 1519} 1520 1521static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, 1522 const SparcTargetLowering &TLI) { 1523 MachineFunction &MF = DAG.getMachineFunction(); 1524 SparcMachineFunctionInfo *FuncInfo = MF.getInfo<SparcMachineFunctionInfo>(); 1525 1526 // vastart just stores the address of the VarArgsFrameIndex slot into the 1527 // memory location argument. 1528 DebugLoc dl = Op.getDebugLoc(); 1529 SDValue Offset = 1530 DAG.getNode(ISD::ADD, dl, MVT::i32, 1531 DAG.getRegister(SP::I6, MVT::i32), 1532 DAG.getConstant(FuncInfo->getVarArgsFrameOffset(), 1533 MVT::i32)); 1534 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1535 return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), 1536 MachinePointerInfo(SV), false, false, 0); 1537} 1538 1539static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { 1540 SDNode *Node = Op.getNode(); 1541 EVT VT = Node->getValueType(0); 1542 SDValue InChain = Node->getOperand(0); 1543 SDValue VAListPtr = Node->getOperand(1); 1544 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 1545 DebugLoc dl = Node->getDebugLoc(); 1546 SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, 1547 MachinePointerInfo(SV), false, false, false, 0); 1548 // Increment the pointer, VAList, to the next vaarg 1549 SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, 1550 DAG.getConstant(VT.getSizeInBits()/8, 1551 MVT::i32)); 1552 // Store the incremented VAList to the legalized pointer 1553 InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr, 1554 VAListPtr, MachinePointerInfo(SV), false, false, 0); 1555 // Load the actual argument out of the pointer VAList, unless this is an 1556 // f64 load. 1557 if (VT != MVT::f64) 1558 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(), 1559 false, false, false, 0); 1560 1561 // Otherwise, load it as i64, then do a bitconvert. 1562 SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, MachinePointerInfo(), 1563 false, false, false, 0); 1564 1565 // Bit-Convert the value to f64. 1566 SDValue Ops[2] = { 1567 DAG.getNode(ISD::BITCAST, dl, MVT::f64, V), 1568 V.getValue(1) 1569 }; 1570 return DAG.getMergeValues(Ops, 2, dl); 1571} 1572 1573static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { 1574 SDValue Chain = Op.getOperand(0); // Legalize the chain. 1575 SDValue Size = Op.getOperand(1); // Legalize the size. 1576 DebugLoc dl = Op.getDebugLoc(); 1577 1578 unsigned SPReg = SP::O6; 1579 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); 1580 SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value 1581 Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain 1582 1583 // The resultant pointer is actually 16 words from the bottom of the stack, 1584 // to provide a register spill area. 1585 SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, 1586 DAG.getConstant(96, MVT::i32)); 1587 SDValue Ops[2] = { NewVal, Chain }; 1588 return DAG.getMergeValues(Ops, 2, dl); 1589} 1590 1591 1592static SDValue getFLUSHW(SDValue Op, SelectionDAG &DAG) { 1593 DebugLoc dl = Op.getDebugLoc(); 1594 SDValue Chain = DAG.getNode(SPISD::FLUSHW, 1595 dl, MVT::Other, DAG.getEntryNode()); 1596 return Chain; 1597} 1598 1599static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { 1600 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1601 MFI->setFrameAddressIsTaken(true); 1602 1603 EVT VT = Op.getValueType(); 1604 DebugLoc dl = Op.getDebugLoc(); 1605 unsigned FrameReg = SP::I6; 1606 1607 uint64_t depth = Op.getConstantOperandVal(0); 1608 1609 SDValue FrameAddr; 1610 if (depth == 0) 1611 FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 1612 else { 1613 // flush first to make sure the windowed registers' values are in stack 1614 SDValue Chain = getFLUSHW(Op, DAG); 1615 FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); 1616 1617 for (uint64_t i = 0; i != depth; ++i) { 1618 SDValue Ptr = DAG.getNode(ISD::ADD, 1619 dl, MVT::i32, 1620 FrameAddr, DAG.getIntPtrConstant(56)); 1621 FrameAddr = DAG.getLoad(MVT::i32, dl, 1622 Chain, 1623 Ptr, 1624 MachinePointerInfo(), false, false, false, 0); 1625 } 1626 } 1627 return FrameAddr; 1628} 1629 1630static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { 1631 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1632 MFI->setReturnAddressIsTaken(true); 1633 1634 EVT VT = Op.getValueType(); 1635 DebugLoc dl = Op.getDebugLoc(); 1636 unsigned RetReg = SP::I7; 1637 1638 uint64_t depth = Op.getConstantOperandVal(0); 1639 1640 SDValue RetAddr; 1641 if (depth == 0) 1642 RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); 1643 else { 1644 // flush first to make sure the windowed registers' values are in stack 1645 SDValue Chain = getFLUSHW(Op, DAG); 1646 RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT); 1647 1648 for (uint64_t i = 0; i != depth; ++i) { 1649 SDValue Ptr = DAG.getNode(ISD::ADD, 1650 dl, MVT::i32, 1651 RetAddr, 1652 DAG.getIntPtrConstant((i == depth-1)?60:56)); 1653 RetAddr = DAG.getLoad(MVT::i32, dl, 1654 Chain, 1655 Ptr, 1656 MachinePointerInfo(), false, false, false, 0); 1657 } 1658 } 1659 return RetAddr; 1660} 1661 1662SDValue SparcTargetLowering:: 1663LowerOperation(SDValue Op, SelectionDAG &DAG) const { 1664 switch (Op.getOpcode()) { 1665 default: llvm_unreachable("Should not custom lower this!"); 1666 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 1667 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 1668 case ISD::GlobalTLSAddress: 1669 llvm_unreachable("TLS not implemented for Sparc."); 1670 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 1671 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 1672 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 1673 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 1674 case ISD::BR_CC: return LowerBR_CC(Op, DAG); 1675 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); 1676 case ISD::VASTART: return LowerVASTART(Op, DAG, *this); 1677 case ISD::VAARG: return LowerVAARG(Op, DAG); 1678 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 1679 } 1680} 1681 1682MachineBasicBlock * 1683SparcTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1684 MachineBasicBlock *BB) const { 1685 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo(); 1686 unsigned BROpcode; 1687 unsigned CC; 1688 DebugLoc dl = MI->getDebugLoc(); 1689 // Figure out the conditional branch opcode to use for this select_cc. 1690 switch (MI->getOpcode()) { 1691 default: llvm_unreachable("Unknown SELECT_CC!"); 1692 case SP::SELECT_CC_Int_ICC: 1693 case SP::SELECT_CC_FP_ICC: 1694 case SP::SELECT_CC_DFP_ICC: 1695 BROpcode = SP::BCOND; 1696 break; 1697 case SP::SELECT_CC_Int_FCC: 1698 case SP::SELECT_CC_FP_FCC: 1699 case SP::SELECT_CC_DFP_FCC: 1700 BROpcode = SP::FBCOND; 1701 break; 1702 } 1703 1704 CC = (SPCC::CondCodes)MI->getOperand(3).getImm(); 1705 1706 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond 1707 // control-flow pattern. The incoming instruction knows the destination vreg 1708 // to set, the condition code register to branch on, the true/false values to 1709 // select between, and a branch opcode to use. 1710 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1711 MachineFunction::iterator It = BB; 1712 ++It; 1713 1714 // thisMBB: 1715 // ... 1716 // TrueVal = ... 1717 // [f]bCC copy1MBB 1718 // fallthrough --> copy0MBB 1719 MachineBasicBlock *thisMBB = BB; 1720 MachineFunction *F = BB->getParent(); 1721 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 1722 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 1723 F->insert(It, copy0MBB); 1724 F->insert(It, sinkMBB); 1725 1726 // Transfer the remainder of BB and its successor edges to sinkMBB. 1727 sinkMBB->splice(sinkMBB->begin(), BB, 1728 llvm::next(MachineBasicBlock::iterator(MI)), 1729 BB->end()); 1730 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 1731 1732 // Add the true and fallthrough blocks as its successors. 1733 BB->addSuccessor(copy0MBB); 1734 BB->addSuccessor(sinkMBB); 1735 1736 BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC); 1737 1738 // copy0MBB: 1739 // %FalseValue = ... 1740 // # fallthrough to sinkMBB 1741 BB = copy0MBB; 1742 1743 // Update machine-CFG edges 1744 BB->addSuccessor(sinkMBB); 1745 1746 // sinkMBB: 1747 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 1748 // ... 1749 BB = sinkMBB; 1750 BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI->getOperand(0).getReg()) 1751 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB) 1752 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB); 1753 1754 MI->eraseFromParent(); // The pseudo instruction is gone now. 1755 return BB; 1756} 1757 1758//===----------------------------------------------------------------------===// 1759// Sparc Inline Assembly Support 1760//===----------------------------------------------------------------------===// 1761 1762/// getConstraintType - Given a constraint letter, return the type of 1763/// constraint it is for this target. 1764SparcTargetLowering::ConstraintType 1765SparcTargetLowering::getConstraintType(const std::string &Constraint) const { 1766 if (Constraint.size() == 1) { 1767 switch (Constraint[0]) { 1768 default: break; 1769 case 'r': return C_RegisterClass; 1770 } 1771 } 1772 1773 return TargetLowering::getConstraintType(Constraint); 1774} 1775 1776std::pair<unsigned, const TargetRegisterClass*> 1777SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 1778 EVT VT) const { 1779 if (Constraint.size() == 1) { 1780 switch (Constraint[0]) { 1781 case 'r': 1782 return std::make_pair(0U, &SP::IntRegsRegClass); 1783 } 1784 } 1785 1786 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 1787} 1788 1789bool 1790SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 1791 // The Sparc target isn't yet aware of offsets. 1792 return false; 1793} 1794